JP2000165782A - Liquid crystal driving controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a controller for a liquid crystal television for minimizing IC redesign even when the specification of the number of pixels of a liquid crystal television is changed. SOLUTION: An outside settable variable frequency-divider is inserted between a crystal oscillator and a first frequency-division circuit 2 and a second frequency-division circuit 6, and a second timing pulse generator (second TPG) 10 operating with a signal before the frequency-division of the variable frequency-divider is provided. An A/D converting circuit operates with the signal of the second TPG, and a timing pulse generator (first TPG) 3 equivalent to a conventional TPG 3 operates with the signal after the variable frequency- division or the frequency-division signal as an input clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video signal or R signal.
The present invention relates to a controller for a liquid crystal television having a main function of converting a GB signal into a signal for a liquid crystal panel driver.

[0002]

2. Description of the Related Art LCD televisions are different from CRT televisions.
Digital signals are used to drive the display device. In other words, a digital circuit whose main function is to create a digital signal for a liquid crystal panel driver in addition to A / D converting a video signal or an RGB signal is used. This is referred to as a controller for a liquid crystal television. The controller for a liquid crystal television includes a crystal oscillator or an LC oscillator as a source of a system clock, and an A / D conversion circuit that operates using an output signal of the system clock oscillator or a frequency-divided signal thereof as a reference clock signal. , A timing pulse generator (hereinafter referred to as TPG) and the like. The A / D conversion circuit A / D converts the video signal and supplies the video data as a result of the conversion to the liquid crystal panel segment driver. The TPG is a group of signals necessary for the operation of the liquid crystal panel common driver and the segment driver, such as a signal for instructing the A / D converter circuit for an operation timing and a data transfer timing signal. Create

FIG. 8 is a block diagram showing the relationship between the structure of a conventional controller for a liquid crystal television and a driver for a liquid crystal panel. In this figure, the controller 20 for the liquid crystal television is surrounded by a dotted line, and the segment driver-2 is shown.
1a, 21b, common driver 22, liquid crystal panel 23
Was shown outside of it.

[0004] Reference numeral 1 denotes a crystal oscillator as a voltage-controlled oscillator. In addition to a crystal oscillator 31, a trimmer capacitor 32, a coupling capacitor 34, and a varactor diode 33 as external components, a phase. Locked. Roux
There are resistors 37 and 35 and a capacitor 36 that constitute an integrating circuit for the loop (hereinafter referred to as a PLL). Reference numeral 2 denotes a first frequency dividing circuit for dividing the frequency of the system clock signal CLK1 from the crystal oscillator 1 and outputting a signal group CB as a basis for synthesizing various pulse signals. Reference numeral 3 denotes a control signal group CI for a common driver, a control signal group C2 for a segment driver, and an A / D conversion from the signal group CB from the first frequency dividing circuit 2. Is a TPG for synthesizing a control signal group C3. The common driver control signal C1 includes the scanning clock signal TK.
And a scan start signal or a reset signal RS.

[0005] Segment driver control signal C
2 includes a data transfer clock CLKA, a PWM reference signal PM for pulse width modulation performed by the segment drivers 21a and 21b, a timing signal PT for synchronizing with the scanning timing of the common driver 22, and the common signal. Signal PL for transmitting selection signal polarity of driver-22
And an inhibitor signal INH for temporarily suspending the output operation of the segment drivers 21a and 21b and setting the output potential to the common potential.

The A / D conversion control signal C3 includes A
In addition to the clock signal CLKB serving as a reference for the / D conversion rate, a signal CLKO serving as a data output timing reference is included.

[0007] 4 is to convert the RGB signal S1 from the outside to the T
A / D conversion is performed at the rate of the clock signal CLKB from the PG 3 to convert it into 4-bit video data D1, and
An A / D conversion circuit for converting each of R, G, and B of the RGB signal S1 into 4-bit digital data, and converts the 4-bit data of each of RGB into the data output timing signal C.
A multiplexer for sequentially outputting in accordance with LKO is included.

Reference numeral 5 is operated by the clock signal group CB from the first frequency dividing circuit 2, receives a synchronization signal SYNC from the outside, separates and outputs a horizontal synchronization signal HS and a vertical synchronization signal VS, and relatively. This is a pattern matching circuit for outputting a wide horizontal synchronizing signal HW. The time difference between the rising edge of the horizontal synchronizing signal HS and the wide horizontal synchronizing signal HW and the edge of the external synchronizing signal SYNC is kept constant. It is configured not to include an error. The horizontal synchronizing signal HS is used for resetting at least a part of the first frequency dividing circuit 2, and the vertical synchronizing signal VS is used for the TPG3.

In the above configuration, if the RGB signal SI and the synchronization signal SYNC are supplied, the device functions as a liquid crystal television and an image is displayed on a liquid crystal panel. However, since the phase of the crystal oscillator 1 is not fixed with respect to the synchronization signal SYNC, the A / D conversion data D1 and the video signal SYNC are not determined.
C is at least equal to the system clock CLK1.
, And the image is constantly shaken. To prevent this, a PLL circuit is used.

Reference numeral 6 denotes a second frequency dividing circuit for dividing the system clock signal CLK1 from the crystal oscillator 1 to the same frequency as the horizontal synchronizing signal HS. 7 detects the phase difference between the output signal HI of the second frequency dividing circuit 6 and the wide horizontal synchronizing signal HW from the pattern matching circuit 5, and detects three phases.
This is a phase comparator that outputs an output signal PD of the target.

The three-state output signal PD is connected to the resistor 37 for the integration circuit described above, and by controlling the frequency of the crystal oscillator 1, a PLL circuit is formed, and the system clock signal CLK1 is formed. Are phase-locked to the horizontal synchronizing signal HS. With this PLL, the image displayed on the liquid crystal panel becomes clear without any disturbance due to digital errors.

[0012]

The above-described controller 20 for a liquid crystal television has a large scale as an IC, and its development period and cost are considerable. On the other hand, today's LCD TVs, especially LCD panel pixel density specifications, are swinging in the opposite direction, with higher image quality and lower prices, larger screens and smaller sizes, and in the future, However, it is almost impossible to avoid that a different number of pixels is required depending on the screen size. Therefore, in particular, it is necessary to produce many types of liquid crystal televisions having different numbers of pixels in the horizontal direction, that is, different numbers of segment electrodes. with this,
There are also many types of LCD TV controllers 20 required.

When the number of segment electrodes changes, the number of segment drivers changes, and each segment driver
In order to satisfy the above data, the A / D conversion rate must be changed, and it is necessary to change the system clock frequency. In that case, the frequency of the crystal oscillator 1 may be changed. However, the price of the crystal oscillator 31 is several tens to one hundred and several tens of times higher than other passive elements (resistors and capacitors). Each time the specification is changed, the crystal oscillator 31 must be changed, and parts purchase becomes complicated, and management problems such as erroneous ordering and unnecessary inventory parts tend to occur. On the other hand, with respect to the controller 20 for the liquid crystal television, there are not many signals whose frequency must not be changed among the driver control signals, and these signals are generated based on the system clock signal CLK1. All parts are redesigned. Specifically, the design of the first frequency divider 2 and the second frequency divider 6 is changed, or the pattern matching circuit 5 and the TP
The design change of G3 is required. As described above, unlike a CRT system, a liquid crystal television is accompanied by a change in expensive specifications, such as a change in specifications, such as a change in an IC, so that problems of labor, cost, and management are inevitable.

[0014]

In order to solve the above-mentioned problem, the present invention provides an external setting between the crystal oscillator 1, the first frequency dividing circuit 2 and the second frequency dividing circuit 6 of the prior art. A variable frequency divider is inserted, and a second timing pulse generator (hereinafter, referred to as a second timing pulse generator) that operates on a signal before frequency division of the variable frequency divider
This is called a second TPG. ), The A / D conversion circuit is operated by the signal of the second TPG, and a timing pulse generator (hereinafter referred to as a first TP) corresponding to the conventional TPG 3 is provided.
Say G. The first characteristic is that the signal after variable frequency division or the frequency divided signal is operated as an input clock signal.

Furthermore, instead of the crystal oscillator 1 as a voltage controlled oscillator, a CMOS transmission. . Gay
Oscillator having an RC time constant circuit using a resistor as a resistor, and the CMOS transmission. A second feature is that a voltage controlled oscillator (hereinafter, referred to as VCO) constituted by a bias circuit for controlling the gate voltage of the field effect transistor constituting the gate is used.

[0016]

FIG. 1 is a block diagram showing the structure of a controller 20 'for a liquid crystal television according to the present invention. The pattern matching circuit 5, the first frequency dividing circuit 2, the second frequency dividing circuit 6, the phase comparator 7, and the A / D conversion circuit 4 are the same as the conventional one, and the first TPG 3 is almost the same as the conventional configuration. is there. 8 is a CMOS transmission. An RC oscillator having an RC time constant circuit using a gate as a resistor;
The CMOS transmission. A VCO constituted by a bias circuit for controlling the gate voltage of the field effect transistor constituting the gate, and as an external component, a phase difference signal PD from the phase comparator 7 as in the conventional case. To provide a control voltage VC to the VCO.
There is. 9 is an output clock signal CLK of the VCO 8
1 is divided by an externally set dividing ratio, and a variable frequency divider 10 for outputting a clock signal CLK2 to the first frequency dividing circuit 2 and the second frequency dividing circuit 6 is provided.
From the signal group C4 from the first TPG 3 and the data transfer clock CLKA for the segment driver;
This is a second TPG for synthesizing a control signal group C3 including a clock signal CLKB serving as a reference for the / D conversion rate and a signal CLKO serving as a timing reference for data output.

That is, the second TPG 10 is a conventional TP.
Only a circuit for generating the signals CLKA, CLKB, and CLKO from G3 is independent, and is not a special circuit.

Therefore, the first TPG also removes the above-mentioned circuit portion, and merely outputs the necessary signal group C4 to the second TPG.

The VCO 8 has an output signal H1 of the second frequency divider 6 and an output signal H of the pattern mapping circuit 5.
The operation so that W has the same frequency is the same as the conventional one, and this operation is the same even if the division ratio of the variable frequency divider 9 changes.

That is, the frequency division ratio of the variable frequency divider 9 is set to 1/1.
, The VCO 8 oscillates at twice the frequency, and the output clock CLK2 of the variable frequency divider 9 does not change in frequency, and therefore the signal H1
Does not change.

With this configuration, even if the clock signal CLK1 changes, the clock signal CL
K2, the first frequency divider 2 operating as an input signal becomes constant regardless of the frequency division ratio of the variable frequency divider 9.
And a second frequency divider 6, a pattern matching circuit 5 operated by an output signal of the first frequency divider 6, and a first TPG.
3 does not need to be changed as in the prior art. On the other hand, the clock signal CLK1 can be changed from the outside for the A / D conversion rate and data transfer rate that change with the change in the number of pixels. This can be done without changing the controller 20 'for the liquid crystal television.

Here, if the crystal oscillator 1 is used, only the change of the crystal oscillator is required.

However, the control for the liquid crystal television of the present invention
The la 20 'is provided with the VCO 8 having a very wide frequency variable range, eliminating the need for any component replacement.

FIG. 2 is a circuit diagram showing the configuration of the variable frequency divider 9. The flip-flop F91 divides the clock signal CLK1 by １ ／ and further divides the clock signal CLK1 to output a を frequency-divided signal. A flip-flop F92 and a 1/3 frequency divider 93 for performing 1/3 frequency division are provided.

Further, the clock signals CLK1, 1 /
NAND gates N95, N95, N96 for passing the divided-by-2 signal, divided-by-1 / 3 signal and divided-by-1 / 4 signal, respectively.
N97 and inverters 101 and 102 for inputting selection signals SL1 and SL2 from the outside to select one of the four NAD gates N94 to N97.
And an output signal of the four NAND gates N94 to N97, and outputs as a clock signal CLK2.
An ND gate N98 is provided.

As described above, unlike the configuration of the variable frequency divider that is generally used, the configuration in which the output signals of the independent frequency dividers are selected instead of changing the frequency division ratio is the same as that of the CLK1. This is to prevent a malfunction when the frequency is extremely high, to reduce the load on the CMOS-IC manufacturing process, and to take into consideration the advantage in cost.

FIG. 3 is a circuit diagram showing the configuration of the 1/3 frequency divider 93. In order to prevent malfunction of the following circuit, 50
A set priority type SR flip-flop F937 having two set input terminals and a reset input terminal is designed to obtain a 1/3 frequency-divided signal of% duty.
F939, NAND gates N931 to N936, and an inverter 1930 for generating an inverted signal of the input clock signal CLK1. N940 is a NAND constituting a self-reset circuit
The gate is provided to prevent the erroneous operation of the 1/3 frequency divider 93 itself, and it is possible to escape from another operation mode which can occur when the power is turned on, that is, the 1/1 frequency division state. ing.

FIG. 4 is a circuit diagram showing an example of the configuration of the VCO 8 according to the present invention. The CMOS transmission. Gate 82
Are connected, and the CMOS transmission. The other end of the gate is connected to a capacitor 83 and a capacitor 84 whose one end is grounded, and to the input of an inverter 85. The output of the inverter 85 is an inverter 86
The output of the inverter 87 is connected to one terminal of the capacitor 83, and the output of the inverter 87 is connected to one terminal of the capacitor 83. The data is input to data 81.

The CMOS transmission. The gate 82 comprises a P-channel transistor 82p and an N-channel transistor 82n. The ON resistance of these transistors 82p and 82n is controlled by a bias circuit 88. The bias circuit 88 includes a P-channel transistor 88p and an N-channel transistor 88.
n. The CMOS transmission. N-channel transistor 82n of gate 82 and N-channel transistor 88 of bias circuit 88
n is directly controlled by a control voltage VC input from outside, and the CMOS transmission. Gate 82
The P-channel transistor 82p is controlled by a second control voltage V2 generated by the bias circuit 88. The second control voltage V2 is created by connecting the gate of the bias circuit 88 with the drain of the P-channel transistor 88p, and connecting this to the drain of the N-channel transistor 88n.

FIG. 5 is a time chart showing the operation of FIG. 4, in which the output signal of the inverter 81 is set to P.
81, the CMOS transmission. Although the output signal of the gate 82 is shown as P82, the inverter 8
5 is almost the same as P81.

FIG. 6 is a circuit diagram showing still another example of the configuration of the VCO 8 of the present invention, in which three inverters 71 to 71 are provided.
CM is connected to each stage of the ring oscillator having the ring 73 connected in a ring shape.
OS transmission. This is an example in which a time constant circuit including gates 74 to 76 and capacitors 77 to 79 is inserted.

FIG. 7 is a time chart showing the waveforms of the output signals P74, P75 and P76 of the three time constant circuits of the VCO 8 in FIG. The signals P74 to P7 indicated by solid lines
The waveforms of the output signals P71 to P73 of the inverters 71 to 73 when 6 is input are shown by dotted lines superimposed on the solid lines.

In the above description of the VCO 8, only the inverter is used for the sake of convenience. In practice, however, in consideration of the IC test and other circumstances, the NAND gate or the NOR gate is used and the switching is performed. It should be configured to be able to.

[0034]

As described above, if the controller for a liquid crystal television is constructed as in the present invention, there is no need to redesign the IC even if the specification of the number of pixels of the liquid crystal television changes. CMOS transmission. If a VCO using a gate is used, external parts such as a crystal oscillator and a varactor diode are not required, and therefore, there is no need to change the parts. -It also contributes to cost reduction and further contributes to cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a controller 20 'for a liquid crystal television according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a variable frequency divider 9 of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a ３ frequency divider 93 of FIG. 1;

FIG. 4 is a circuit diagram showing a configuration example of a VCO 8 of the present invention.

FIG. 5 is a time chart showing the operation of the VCO shown in FIG. 4;

FIG. 6 is a circuit diagram showing still another example of the configuration of the VCO of the present invention.

7 is a time chart showing waveforms of respective output signals of three time constant circuits of the VCO of FIG. 6;

FIG. 8 is a block diagram showing a relationship between a configuration of a conventional controller for a liquid crystal television and a driver for a liquid crystal panel.

[Explanation of symbols]

8 voltage controlled oscillator (VCO) 9 variable frequency divider 10 second timing pulse generator (second TP
G) Controller for 20 'LCD TV

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[Procedure amendment]

[Submission Date] January 14, 2000 (2000.1.1)
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Liquid crystal drive controller

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video signal or R signal.
The present invention relates to a liquid crystal drive controller having a main function of converting a GB signal into a signal for a liquid crystal panel driver.

[0002]

2. Description of the Related Art As a liquid crystal display device using the liquid crystal drive controller of the present invention, there are a liquid crystal monitor, a liquid crystal television, a liquid crystal display view finder, a liquid crystal display projector, and the like. Will be described as one embodiment of the present application.

[0003] Unlike liquid crystal televisions, liquid crystal televisions use digital signals to drive display devices. That is,
In addition to A / D conversion of a video signal or an RGB signal, a digital circuit whose main function is to create a digital signal for a liquid crystal panel driver is used. This will be referred to as a liquid crystal drive controller. Here, the relationship between the driving method of the liquid crystal panel and the number of pixels of the liquid crystal panel will be described. For example, when displaying an NTSC signal on a liquid crystal television or a liquid crystal monitor, the liquid crystal panel is arranged in a vertical direction which is a common side electrode of the liquid crystal panel. The number of electrodes is approximately N
Although the number of synchronization signals in the TSC broadcasting system is adjusted, the number of pixels in the horizontal direction is various because the number of pixels in the horizontal direction is determined by the product specifications based on the performance required for the liquid crystal display device or the characteristics of the product. It is. Of course, the larger the number of pixels, the higher the resolution and the better the image display quality, but the higher the price of the liquid crystal display.

Since the size relationship of the number of horizontal pixels in the entire system of the liquid crystal display device causes the sampling frequency of a video signal or an RGB signal to be high and low and the data transfer rate to be large, the basic clock frequency also changes according to the number of horizontal pixels. Will be. On the other hand, in the vertical direction, as described above, it is often constant regardless of the number of horizontal pixels. A driver IC of a segment driver for driving a horizontal pixel generally has a 160-pin output or a 24 pin output.
The output number is about 0 pin output. For this reason, the number of horizontal pixels is often set to an integral multiple of the number of outputs of the driver IC.

The liquid crystal drive controller includes a crystal oscillator or an LC oscillator as a source of a system clock, and an A / D conversion circuit that operates using an output signal of the system clock oscillator or a frequency-divided signal thereof as a reference clock signal. , A timing pulse generator (hereinafter referred to as TPG) and the like. The A / D conversion circuit A / D converts the video signal and supplies the video data as a result of the conversion to the liquid crystal panel segment driver. The TP
G is a common driver and a segment driver for a liquid crystal panel, such as a signal for instructing the A / D converter circuit for operation timing and a data transfer timing signal.
Create the signal group necessary for the operation of.

FIG. 8 is a block diagram showing the relationship between the configuration of a conventional liquid crystal driving controller and a liquid crystal panel driver. In the figure, the liquid crystal driving controller 20 is surrounded by a dotted line, and the segment driver 21a,
21b, the common driver-22, and the liquid crystal panel 23 are shown outside thereof. Reference numeral 1 denotes a crystal oscillator serving as a voltage controlled oscillator which is an oscillator serving as a clock source in the liquid crystal drive controller 20. As external components, a crystal oscillator 31, a trimmer capacitor 32, a coupling capacitor 34, a varactor In addition to the diode 33, a phase. Locked. The resistors 37 and 35 and the capacitor 3 forming an integration circuit for a loop (hereinafter, referred to as a PLL)
There are six. Reference numeral 2 denotes a third frequency dividing circuit for dividing the frequency of the system clock signal CLK1 from the crystal oscillator 1 and outputting a signal group CB as a basis for synthesizing various pulse signals.

Reference numeral 13 denotes a control signal group C1 for a common driver and a control signal group for a segment driver from the signal group CB from the third frequency dividing circuit 12.
This is a TPG for synthesizing a control signal group C2 and a control signal group C3 for A / D conversion. The common driver control signal C1 includes a scan clock signal TK, a scan start signal, or a reset signal RS. The segment driver control signal C2 includes, in addition to the data transfer clock CLKA, the segment drivers 21a and 21b.
Signal PM for synchronizing with a PWM reference signal PM for pulse width modulation, a timing signal PT for synchronizing with the scanning timing of the common driver 22, a signal PL for transmitting the selection signal polarity of the common driver 22, and a segment driver 2
An inhibit signal INH for temporarily suspending the output operation of 1a and 21b and setting the output potential to the common potential is included. The A / D conversion control signal C3 includes A / D
In addition to the clock signal CLKB serving as a reference for the D conversion rate,
A signal CLKO serving as a timing reference for data output is included.

Reference numeral 14 denotes an A / A converter that converts an external RGB signal S1 into a clock signal CLKB from the TPG 13 at the rate of the clock signal CLKB.
An A / D conversion circuit which converts the RGB signals S1 into R, G, and B signals into 4-bit digital data while converting them into 4-bit video data D1. A multiplexer for sequentially outputting bit data in accordance with the data output timing signal CLKO is provided.

Reference numeral 15 operates according to the clock signal group CB from the third frequency dividing circuit 12, and externally outputs a synchronization signal SYN.
C is a pattern matching circuit which receives C and outputs a horizontal synchronizing signal HS and a vertical synchronizing signal VS separately and outputs a relatively wide horizontal synchronizing signal HW. The horizontal synchronizing signal HS and the wide horizontal synchronizing signal The time difference between the rising edge of the HW and the edge of the synchronization signal SYNC from the outside is kept constant, and is configured not to include a digital error. The horizontal synchronizing signal HS is used for resetting at least a part of the first frequency dividing circuit 2,
The vertical signal VS is used for the TPG 13.

In the above configuration, if the RGB signal S1 and the synchronization signal SYNC are supplied, the device functions as a liquid crystal television and an image is displayed on a liquid crystal panel. That is, in the liquid crystal drive controller 20, the crystal oscillator 1 as a system clock source is connected to an external crystal oscillator 31, and the output of the crystal oscillator 1 is supplied to the fourth frequency dividing circuit 16 and the third frequency dividing circuit 12. Connected to the input. Fourth frequency divider 16
Is connected to the phase comparator 17. Further, an output (signal HW) from the pattern matching circuit 15 is input to the phase comparator 17. The output of the phase comparator 7 is connected to a resistor 37 for an integration circuit, and is configured to control transmission of the crystal oscillator 1.

On the other hand, the output (signals HS and V) of the pattern matching circuit 15 to which the synchronization signal SYNC is input from the outside.
S, HW), the output (signal HW) is connected to the input of the phase comparator 17 as described above, and the other output (signal VS) is connected to the timing pulse generator (TP).
G), which is connected to the input of the TPG 13, and another output (signal HS) is connected to the input of the third frequency dividing circuit 12. The output (signal CB) of the third frequency dividing circuit 12 is connected to another input of the pattern matching circuit 15. The output (signal CB) of the third frequency dividing circuit 12 is TP
Connected to other input of G13. Among the outputs (signals C1, C2, C3) of the TPG 13, the output (signal C1) is connected to the input of the common driver 22, and the output (signal C2) of the TPG 13 is connected to the segment drivers 21a, 21a.
b, and the output of the TPG 13 (signal C3) is connected to the input of the A / D conversion circuit 14.

On the other hand, the output (signal C3) of the TPG 13 is input to another input of the A / D conversion circuit 14 to which the RGB signal S1 is input from the outside, and the output (signal D1) of the A / D conversion circuit 14 is Connected to the inputs of segment drivers 21a and 21b. The output of the common driver 22 is connected to a common electrode (horizontal electrode in FIG. 8) of the liquid crystal panel, and the output of the segment drivers 21a and 21b is connected to the segment electrode (vertical electrode in FIG. 8) of the liquid crystal panel. The basic operation of the liquid crystal drive controller 20 connected as described above will be described. The signal from the fourth frequency dividing circuit 16 by the phase comparator 17 and the external frequency reference signal (synchronization signal SYNC) input to the liquid crystal drive controller 20 are shown. Pattern matching with the output CB of the third frequency dividing circuit 12 is performed, and the output signal HW of the pattern matching circuit 15, which is the output, is compared in phase with the output signal HW to fine-tune and control the oscillation frequency of the crystal oscillator 8.

The crystal oscillator 1 generates a system clock signal CLK1 as a system clock source. This system clock signal CLK1 is frequency-divided by the third frequency divider 12 to form a signal group CB, which is input to the TPG 13 which is a timing pulse generator, and is controlled by the vertical synchronizing signal VS which is input to the other terminals of the TPG 13. Signal groups C1, C2 and C3 are created. The A / D conversion circuit 14 A / D converts the video signal or the RGB signal at a rate of the clock signal CLKB which is a part of the control signal group C3, converts it into 4-bit video data D1, and converts the converted video data. Is supplied to the liquid crystal panel segment drivers 21a and 21b. On the other hand, TPG13
The control signal group C1 output from the controller includes a scan clock signal, a scan start signal, and a reset signal, and the common driver 22 is driven and controlled by these signals.

On the other hand, the segment driver control signal C2, which is a control signal group C2 output from the TPG 13, has the same timing as the data transfer clock, the pulse width modulation reference signal for generating the gradation of the display image, and the scanning signal. And a timing signal for causing the segment driver 21 to operate.
a and 21b are driven and controlled. The electrodes of the liquid crystal panel are driven by these common driver and segment driver to display an image.

However, the crystal oscillator 1 outputs the synchronization signal SY
Since the phase is not fixed for NC,
The time difference between the D-converted data D1 and the video signal SYNC includes a digital error of at least one cycle of the system clock CLK1, and the image is constantly shaken.
To prevent this, a PLL circuit is used. 16
Is the system clock signal CLK from the crystal oscillator 1.
1 is a fourth frequency dividing circuit which divides the frequency of the H.1 to the same frequency as the horizontal synchronizing signal HS. A phase comparator 17 detects the phase difference between the output signal HI of the fourth frequency dividing circuit 16 and the wide horizontal synchronizing signal HW from the pattern matching circuit 15, and outputs a 3-state output signal PD. It is. 3 above
The state output signal PD is connected to the above-mentioned integrating circuit resistor 37, and a PLL circuit is formed by controlling the frequency of the crystal oscillator 1. The system clock signal CLK1 is a horizontal synchronizing signal. Phase locked to HS. With this PLL, the image displayed on the liquid crystal panel becomes clear without any disturbance due to digital errors.

[0016]

The liquid crystal drive controller 20 as described above is a large-scale IC, and the development period and cost are considerable.
On the other hand, today's LCD TVs, especially LCD panel pixel density specifications, are swinging in the opposite direction, with higher image quality and lower prices, larger screens and smaller sizes, and in the future, However, it is almost impossible to avoid that a different number of pixels is required depending on the screen size. Therefore, in particular, it is necessary to produce many types of liquid crystal televisions having different numbers of pixels in the horizontal direction, that is, different numbers of segment electrodes. Accordingly, a variety of liquid crystal drive controllers 20 are required.

When the number of segment electrodes changes, the number of segment drivers changes, and each segment driver
In order to satisfy the above data, the A / D conversion rate must be changed, and it is necessary to change the system clock frequency. In that case, the frequency of the crystal oscillator 1 may be changed. However, the price of the crystal oscillator 31 is several tens to one hundred and several tens of times higher than other passive elements (resistors and capacitors). Each time the specification is changed, the crystal oscillator 31 must be changed, and parts purchase becomes complicated, and management problems such as erroneous ordering and unnecessary inventory parts tend to occur. On the other hand, as for the liquid crystal drive controller 20, there are not many signals whose frequency must not be changed among the driver control signals, and a circuit portion that generates these signals based on the system clock signal CLK1. Are all redesigned. Specifically, the third frequency dividing circuit 12 and the fourth frequency dividing circuit 16
Or the pattern matching circuit 5 and T
It is necessary to change the design of PG3.

As described above, unlike the CRT system, a slight change in the specification of the liquid crystal television involves a change in expensive components such as a change in the IC, so that problems of labor, cost, and management are inevitable.

The large design of the liquid crystal drive controller IC (integrated circuit) corresponding to the change of the specification of the number of pixels of the liquid crystal panel which is the image display unit of the liquid crystal display device such as the liquid crystal monitor and the liquid crystal television according to the prior art. Solves the problem of having to make changes, and the problem of high cost and variety of components such as crystal oscillators for the system clock source externally connected to the liquid crystal drive controller IC due to the change in the specification of the number of pixels of the liquid crystal panel. It is another object of the present invention to provide a liquid crystal drive controller capable of improving the development speed of an LCD television, reducing development costs, reducing parts management costs in manufacturing, and reducing product costs.

[0020]

In order to solve the above-mentioned problems, the present invention provides an oscillator comprising a crystal oscillator or a CR oscillator, a frequency dividing circuit provided on the subsequent stage of the oscillator,
A phase comparator for inputting an external frequency reference signal and comparing the output signal of the frequency dividing circuit with the phase of the external frequency reference signal to control the oscillator; and a phase comparator inserted before the frequency dividing circuit. A variable frequency divider whose frequency division ratio can be set from the outside, a second timing pulse generator that operates on a signal before frequency division of the variable frequency divider, and the second frequency pulse generator.
An A / D conversion circuit which operates by a signal of a timing pulse generator, A / D converts a video signal or an RGB signal and supplies video data to a segment driver for a liquid crystal panel, and a signal after the variable frequency division Alternatively, it is characterized by having a first timing pulse generator for generating at least an operation timing signal for a liquid crystal panel common driver by operating the frequency-divided signal as an input signal.

Also, an oscillator comprising a crystal oscillator or a CR oscillator, a frequency dividing circuit provided on the subsequent stage of the oscillator, an external frequency reference signal input, an output signal of the frequency dividing circuit and the external frequency reference signal And a phase comparator which controls the oscillator by comparing the phases of the signals and an A / D converter of a video signal or an RGB signal operated by a signal of a second timing pulse generator to convert the video data into a segment driver for a liquid crystal panel. And an A / D conversion circuit for supplying the signal to the negative side, the signal after the variable frequency division or the frequency-divided signal serving as an input clock signal, and instructing the A / D conversion circuit to operate at the same time as the A / D conversion circuit. In addition to generating a data transfer timing signal for transferring video data to the segment driver, an operation data for a common driver is provided. A first timing pulse generator for generating a timing signal, a variable frequency divider inserted into a preceding stage of the frequency dividing circuit and capable of externally setting a frequency dividing ratio, and a signal before frequency division of the variable frequency divider. And at least the second timing pulse generator operating in the above.

According to the configuration characteristic of the present invention, a clock signal for an external frequency reference signal such as a reference signal or a segment driver pause signal for pulse width modulation of a common driver control signal or a segment driver control signal is supplied from outside. The use of the output signal of the controlled variable frequency divider makes it possible to respond optimally. As described above, according to the present application, by changing the variable frequency division ratio with respect to the change in the number of pixels, it is possible to change the signal and the number of pixels that must respond to the change in the number of pixels without changing the circuit inside the liquid crystal drive controller. A circuit that optimally generates a signal that does not need to be directly adjusted can be obtained, and a liquid crystal drive controller can be shared for liquid crystal panels having different numbers of pixels.

[0023]

FIG. 1 is a block diagram showing the structure of a liquid crystal drive controller 20 'according to the present invention. A pattern matching circuit 5, a first frequency dividing circuit 2, a second frequency dividing circuit 6,
The phase comparator 7 and the A / D conversion circuit 4 are almost the same as the conventional one, and the first TPG 3 is almost the same as the conventional one. 8 shows an RC oscillator having an RC time constant circuit using a CMOS transmission gate as a resistor; A VCO constituted by a bias circuit for controlling the gate voltage of the field effect transistor constituting the gate, and as an external component, a phase difference signal PD from the phase comparator 7 as in the conventional case. Is integrated into the VCO.
There are resistors 37 and 35 and a capacitor 36 for applying a voltage VC. 9 is an output clock signal C of the VCO 8
LK1 is divided by an externally set dividing ratio, and the clock signal CLK2 is divided into the first frequency dividing circuit 2 and the second frequency dividing circuit 6.
The variable frequency divider 10 outputs the clock signal CL.
From K1 and the signal group C4 from the first TPG 3, the data transfer clock CLKA for the segment driver is obtained.
And a clock signal CLK serving as a reference for the A / D conversion rate.
This is a second TPG for synthesizing a control signal group C3 including B and a signal CLKO serving as a data output timing reference.

That is, the second TPG 10 is a conventional TP.
Only circuits for generating the signals CLKA, CLKB, CLKO from G13 are independent, and are not special circuits. Therefore, the first TPG also only removes the above-mentioned circuit portion, and the signal group C required for the second TPG
It just outputs 4. The operation of the VCO 8 such that the output signal H1 of the second frequency divider 6 and the output signal HW of the pattern matching circuit 5 have the same frequency is the same as the conventional one. The same applies even if the frequency division ratio of the variable frequency divider 9 changes. That is, if the frequency division ratio of the variable frequency divider 9 is changed from 1/1 to 1/2, the VCO 8 oscillates at twice the frequency, and the output clock CLK2 of the variable frequency divider 9 becomes The frequency does not change, and therefore the frequency of the signal H1 does not change. With this configuration, even if the clock signal CLK1 changes, the clock signal CLK2 and the frequency dividing ratio of the variable frequency divider 9 are always constant, and the first signal which operates as an input signal is used. Frequency divider 2 and second frequency divider 6,
Further, a pattern operated by the output signal of the first frequency divider 6
The matching circuit 5 and the first TPG 3 do not need to be changed as in the prior art, while the A /
As for the D conversion rate and the data transfer rate, since the clock signal CLK1 can be changed from the outside, it is possible to deal with the liquid crystal drive controller 20 'without any change.

Here, if the crystal oscillator 1 shown in FIG. 8 is used instead of the RC oscillator having the RC time constant circuit, only the crystal oscillator needs to be changed.

However, the liquid crystal driving controller 2 of the present invention
0 'is provided with the VCO 8 having a very wide frequency variable range, eliminating the need for any component replacement.
That is, in the liquid crystal drive controller 20 ', a VCO 8 which is a voltage controlled oscillator using a CMOS transmission gate is connected as a system clock source, and the output of the VCO 8 is connected to the input of the variable frequency divider 9 and the second timing. It is connected to the input of a pulse generator (second TPG) 10.

The variable frequency dividing circuit 9 includes a variable frequency dividing circuit 9
An input for controlling from outside is provided. The output signal of the variable frequency divider 9 is supplied to the second frequency divider 6 and the first frequency divider 2.
Connected to the input. The output (signal H1) of the second frequency divider 6 is connected to the phase comparator 7. Further, an output signal HW from the pattern matching circuit 5 is input to the phase comparator 7. The output of the phase comparator 7 is connected to a circuit composed of resistors 37 and 35 and a capacitor 36 for integrating the phase difference signal PD from the phase comparator 7 and applying the control voltage VC to the VCO 8.

On the other hand, the output (signals HS and V) of the pattern matching circuit 5 to which the synchronization signal SYNC is input from the outside.
S, HW), the output (signal HW) is connected to the input of the phase comparator 7 as described above, and the other output (signal VS) is connected to the input of the first TPG 3 which is a timing pulse generator. Output (signal H
S) is connected to the input of the first frequency divider 2. Also, the first
The output (signal CB) of the frequency divider 2 is connected to another input different from the SYNC signal input terminal of the pattern matching circuit 5. The output of the first frequency divider 2 (signal C
B) is connected to another input of TPG3. Also, the first T
Of the outputs (signals C1, C2 ', C4) of PG3, the output (signal C1) is connected to the input of the common driver 22, and the output (signal C2') of the first TPG3 is connected to the input of the segment drivers 21a, 21b. , 1st TPG
The third output (signal C4) is connected to another input of the second TPG 10. The output of the second TPG 10 (signal C3)
Is connected to the input of the A / D conversion circuit 4. The second T
The output (signal CLKA) of PG10 is connected to the inputs of segment drivers 21a and 21b.

On the other hand, the output (signal C3) of the second TPG 10 is connected to the other input of the A / D conversion circuit 4 to which the RGB signal S1 is input from the outside as described above. A /
The output (signal D1) of the D conversion circuit 4 is connected to the inputs of the segment drivers 21a and 21b. The output of the common driver 22 is connected to a common electrode (horizontal electrode in FIG. 1) of the liquid crystal panel, and the segment drivers 21a, 21b
Are connected to segment electrodes (vertical electrodes in FIG. 1) of the liquid crystal panel.

The basic operation of the liquid crystal drive controller 20 'connected as described above will be described. The signal from the second frequency dividing circuit 6 by the phase comparator 7 and the external frequency reference signal (synchronous signal) input to the liquid crystal drive controller 20' The oscillation frequency of the VCO 8 is controlled by comparing the phase with the signal SYNC). The VCO 8 generates a system clock signal CLK1 as a source of the system clock. This system clock signal CLK1 is input to the variable frequency dividing circuit 9. The variable frequency dividing circuit 9 includes a liquid crystal driving controller I
A terminal for controlling the frequency division number that can be controlled from outside C is provided in the liquid crystal drive controller IC. The output signal of the variable frequency dividing circuit 9 divided by the frequency dividing ratio set from the outside is
The signal is divided by the first frequency divider 2 into a signal group CB, which is input to a first TPG 3 which is a timing pulse generator. The first TPG 3 also has an external synchronization signal SY.
A vertical synchronization signal (signal VS) which is an output of the pattern matching circuit 5 to which the NC and the signal group CB are input is input. By the vertical synchronizing signal VS and the signal group CB, T
PG control signal groups C1, C2 'and C4 are created.

Here, the control signal group C4 output from the first TPG 3 is input to the second TPG 10, and the data transfer clock CLKA for the segment drivers 21a and 21b and the clock signal CLKB serving as a reference for the A / D conversion rate. And a control signal group C3 including a signal CLK0 serving as a data output timing reference. Further, the control signal group C1 output from the first TPG 3 includes a scan clock signal, a scan start signal, and a reset signal, and the common driver 22 is driven and controlled by these signals. Further, the control signal group C2 ′ output from the first TPG 3 includes a reference signal for pulse width modulation for generating a gradation of a display image, and the like.
a and 21b are driven and controlled. Further, the A / D conversion circuit 4 transmits the video signal or the RGB signal to the control signal group C.
A / D conversion is performed at the rate of the clock signal, which is a part of 3, to convert it into 4-bit video data D 1, and the converted video data D 1 is supplied to segment drivers 21 a and 21 b. The data transfer clock CLKA output from the second TPG 10 is supplied to the segment driver 21.
a, 21b. In this case, the A / D conversion rate and the data transfer rate (data transfer clock CLKA) that change with the pixel change can be varied by the variable frequency divider 9 set from outside. Thus, the common driver 22 and the segment drivers 21a, 21a
By controlling the driving of b, the electrodes of the liquid crystal panel are driven to display an image.

FIG. 2 is a circuit diagram showing the configuration of the variable frequency divider 9. The flip-flop F91 which divides the clock signal CLK1 by と and further divides the clock signal CLK1 to output a ４ frequency-divided signal. A flip-flop F92 and a 1/3 frequency divider 93 for performing 1/3 frequency division are provided. Further, the clock signal CLK1, a 1/2 frequency divided signal, a 1/3 frequency divided signal,
NAND gate N for passing a 1/4 frequency-divided signal respectively
95, N95, N96, and N97, and inverters 101 and 102 for inputting external selection signals SL1 and SL2 and selecting one of the four NAD gates N94 to N97. , The four NAND gates N
94 to N97 are input to output a clock signal CLK.
2 is provided with a NAND gate N98 for outputting as N2.
As described above, unlike the configuration of the variable frequency divider that is generally used, the configuration in which the output signals of the independent frequency dividers are selected instead of changing the frequency division ratio is described above.
This is to prevent a malfunction when the frequency of K1 is very high, and to reduce the load on the CMOS-IC manufacturing process.
This is because the cost advantage was considered.

FIG. 3 is a circuit diagram showing the structure of the 1/3 frequency divider 93. In order to prevent malfunction of the following circuit, 50
A set priority type SR flip-flop F937 having two set input terminals and a reset input terminal is designed to obtain a 1/3 frequency-divided signal of% duty.
F939, NAND gates N931 to N936, and an inverter 1930 for generating an inverted signal of the input clock signal CLK1. N940 is a NAND constituting a self-reset circuit
The gate is provided to prevent the erroneous operation of the 1/3 frequency divider 93 itself, and it is possible to escape from another operation mode which can occur when the power is turned on, that is, the 1/1 frequency division state. ing.

FIG. 4 is a circuit diagram showing a configuration example of the VCO 8 of the present invention. The CMOS transmission gate 82 as a voltage control resistor is provided at the output terminal of the inverter 81.
The other end of the CMOS transmission gate is connected to a capacitor 83 and a capacitor 84, one end of which is grounded, and to the input of an inverter 85. The output of the inverter 85 is an inverter 86
The output of the inverter 87 is connected to one terminal of the capacitor 83, and the output of the inverter 87 is connected to one terminal of the capacitor 83. The data is input to data 81. The CMOS transmission gate 82
Is composed of a P-channel transistor 82p and an N-channel transistor 82n. The ON resistance of these transistors 82p and 82n is controlled by a bias circuit 88. The bias circuit 88 includes a P-channel transistor 88p and an N-channel transistor 88n. The N-channel transistor 82n of the CMOS transmission gate 82 and the N-channel transistor 88n of the bias circuit 88
Is directly controlled by a control voltage VC input from the outside, and the P-channel transistor 82p of the CMOS transmission gate 82 is controlled by a second control voltage V2 generated by the bias circuit 88. The second control voltage V2 is supplied to the bias circuit 8
8 P-channel transistor 88p drain and gate
And an N-channel transistor 8
It is made by connecting to the 8n drain.

FIG. 5 is a time chart showing the operation of FIG. 4, wherein the output signal of the inverter 81 is set to P.
81, the output signal of the CMOS transmission gate 82 is shown as P82;
5 is almost the same as P81.

FIG. 6 is a circuit diagram showing still another example of the configuration of the VCO 8 of the present invention, in which three inverters 71 to 71 are provided.
CM is connected to each stage of the ring oscillator having the ring 73 connected in a ring shape.
This is an example in which a time constant circuit including OS transmission gates 74 to 76 and capacitors 77 to 79 is inserted.

FIG. 7 is a time chart showing the waveforms of the output signals P74, P75 and P76 of the three time constant circuits of the VCO 8 of FIG. The signals P74 to P indicated by solid lines
The waveforms of the output signals P71 to P73 of the inverters 71 to 73 when the signal 76 is input are shown by dotted lines superimposed on the solid lines. In the above description of the VCO 8, only the inverter is used for the sake of convenience. However, in actuality, switching is performed by using a NAND gate or a NOR gate in consideration of an IC test or other convenience. Should.

[0038]

As described above, if the liquid crystal driving controller is constructed as in the present invention, there is no need to redesign the IC even if the specification of the number of pixels of the liquid crystal television changes, and the liquid crystal driving controller is changed. It is possible to cope with a change in the specification of the number of pixels without performing the above. At this time, even if a crystal oscillator is used, only the crystal oscillator needs to be changed. Therefore, the number of changed parts is reduced, and not only the management in manufacturing, but also the speed of development of the liquid crystal television.
It also contributes to upgrades and further reduces costs.

Further, according to the present invention, there is a problem that a large design change of a liquid crystal drive controller IC (integrated circuit) due to a change in the specification of the number of pixels of a liquid crystal panel which is an image display unit of a liquid crystal display device is required. Changes in the specifications of the number of pixels of the LCD drive controller IC, externally connected to the liquid crystal drive controller IC. A liquid crystal drive controller that can reduce development costs, reduce parts management costs in manufacturing, and reduce product costs can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal drive controller 20 ′ of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a variable frequency divider 9 of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a ３ frequency divider 93 in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of a VCO 8 of the present invention.

FIG. 5 is a time chart showing the operation of the VCO of FIG. 4;

FIG. 6 is a circuit diagram showing still another example of the configuration of the VCO of the present invention.

7 is a time chart showing waveforms of respective output signals of three time constant circuits of the VCO of FIG. 6;

FIG. 8 is a block diagram showing the relationship between the configuration of a conventional liquid crystal driving controller and a liquid crystal panel driver.

[Description of Signs] 2 First frequency divider circuit. 3 First timing pulse generator (1st TP
G). 4 A / D conversion circuit. 5 Pattern matching circuit. 6 Second frequency divider. 7 Phase comparator. 8 Voltage controlled oscillator (VCO). 9 Variable frequency divider. 10 Second timing pulse generator (2nd TP
G). 20 'Liquid crystal drive controller. 37 Resistance. 35 Resistance. 36 Capacitor.

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Claims (2)

[Claims] 1. A voltage controlled oscillator, a frequency dividing circuit for dividing an output signal of the voltage controlled oscillator, an external frequency reference signal being input, and comparing the phase of the output signal of the frequency dividing circuit with the phase of the frequency reference signal. A phase comparator for controlling the voltage controlled oscillator, an A / D conversion circuit for A / D converting a video signal or an RGB signal, and supplying video data to a liquid crystal panel segment driver; A / D
It instructs the operation timing to the conversion circuit, generates a data transfer timing signal for transferring the video data of the A / D conversion circuit to the segment driver, and operates the common driver. In a controller for a liquid crystal television having a first timing pulse generator for generating a signal, a variable frequency divider which can be set externally is inserted at a relatively preceding stage of the frequency dividing circuit, and the variable frequency dividing is performed. A two-timing pulse generator that operates on a signal before frequency division of the converter;
A first timing pulse generator configured to operate by a signal of a timing pulse generator and to operate the signal after variable frequency division or the divided signal as an input clock signal; Control
La. 2. The voltage-controlled oscillator according to claim 1, wherein said voltage-controlled oscillator is a CMOS transmission. An RC oscillator having an RC time constant circuit using a gate as a resistor; 2. A controller for a liquid crystal television according to claim 1, wherein said controller comprises a bias circuit for controlling a gate voltage of a field effect transistor constituting said gate.