JP2000163456A - Logic verifying method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform fast and efficient logic verification which is superior in operability and observing performance. SOLUTION: A dummy logic model 304 providing the I/O environment, etc., of a logic structure model 105 to be verified is built in the logic model 105 mounted on a logic emulator device 101, a test control program 305 which controls logic verifying operation by input to the logic structure model 105 of a test vector 303a is built in the test vector 303a, and test information is sent and received between the dummy logic model 304 and test control program 305 from a process control program 201 having a GUI interface described in an external general language through interface information 306 to improve the operability and observing performance of logic verification by the GUI interface, thereby achieving the consistent logic verification of a lage-scale logic device by the fast logic emulator device 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification technique, and more particularly to a technique effective when applied to a function verification technique of a logic circuit device using a logic simulator or a logic emulator.

[0002]

2. Description of the Related Art Logic emulation using a conventional logic emulation apparatus (logic emulator) is a technique for designing a logic model, which is a part of a logic verification target system device or a logic chip, by using an operation description language to describe an operation. The structural model is logically compiled, mounted on the RAM in the logical emulation device, and the logic is verified by the in-circuit method of emulating the operation of the logical model. For devices and logic chips that are not in-circuit, connect external signal lines to the external connection pins of the logic emulation device to secure an interface with the in-circuit logic, and synchronize the operation at the signal value level. I have. In addition, when observing a logical operation or individually specifying a test vector, a logical value is given to an observable internal signal or an external pin in the logic emulator, or a signal is applied to a signal line specified in advance. Observations were made on a line-by-line basis to confirm the logical operation.

[0003] As for such a logic emulation technique, a method as disclosed in Japanese Patent Application Laid-Open No. 02-245831 is known. That is, by mapping the logic function to be verified on an externally programmable gate array, the target logic function is realized in hardware, thereby enabling high-speed execution and logic verification. .

[0004]

In the conventional in-circuit method, a logic emulation in a partial logic is required for a recent increase in logic scale and logic complexity in order to secure logic quality such as a system test. It is not enough, and system logic verification by logic emulation for the entire logic chip has become necessary. In logic verification for the entire logic chip, the logic scale has increased and the logic complexity has increased.
In the conventional logic emulation of giving a logical value at the signal line level or observing the value of the signal line, it is necessary to set the logical value to all the signal lines, so that it is difficult to perform efficient logic verification. To improve observability and operability, it is necessary to enhance the man-machine interface and improve testability.

In the logic simulation of the entire logic chip, since a logic simulator creates a logic model by software, the logic operation requires a lot of time for software verification compared to the hardware operation, and the product is developed in a short time. However, it is difficult to apply it today because it has to be shipped early, and it is one of the issues to be solved.

When the logic to be verified is a logic of a peripheral device or the like, the logic verification operation of the logic alone may not be able to be confirmed, and the logic to be verified is used together with an architecture logic simulator having a different verification level. It is necessary to perform the logic verification by using the logic verification described above or using a dedicated logic simulator. Therefore, it is important to select an efficient logic simulator and to construct a logic emulation method that can be used at the system test level.

In addition, when a real chip is manufactured at the stage when the logic emulation is completed, and a logic quality inspection is performed on a single chip or on the entire apparatus, a logic defect is found if the logic verification environment can be used continuously. In this case, it is easy to provide feedback to logic simulation and logic emulation, and it is necessary to construct a consistent logic verification environment when considering the construction of a verification environment.

An object of the present invention is to provide a logic verification technique capable of efficiently performing system logic verification in a short time by logic emulation of an entire logic chip.

Another object of the present invention is to provide a logic verification technique capable of enriching a man-machine interface and improving observability and operability of an internal state in logic emulation, as well as testability. is there.

Another object of the present invention is to provide a logic verification technique capable of realizing a consistent logic verification from a logic model to an actual chip.

Another object of the present invention is to provide a logic verification technique capable of reducing the man-hour and period required for constructing a logic verification environment and realizing cost reduction in a logic verification process.

[0012]

SUMMARY OF THE INVENTION According to the present invention, for the purpose of verifying the logic of a target logical device, the logical emulator executes the logical structure model of the target logical device by operating together with the logical structure model of the target logical device on a logical emulator. Implements a pseudo-logic model that provides an environment, and implements a test control program that controls the logic verification operation by transmitting and receiving information to and from an external processing control program in the test vector executed on the logic emulator Is what you do.

[0013] The pseudo-logic model, the program, and the processing control program for controlling the logic emulator are mounted on, for example, an information processing device connected to the logic emulator via a network, and perform information communication between the logic emulator and the processing control program. Means to operate the logic emulator asynchronously, a graphical user interface to provide a visualization display of various information and an information input environment, etc., and a logic verification program with different verification methods such as a logic simulator other than the logic emulator. It has a connection plug interface that connects to the processing control program, and an interface with a test control program and test vector that runs on the logic emulator, improving the operability and observability of logic verification of the target logic device and improving efficiency. Well fast To allow the physical verification.

Further, in a dedicated test apparatus in which a real chip of a target logic device is mounted, information is exchanged with an external processing control program in a test vector input to the real chip, thereby performing a logic verification operation. This implements a test control program that controls In this case, in addition to the above-described configuration, the processing control program is mounted on an information processing device to which the dedicated test device is connected via an arbitrary connection interface, and exchanges information with a device driver that controls the connection interface. It has a driver control program to perform, and improves operability and observability in logic verification of a real chip to perform logic verification efficiently and at high speed. In addition, the test vector, the test control program, and the processing control program can be the same as those of the logic emulator.

In a processing control program having an interface between the test control program in the test vector and the pseudo-logic model, the internal signal value of the logic model of the target logic device mounted on the logic emulator is observed and controlled, and the processing status is controlled. Is controlled as an I / O request, and the processing control program transmits and receives the I / O request, so that the logic verification of the target logic device can be performed while controlling the logic emulator.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of a configuration of an information processing system in which a logic verification method according to a first embodiment of the present invention is implemented. FIG. 2 shows a logic verification method according to the present invention. FIG. 2 is a conceptual diagram illustrating an example of a configuration of software for performing the operation. FIG. 8 is a conceptual diagram illustrating an example of a configuration of a logic emulation system according to a reference technique of the logic verification method according to the present embodiment.

First, before describing the present embodiment with reference to FIG. 8, an outline of a logic emulation system according to a reference technique of the present embodiment will be described.

The logic emulation system 10 of FIG.
0 is the logical emulator device 101 connected to the LAN
And a logical emulator control program 109 that operates on the information processing device 108 also connected to the LAN. The logic emulator device 101 includes a control device 102
And a read / write RAM 103, and the control device 1
Reference numeral 02 includes a clock generator 104 for generating an operation clock supplied to the logic emulator device 101, a control signal pin 107 for controlling logic emulation, and the like. It should be noted that only the components related to the present invention will be specifically described.

The control signal pin 107 is an external pin for reporting an emulation state to the logic emulator control program 109 and receiving an operation instruction. RA
M103 is a logical structure model storage area 105 to be verified.
Is used to implement a later-described verification target logical structure model 114a or a test vector in the test vector storage area 106. The logic emulator control program 109 includes a control unit 110 for controlling the logic emulator device 101 and the logic emulator control program 109, a RAM access unit 112, and a logic compiler for logically compiling the verification target logic 114 described in an operation description language. 111, and a graphical user interface (GUI) control unit 113 for graphically displaying and controlling the entire logic emulation system. The logic compiler 111 checks the logic 114 to be verified.
Is input, and is logically compiled, and the RA in the logic emulator apparatus 101 is obtained as the logical structure model 114a to be verified.
It is implemented in the logical structure model storage area 105 to be verified in M103.

Next, a procedure for actually performing the logic emulation will be described. After the above-described logic 114 to be verified is logically compiled and mounted on the RAM 103 as the logic structure model 114a to be verified, the test vector is
The access vector 112 allows the test vector storage area 10
6 and the control unit 110 controls the control signal pin 107
Operating condition information to the clock generator 104
The clock is actually supplied, and the logic emulator 101 is operated to perform logic emulation. Next, after performing the constant cycle logic emulation, the control device 102 sets emulation operation state information on the control signal pin 107, the control unit 110 monitors this information, and continuously supplies a clock in accordance with the state information. Or interrupt and observe the state of the RAM 103. Logic verification is performed by repeating these processes.

Next, FIG. 2 shows an example of a processing control program for realizing the logic verification method according to each embodiment of the present invention. The processing control program 201 includes an inter-process communication control unit 203 that performs inter-process communication with the logical emulator control program 109 activated on the network.
, A logic emulator control unit 204, a test vector control unit 205, and a data conversion unit 20 that performs conversion processing of data transmitted and received between the logic emulator device 101.
6, a connection plug interface 207 for connecting a verification device and a verification system other than the logic emulator device 101 to the processing control program 201, and a graphical user interface (GUI) control unit for comprehensively controlling the logic verification method of the present invention. 202. A detailed description of each processing unit will be given in the description of the embodiment. Although FIG. 2 illustrates a configuration including all the components of the inter-process communication control unit 203 to the connection plug interface 207 for simplicity, a configuration including only necessary components among these components is also illustrated in FIG. Included in the invention.

Next, a logic emulation system in which the logic verification method according to the first embodiment of the present invention will be described with reference to FIG. In the logic emulation system 300 according to the first embodiment shown in FIG. 1, the logic to be verified is logically compiled as logic realizing the function level architecture, set in the RAM 103 of the logic emulator device 101, and logic verification is performed. explain.

In the logic emulation system 300 of this embodiment, the logic emulator 101
In the in-circuit logic verification, a pseudo-logic model 304 described later is mounted in the logic emulator apparatus 101, thereby enabling vector verification in a state where only the logical structure model to be verified is mounted. In addition, there is no need to connect peripheral hardware circuits to the logic emulator device 101 to provide an actual operation environment of the logic model to be verified (and a real chip performing an equalization operation).

For example, when the object to be verified is a microprocessor, it is necessary to realize an input / output environment with peripheral circuits used for constructing an actual system in order to verify the entire logical function. In the logic emulation system 100 of the reference technique as described above, it is necessary to prepare a hardware environment of peripheral circuits in advance, and to connect the wiring to a logic emulator device 101 that emulates the operation of a microprocessor. On the other hand, in the case of the logic emulation system 300 of the present embodiment, a pseudo logic model 304 described later
Since an I / O interface necessary for the operation of the target logical structure model 307a to be verified is realized, connection to an actual peripheral circuit or the like (in-circuit connection) is unnecessary, and verification operation can be performed by the logical emulator device 101 alone. It is possible.

In this embodiment, the test vector 303
Are stored in the information processing apparatus 301 (A) connected to the LAN. The information processing device 302 (B) connected to the LAN has a logical emulator control program 1
09 and the processing control program 201 are mounted and executed. Information processing device 301 (A) and information processing device 30
2 (B) includes, for example, a workstation or a personal computer operating on an OS such as UNIX.

First, a logic 307 to be verified and a test vector 303 are prepared as preparation. The verification target logic 307 incorporates a pseudo logical model 304 having an interface function with the processing control program 201, and is logically compiled by the logic compiler 111 to be a verification target logical structure model 307a. Pseudo logic model 304
The function of (1) is to observe and monitor the logical value of the internal signal line during the logical operation;
It has a system control function for controlling the operation of the (verification target logical structure model 307a) and an interface function for the processing control program 201. The test vector 303 includes a test control program 305 having an interface function with the processing control program 201.
And interface information 306 used for an interface with the processing control program 201.

Next, the logic emulator control program 1
09 is activated, and the compilation result of the prepared logic 307 to be verified is set as the logic structure model 307a to be verified in the logic structure model storage area 105 in the RAM 103 using the RAM access unit 112.

Next, the processing control program 201 is started, and
The prepared test vector 303 is transferred to the data conversion unit 2
In step 06, the test vector 303a is converted into a test vector 303a in a format that can be set in the RAM 103, and set in the test vector storage area 106 in the RAM 103 via the RAM access unit 210 in the logic emulator control unit 204.

The difference from the logic emulation system 100 of the reference technology shown in FIG.
4 and a test control program 305 and interface information 306 in the test vector 303a, and a processing control program 201 independent of the logic emulator control program 109.

Since the logic emulator control program 109 of the present embodiment has a Tcl / Tk interface, the processing control program 201 is
In this case, the functions of the logic emulator control program 109 shown in FIG. 8, which is a reference technology, can be used as they are and can be easily connected as an extension of the logic emulator control program 109. In other words, the processing control program 201
1 can be said to be an extension program that can be operated from the outside.

Tcl / Tk is a general-purpose scripting language having a graphical interface (GUI) developed at the University of California, Berkeley, and is an open shell script for many universities and research laboratories, as well as for companies of various sizes. It's being used.

Further, the Tcl / Tk interface employed in the present invention is a
This is because it has an I / Tk interface, and when implementing the present invention, a GUI function for providing a man-machine interface can be realized by an X window system, Motif, or the like. In other words, as long as the system has a GUI interface, the functions and systems are not limited.

Next, the procedure for actually performing the logic emulation will be described. After the test vector 303a is set, the setting information control unit 215 sets the detailed logic emulation operation and the test control program 305.
, Detailed settings of the interface information 306, and various settings necessary for the logic emulation operation, such as the operating frequency. These settings are performed by the GUI control unit 113 or the GUI.
It is controlled by the control unit 202. After the various settings are completed, the operation control unit 209 in the logic emulator control unit 204 issues a reset request to the pseudo logic model 304, and changes the state of the verification target logical structure model 307a to an operable state. Thereafter, the number of operation clocks is given to the control signal pin 107, and the control device 102 is supplied with the clock by the clock generation device 104 to the logic emulator device 101 by the specified number of clocks, and actually operates. When the test control program 305 is operating for the specified number of clocks, the test control program 305 sets the internal operation state and the test operation state in the interface information 306. When the emulation is interrupted without reaching the designated clock number or when a request for outputting a message or the like to the processing control program 201 occurs in the test control program 305, the state information is transmitted to the interface information 306. Set to.

Since the pseudo-logic model 304 monitors the interface information 306, when these requests are detected, the pseudo-logic model 304 sends the control signal pin 107 of the control device 102
A trigger event is generated and an interruption report is sent to the control device 102. As described above, the pseudo logic model 304 has a function of interrupting the emulation operation, and can directly exchange information with the processing control program 201 in an interactive manner. That is, by monitoring the value of an internal signal in the logic, emulation can be interrupted, and the information can be transmitted to the processing control program 201.

Next, since the trigger event control unit 208 of the processing control program 201 monitors the control signal pin 107, when the trigger event is detected, the interface information 306 storing the interruption information is stored in the RAM.
The information obtained through the access unit 210 is converted by the data conversion unit 206 for display, and
To display the delivery. The test vector control unit 205 analyzes the acquired information with respect to the interruption information. When the test control program 305 requests an input or a command, the input control unit 213 controls the operator's key input or the GUI window. The operation is accepted, and the input information is set in the interface information 306. After the setting, if the clock is supplied, the logic emulation is continued.

When the emulation result and the operating state are stored, the log data acquisition control unit 216 acquires the displayed information, the input information, and the accessible RAM information, and the like. Log information 3
08 can be stored. The processing control unit 211 and the window control unit 214 control the processing control program 201 consistently and support various operations.

As described above, using the various functions of the GUI control unit 202 and the test vector control unit 205, the RAM 103
By performing logic emulation interactively with the test control program 305 in the inside, it is possible to secure a means for interacting with the dedicated pseudo logic model 304 in the logic emulator apparatus 101. In the logic emulation operation, only the interface information 306 is used. Logic emulation can be controlled by operation, operability and observability can be improved, and efficient logic verification can be performed. In addition, since these methods indirectly control the logic emulator control program 109, they include the reference technology illustrated in FIG.
Can be controlled. Further, the test control program 305
Can control the logic emulation operation, the interruption of the logic emulation can be minimized, and the high speed of the logic emulator device 101 can be used to the maximum, so that the high speed logic emulation can be performed.

Next, an example of a specific processing flow in the logic emulation of the first embodiment is shown in FIG.
FIG. 3 illustrates a processing flow of only the operation of the components of the present embodiment when the test control program 305 generates a message output request and a command input request during the logic emulation operation. First, the processing stages in FIG. 3 are divided into the stages of the operator 401, the processing control program 201, the pseudo-logic model 304, and the test control program 305, and the cooperative operation of these stages is shown as a processing flow.

The above-described logic 307 to be verified and the test vector 303 are respectively the logical structure model 307a to be verified.
When the emulation can be started if the clock is supplied to the RAM 103 as the test vector 303a and the clock is supplied, the operator gives an operation start instruction (step 402). This step 40
The operation start instruction of No. 2 indicates the number of operation clocks (the number of operation cycles). Next, the processing control program 20
1 actually starts emulation (step 40).
3), the logic emulator device 101 starts logic emulation. When the logic emulation is started, the pseudo logic model 304 and the test control program 305 start operating (step 404). At this time, the pseudo logic model 304 constantly monitors the interface information 306 (step 405). When the test control program 305 reports a message to the operator during operation, a message output request is generated, and further, a request for inputting a response command to the message is generated (step 406). The output message and event information that can be detected by the pseudo logic model 304 are set in 306 (step 407). Next, the pseudo logic model 304 detects an event by monitoring the interface information 306 (step 408), and generates a trigger event for the control signal pin 107 (step 409). When a trigger event occurs, the control device 102 suspends the emulation (step 410), the processing control program 201 recognizes that the interruption is caused by the trigger event from the suspended state (step 411), and acquires the interface information 306 by reading the RAM. (Step 412). The acquired information is subjected to data conversion through the data conversion unit 206 (step 413), and displayed on the window of the display unit 212 as an output message from the test control program 305 (step 414). Normally, if only a message is output, the emulation is resumed after the display. However, in this embodiment, since an input command request is also generated at the same time, a command input request is made to the operator 401 ( (Step 415), the processing control program 201 enters an input waiting state (Step 417). The operator 401 performs a key input (step 416), and inputs a command for the test control program 305. Next, the key input command is obtained (step 418), and data conversion is performed by the data conversion unit 206 (step 413).
6 is written to the RAM (step 4).
19). Next, the emulation operation is restarted (step 420), and the pseudo logic model 304 and the test control program 305 restart the operation (step 421). After the restart, the input command is acquired from the interface information 306 (step 422), and the operation according to the command is performed (step 423).

As described above, by transferring the interface information between the operator 401 and the test control program 305 and performing the logic emulation interactively,
The operator controls the logic emulator device 101 from the outside, and the test control program 305 controls the logic emulator device 101 from the inside to enable efficient logic verification. The pseudo-logic model 304 that monitors the interface information 306 as well as the test control program 305 can also control the logic emulator device 101 from the inside. In particular, since it is a logic model, it is excellent in observability of internal signals and the like, and The model 304 can control the logic emulator device 101 by hardware and the test control program 305 can control the logic emulator device 101 by software, and efficient logic emulation is possible.

That is, according to the present embodiment, the interface with the test vector 303a is secured by the test control program 305 provided in the test vector 303a of the test vector storage area 106 and the pseudo logical model 304, and the test vector I / from 303a
The processing control program 201 transmits and receives the O request,
By improving operability and observability using a general-purpose GUI function such as Tcl / Tk, it is possible to efficiently and quickly perform system logic verification by logic emulation.

Next, a logic emulation system 5 in which a logic verification method according to a second embodiment of the present invention is performed.
00 will be described with reference to FIG. In the logic emulation system 500 shown in FIG.
In the following, a method of connecting a dedicated information processing device or the like and performing logic verification of the verification logic chip 508 will be described. As for the configuration, the information processing apparatus 301 (A) connected to the LAN is the same as the first embodiment, and the test vector 303 is the same. In the second embodiment, the information processing device 501 (C) will be described as an example as a personal computer that runs on a Windows OS, which is a general-purpose personal computer OS. The information processing device 501 (C) uses the Tcl / Tk interpreter 5
03, a processing control program 201, a driver control program 601, and a device driver 505.

Then, the parallel I / O is provided to the information processing apparatus C.
Dedicated information processing device 5 connected by interface 506
02 is a control device 507, a verification logic chip 508,
It comprises a RAM 509. Verification logic chip 5 here
Reference numeral 08 denotes a case where the verification target logical structure model 307a (verification target logic 307) in the first embodiment is manufactured as an actual chip. The test vector storage area 106 of the RAM 509 stores the test vectors 303a (test vectors 303) used in the first embodiment.
Set as it is.

The device driver 505 is a Windows
This is a device driver that can control the parallel I / O interface 506 with an s-system OS device driver. The driver control program 601 for controlling the device driver 505 includes the processing control program 2
By having an interface with the connection plug interface 207 of FIG. 1, the processing control program 201 and the device driver 505 are connected, and the processing control program 201 can control the entire system. Then, the dedicated information processing device 502 is controlled by controlling the control device 507 via the device driver.

The Tcl / Tk interpreter 503
Is a Tcl / Tk interpreter for the Windows OS, and the processing control program 201 for the UNIX OS of the first embodiment is the Windows OS as it is.
It can operate with the ws-based OS version.

Therefore, the purpose of the verification of the second embodiment is to set the test vector 30 used in the logic emulation at the time when the logic chip to be mounted on the actual device is manufactured.
3 and the processing control program 201 to verify the logic quality of the logic chip. That is, the logic quality of a single logic chip is verified before verifying the actual system.

Next, an outline of the driver control program 601 is shown in FIG. The driver control program 601 includes a control unit 602 and a processing control program interface unit 6
03, a device driver control unit 604, and a log data collection control unit 605. The control unit 602 controls the entire driver control program 601, and the processing control program interface unit 603 controls RAM access from the processing control program 201 and control instructions for the dedicated information processing device 502. The device driver control unit 604 has an interface with the device driver 505, and controls the parallel I / O interface 506 via the device driver. Log data collection control unit 60
Reference numeral 5 has a function of collecting log data that can be acquired by the driver control program 601 and outputting or storing the log data as log information 504.

Next, a specific processing flow of the second embodiment will be described with reference to FIG. In FIG. 6, the processing flow will be described focusing on the part of the present invention when the test control program 305 generates a message output request and a command input request while the dedicated information processing device 502 is operating. First,
The processing stages in FIG. 6 are divided into the stages of an operator 701, a processing control program 201, a driver control program 601, and a test control program 305, and represent the entire processing flow.

When the above-described verification logic chip 508 is set in the dedicated information processing device 502, the test vector 303a is set in the test vector storage area 106 of the RAM 509, and the operation start instruction wait state is set, the operator 701 issues the verification start instruction. (Step 70)
2). Next, the processing control program 201 issues an operation start instruction to the driver control program 601 (step 703), and the driver control program 601 activates the dedicated information processing device 502 (step 704). When the device operates, the test control program 305 starts operation (step 705). After performing step 703, the processing control program 201 starts monitoring interface information (step 706). In the monitoring of the interface information 306, the driver control program 601 always accesses the RAM and reads the RAM for polling access of the RAM 509 (step 707). In these states, when a message output request and a command input request occur (step 708), the test control program 305 sets the message and event in the interface information (step 709). Next, the processing control program 201 monitoring the interface information 306 detects this event as a request (step 710), and acquires the interface information 306 (step 711). The acquired data is converted (step 712) and displayed on the window as a message (step 71).
3). After the display, the operator 701 performs a key input or a window operation (step 715) in response to the command input request (step 714).

Next, the processing control program 2 in the input waiting state
01 (step 716), acquires the input key input (step 717), and performs data conversion (step 7).
12), RAM 509 as interface information 306
(Step 718), and transferred to the test control program 305 (step 719). After the transfer, the processing control program 201 enters the monitoring state of the interface information 306 again (step 706). The test control program 305 is still operating even after issuing the request in step 708 (step 720), and when detecting an input event from the transferred interface information 306 (step 721), the
Then, an input command is obtained (step 722), and an operation is performed on the obtained command (step 723). Such a series of operations are performed, and the verification logic chip 5 is interactively operated.
08 logic verification is performed.

Further, the test vector 303 and the processing control program 201 common to the first embodiment can be used as they are, and the logic emulation using the verification target logical structure model 105 and the real chip such as the verification logic chip 508 can be performed. Can be verified in the same environment, and consistent logic verification from the logical model to the actual chip can be performed.

That is, common software and test vectors can be used for a logic verification step by logic emulation using the logic emulator device 101 and a logic verification step by a real chip such as the verification logic chip 508. Overlapping labor such as preparing a vector can be reduced, and efficient logic verification can be performed.

Next, a logic emulation system 8 in which a logic verification method according to a third embodiment of the present invention is performed.
00 is shown in FIG. In the logic emulation system 800 of FIG. 7, a logic simulator is added to the first embodiment of FIG. 1, and a logic verification method in which logic emulators and logic simulators having different logic verification levels and logic verification levels are mixed is illustrated. .

In the third embodiment, specifically, for example, the logic simulator 802 performs a logic operation of a microprocessor or the like, and the logic emulator 10
In the first method, by implementing logic such as an I / O control device used in a system including this microprocessor,
Before assembling a system using both real chips,
There may be a case where both logic verifications are performed in an operation in which both cooperate.

The logic simulator 802 in the third embodiment is a function level instruction simulator, and the logic simulator 802 will be described as a micro instruction operation.
On the information processing device 801 (D), a logical emulator control program 109, a processing control program 201,
The logic simulator 802 is started. Among these three programs, the logic simulator 802 is connected by the connection plug interface 207 of the processing control program 201.
Are connected, and the inter-process communication control unit 203 performs inter-process communication. Therefore, it is the processing control program 201 that controls and controls the entire system.

As a procedure of the logic verification, the logic emulator device 101 is operated and brought into an operable state as described in the first embodiment. Next, the processing control program 201 starts the logic simulator 802, and the logic simulator 802
A test vector (test instruction sequence) 806 given to
Set to M model 805. The logic simulator 802 described here is a general function level instruction logic simulator, and the processing control unit 803 and the logic model 80
4 and the RAM model 805 as components.

Next, when the test instruction sequence of the test vector 806 set by the logic simulator 802 is sequentially simulated, when an instruction sequence having a special meaning is simulated, if the special instruction sequence involves a microinstruction operation, the logic The simulator 802 sets the contents of the current RAM model 805 in the interface information 306, and executes the microinstruction operation in the logic emulator device 101.
Request for This request is transmitted to the processing control program 201 via the processing control unit 803, and the set interface information is transferred to the interface information 306 of the logical emulator apparatus 101. Logic simulator 8
02 issues a request and then resumes the simulation of the test instruction sequence. After transferring the interface information, the processing control program 201 operates the logic emulator device 101, and at this time, the logic simulator 802 and the logic emulator device 101 start to operate completely asynchronously. Next, when the emulation is performed for a fixed cycle, the microinstruction operation is completed, and the operation of the logic emulator device 101 is interrupted in the same procedure as in the first embodiment. At this time, the suspended state is transferred to the logic simulator 802 as interface information, and the synchronization / asynchronization control unit 217 synchronizes with the logic simulator 802 operating asynchronously.

The synchronous / asynchronous control unit 217 predicts the completion time of the logic emulation on the logic simulator 802 side when the logic simulator 802 issues a microinstruction operation request. When the simulation is performed for a certain number of instructions, a wait is performed. When the simulation is not completed for a certain number of instructions, a case where the simulation is reported to the logic simulator 802 as an interrupt process is controlled.

The processing control unit 803 manages the reported emulation completion report, and controls the simulation of the test instruction sequence. By repeating these series of processes, logic verification is performed. As described above, in the logic verification method in which the logic simulator 802 and the logic emulator device 101 coexist, the interface information is transferred to each other, and the verification state is made consistent. I do. When connecting the logic simulator 802, the connection is made using the connection plug interface 207, so that connection can be made by any logic verification method as long as the connection interface can be unified. , And a plurality of different logic verification means can be collectively handled.

As described above in the first embodiment, the pseudo logic model 304 incorporated in the logical structure model 105 to be verified, the test control program 305 incorporated in the test vector 303a, The processing control program 201 for externally controlling the logic emulation by incorporating
It is possible to establish a high-speed interactive logic verification method which is excellent in operability and observability by making full use of the high-speed performance of the logic emulator device 101.

Further, as exemplified in the second embodiment, the processing control program 201 is described in a general-purpose language such as Tcl / Tk which does not depend on an execution environment such as an OS, so that By using the test vector 303 and the processing control program 201 used in the embodiment as they are, it is possible to construct an environment in which the logic verification of the real chip such as the verification logic chip 508 can be performed. Logic verification can be performed consistently, and the logic verification can be performed efficiently.

As exemplified in the third embodiment, the logic simulator 802 and the logic emulator 1
01, etc., logic verification methods having different verification levels are connected to each other, and interface information is transferred to each other, so that logic verification with consistency of asynchronous operation is possible. It is possible to consistently verify the logic of the entire large-scale logic device, such as the entire system including the / O control device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is.

[0065]

According to the logic verification method of the present invention, there is an effect that the system logic verification by the logic emulation of the whole logic chip can be efficiently performed in a short time.

Further, there is an effect that the man-machine interface can be enhanced and the observability and operability of the internal state in the logic emulation and the testability can be improved.

Further, there is an effect that a consistent logic verification from the logic model to the actual chip can be realized.

Further, it is possible to shorten the man-hour and period required for constructing the environment of the logic verification, thereby achieving the effect of reducing the cost in the logic verification process.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an example of a configuration of an information processing system in which a logic verification method according to a first embodiment of the present invention is performed.

FIG. 2 is a conceptual diagram showing an example of a software configuration for realizing the logic verification method of the present invention.

FIG. 3 is a flowchart illustrating an example of an operation of the logic verification method according to the first embodiment of the present invention.

FIG. 4 is a conceptual diagram illustrating an example of a configuration of an information processing system in which a logic verification method according to a second embodiment of the present invention is performed.

FIG. 5 is a conceptual diagram showing an example of a configuration of software used in a logic verification method according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing an example of the operation of the logic verification method according to the second embodiment of the present invention.

FIG. 7 is a conceptual diagram illustrating an example of a configuration of software used in a logic verification method according to a third embodiment of the present invention.

FIG. 8 is a conceptual diagram showing an example of a configuration of a logic emulation system which is a reference technique of the logic verification method of the present invention.

[Explanation of symbols]

100: logic emulation system, 101: logic emulator device, 102: control device, 103: RA
M, 104: clock generation device, 105: storage area of the logical structure model to be verified, 106: storage area of test vector, 107: control signal pin, 108: information processing device,
109: logic emulator control program, 110: control unit, 111: logic compiler, 112: RAM access unit, 113: GUI control unit, 113: graphical user interface control unit, 114: logic to be verified,
114a: Logical structure model to be verified, 201: Processing control program, 202: GUI control unit, 203: Inter-process communication control unit, 204: Logical emulator control unit, 20
5 ... test vector control unit, 206 ... data conversion unit, 2
07: connection plug interface, 208: trigger event control unit, 209: operation control unit, 210: RAM access unit, 211: processing control unit, 212: display unit, 21
3. Input control unit, 214 Window control unit, 215
Setting information control unit, 216: log data collection control unit, 21
7, a synchronous / asynchronous control unit, 300, a logical emulation system, 301, an information processing device, 302, an information processing device, 303, a test vector, 303a, a test vector, 304, a pseudo logical model (second logical structure model), 305: test control program, 306: interface information, 307: logic to be verified, 307a: logical structure model to be verified (first logical structure model), 308
... Log information, 500 ... Logic emulation system,
501: information processing device, 502: dedicated information processing device, 5
03: Tcl / Tk interpreter, 504: log information,
505: device driver, 506: parallel I / O interface, 507: control device, 508: verification logic chip (target logic device), 509: RAM, 601: driver control program, 602: control unit, 603: processing control program interface Unit, 604: device driver control unit, 605: log data collection control unit, 800 ...
Logic emulation system, 801, information processing device, 802, logic simulator, 803, processing control unit,
804: logical model, 805: RAM model, 806 ...
Test vector.

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Claims (3)

[Claims] The test vector used for logic verification in a logic emulator in which a logical structure model of a target logic device to be verified is mounted or a dedicated test device in which a real chip of the target logic device is mounted is included in the test vector. A test control program which enables control of the logic verification by input of the test vector from the processing control program by exchanging information with an emulator or a processing control program provided outside the dedicated test apparatus. A logic verification method characterized by being implemented. 2. The logic verification method according to claim 1, wherein the logic emulator includes a first logic structure model for realizing a logic function equivalent to the target logic device, and the first logic structure model. And a second logical structure model for realizing at least a part of the logical function that provides the operating environment of the target logical device, and requires connection to external hardware for realizing the execution environment of the target logical device. A logic verification method of performing logic verification of the target logic device without performing the logic verification. 3. The logic verification method according to claim 1, wherein the processing control program has a function of transmitting and receiving information to and from the test control program, and a logic emulator control program that controls the logic emulator. A function of exchanging information with the logic simulator that performs software verification of the logic of the target logical device with software, a function of exchanging information with the dedicated test device, A general-purpose graphical computer that visualizes and displays the information and receives user input that are exchanged with at least one of a test control program, the logic emulator control program, the logic simulator, and the dedicated test apparatus.
A logic verification method comprising at least one of a user interface.