JP2000163152A - Electronic controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of consumption current owing to an unnecessary circuit operation and to prevent the malfunction of a device since plural operation clocks simultaneously exist by stopping the other clock while one clock is used and preventing the first clock and the second clock from being simultaneously generated. SOLUTION: CPU 6 has a clock oscillation circuit OSC1 for an operation. CPU 6 operates so that it moves to a low consumption current mode when the non-operation state of an electronic controller continues and sets a mode switch signal 3 to an 'L' level being the consumption current mode lower than 'H'. An oscillation circuit OSC2 starts operating with the signal change of the mode switch signal 3 and the inner switch of a clock switch circuit 9 which is brought into contact with 1a at regular time is connection-changed to 3a-side. The clock signal of OSC1 at regular time is switched to the operation clock of OSC2 at the time of the low consumption current mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic control device having a low current consumption mode in which a current consumption of a circuit is reduced in addition to a normal operation of the electronic control device.

[0002]

2. Description of the Related Art Conventionally, in the case of an electronic control device having a low current consumption mode in addition to a normal operation mode as a known technology, a normal operation mode is controlled by an operation clock generated from the first clock oscillation circuit. Is operated, and in the case of the low current consumption mode, the CPU is once set to the low current consumption mode, and then the operation clock of the apparatus is switched to the second low-speed clock to reduce the current consumption of the apparatus, thereby reducing the current consumption of the apparatus. Is realized.

[0003]

In the above prior art, the oscillation circuit of the second low-speed clock is operating even in the normal operation mode, and wasteful circuit current is consumed by the operation current of this oscillation circuit. And the malfunction of the device due to the interference between the first clock and the second clock, and the influence on the peripheral circuits and other devices due to the electromagnetic noise emitted from the device including the second clock component. It needed to be considered.

[0004]

The above problem is solved by using a switching circuit for switching between a first operation clock used during normal operation in the electronic control unit and a second operation clock used during operation in the low current consumption mode. This can be achieved by stopping the other clock while using one clock and not simultaneously generating the first clock and the second clock.

In other words, it is possible to eliminate an increase in circuit current consumption due to unnecessary circuit operations in the electronic control device, a malfunction of the device due to the simultaneous presence of a plurality of operation clocks, and the effect of electromagnetic noise on peripheral devices and equipment. .

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

The CPU has a clock oscillating circuit OSC1 for operating, and the clock generated by this circuit is
At the same time, this clock signal, which is used as a clock for operating the PU, is once frequency-divided and is commonly used as an operation clock for the gate array 7 and the input / output circuit 8 as other peripheral devices.

The CPU 6 operates so as to shift to the low current consumption mode when the inactive state of the electronic control device continues.
That is, the mode switching signal 3 is set to “L” level which is a lower current consumption mode than normal “H”.

Due to the change of the mode switching signal, the oscillation circuit of the OSC2 starts operating. At the same time, the connection state of the internal switch of the clock switching circuit, which was normally in contact with 1a, is changed to 3a side. While the clock signal is normally the OSC1 clock signal, it switches to the OSC2 operation clock in the low current consumption mode.

The low current consumption mode is a mode in which the clock is stopped while maintaining the state of each port of the CPU and the memory (standby mode), and the current that normally consumes several hundred milliamps is reduced to about several microamps. ,
In this state, when the terminal of the external interrupt input terminal (NMI: non-maskable interrupt) changes, the OSC1 starts oscillating, and at the same time, the switching signal 3 changes from the “L” level, which is the low current consumption mode, to the “H” level during normal operation. Return to steady state.

In this embodiment, a W / U for controlling the NMI signal in response to an external operation request signal during the low current consumption mode.
(Wake-up signal) circuit is used.

In general, the current consumption of a circuit, such as a CPU, which operates with a clock increases in proportion to the operation clock of the circuit. Even when the device is not operated, if the current consumption of the circuit is large, the load on the battery becomes large and the battery may run down at worst. Therefore, when the device is not operating, it is necessary to reduce the current consumption.

For this reason, the operating frequency of the above-mentioned first oscillation circuit is equivalent to that of a normal operation clock, and the frequency of the operation clock generated by the second oscillation circuit is low in the low current consumption mode. The current consumption can be reduced by setting the frequency to be sufficiently lower than the frequency and performing the minimum operation on a portion that does not depend on the operation of the CPU.

In this embodiment, a PWM output circuit, a digital output circuit, and an input / output circuit connected to the CPU via an address bus and a data bus are described in addition to the above-described circuits. Circuits are also possible.

FIG. 2 shows an example of an oscillation circuit in the CPU.

In the embodiment, the oscillation circuit is constituted by an oscillation circuit using a crystal, and the oscillation and the stop state can be switched by a mode switching signal. Here, the mode switching signal is defined by Table 1, but switching can be performed by the opposite logic.

[0017]

[Table 1]

FIG. 3 shows a circuit configuration of the OSC2. In this embodiment, the circuit is made up of only the CR to simplify the circuit.

FIG. 4 shows a configuration example of the clock switching signal 9. Any configuration having the same function can be used.

As can be seen from the present embodiment, the circuit is configured so that the first oscillation circuit and the second oscillation circuit do not operate at the same time, and the control by interference noise caused by the simultaneous generation of the first and second clocks. It is possible to prevent an erroneous operation of the device itself, adverse effects such as noise on peripheral devices, and an increase in circuit current consumption due to simultaneous operation of both oscillation circuits.

[0021]

According to the present invention, an increase in circuit current consumption due to unnecessary circuit operations in the electronic control device, a malfunction of the device due to the simultaneous presence of a plurality of operation clocks, and a reduction in electromagnetic noise to peripheral devices and equipment. Has the effect of eliminating the effects.

[Brief description of the drawings]

FIG. 1 is a diagram showing an electronic control device that is a main configuration of the present invention.

FIG. 2 is a diagram showing a configuration of a transmission circuit of FIG. 1;

FIG. 3 is a diagram illustrating a configuration of an oscillation circuit in FIG. 1;

FIG. 4 is a clock switching circuit of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... OSC1 clock signal, 1a ... frequency dividing circuit output signal, 2 ... clock signal, 3 ... clock switching signal, 3
a: frequency dividing circuit output signal, 4: NMI signal, 5: bus line, 6: CPU, 7: gate array, 8: input / output circuit,
9: Clock switching circuit.

Claims (4)

[Claims] An interface between a CPU, its peripheral circuits, and the outside.
A circuit for generating a first operation clock in at least one of the constituent circuits, and using the operation clock obtained from the oscillation circuit as a circuit operation clock for other components. Electronic control device. 2. The electronic control device according to claim 1, further comprising a second circuit other than the configuration circuit having the oscillation circuit.
An electronic control device, comprising: an oscillation circuit for the operation clock. 3. The electronic control device according to claim 1, wherein the second operation clock separates the entire device or a part of the device from an operation mode in which the entire device operates with a normal first operation clock. An electronic control device having an operation mode in which a circuit operates. 4. The electronic control device according to claim 1, further comprising means for switching between one operation clock and the other operation clock, and one of the oscillation circuits is operated, and as a result, the first When the second operation clock is supplied to the device, the other oscillation circuit is stopped so that the second operation clock is not supplied to the device. When the second operation clock is supplied to the device, the first operation clock is supplied. Is an electronic control unit characterized by being stopped and not supplied to the device.