JP2000156698A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing circuit that can extract only specific data and add information to the extracted data without the need for an externally mounted circuit. SOLUTION: In a plurality of application interface circuit 103A is provided with a PID filter 1031 that extracts specific stream data designated by a value set to a register PID of a CFR 114 from channel data of a digital satellite broadcast sent as transport stream data and a timing generating circuit 1032 that generates a timing signal S1032 to insert insert packet data to a stream data area not extracted from timing information of unselected stream data among a series of transport stream data and outputs the signal S1032 to an insert packet buffer 106. An insert packet is read from the insert packet buffer 106 by the timing signal S1032.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit used for a digital serial interface.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

[0003] In the data transfer of the IEEE 1394 serial interface, an asynchronous (Asynchronous) method of requesting and acknowledgment request and reception confirmation of the related art is used.
Transfer includes isochronous transfer in which data is always sent from a certain node once every 125 μs.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Transfer is performed in packet units.

FIG. 8 is a diagram showing the byte size of one source packet in isochronous communication. FIG.
FIG. 8A shows a packet size in DVB (Digital Video Broadcast) specification, and FIG. 8B shows a packet size in DSS (Digital Satelite System) specification.

[0006] The source packet size in the DVB specification is
As shown in FIG. 8A, it is 192 bytes of a 4-byte source packet header (SPH; Source Packet Header) and 188 bytes of transport stream data.

On the other hand, as shown in FIG. 8B, the source packet size in the DSS specification is 144 bytes of a 4-byte source packet header (SPH), 10-byte additional data, and 130-byte data. Bytes. Additional bytes are inserted between the source packet header and the data. In the IEEE 1394 standard, the minimum data unit handled is one quadlet (=
(4 bytes = 32 bits), it is necessary that the total of the transport stream data and the additional data be set in a 32-bit unit. However, it is set without additional bytes by default.

FIG. 9 shows original data when data is transmitted by isochronous communication of the IEEE 1394 standard,
FIG. 6 is a diagram illustrating an example of a correspondence relationship with a packet to be actually transmitted.

As shown in FIG. 9, a source packet which is original data is divided into a predetermined number of data blocks after adding a 4-byte source packet header and padding data for adjusting a data length. Is done. Since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks and various headers are all set to multiples of four.

FIG. 10 is a diagram showing a format of a source packet header. As shown in FIG. 10, 25 bits in the source packet header include, for example, a moving picture experts group (MPEG) -TS (Tra) used in digital satellite broadcasting of the above-described DVB system or the like.
When transmitting nsport stream data by isochronous communication, a time stamp used to suppress jitter is written.

Then, such a packet header or CI
Data such as P (Common Isochronous Packet) header
A packet is generated by being added to a predetermined number of data blocks.

FIG. 11 is a diagram showing an example of the basic configuration of an isochronous communication packet. As shown in FIG. 11, the packet of the isochronous communication has a first quadlet of 13 packets.
94 header (Header), 2nd quadlet is header CRC
(Header-CRC), the third quadlet is CIP header 1 (CI
P-Header1), the fourth quadlet is CIP header 2 (CIP-
Header2), the fifth quadlet is the source packet header (SPH), and the sixth and subsequent quadlets are the data area. The last quadlet is the data CRC (Data-
CRC).

The 1394 header has a data-l representing a data length.
ength, the number of the channel to which this packet is transferred (0
63), indicating the processing code
tcode and a synchronization code sy defined by each application. The header CRC is an error detection code of the packet header.

The CIP header 1 includes an SID (Source node ID) area for a transmission node number, a DBS (Data Block Size) area for a data block length, and an FN (FN) for a data division number in packetization. Fraction Number)
QP for number of quadlets in region, padding data
C (Quadlet Padding Count) area, SPH area for flag indicating presence / absence of source packet header, DBC for counter for detecting number of isochronous packets
(Data Block Continuty Counter) area. Note that the DBS area indicates the number of quadlets transferred in one isochronous packet.

The CIP header 2 has an FMT area for a signal format indicating the type of data to be transferred, and an FDF (Format) used corresponding to the signal format.
Dependent Field) area.

The SPH header has a time stamp area in which a value obtained by adding a fixed delay value to the time when the transport stream packet arrives is set. The data CRC is an error detection code of the data field.

The signal processing circuit of the IEEE 1394 serial interface for transmitting and receiving packets having the above-described configuration is mainly composed of an IEEE 1394 serial interface as shown in FIG.
It comprises a physical layer circuit 1 for directly driving a 94 serial bus, and a link layer circuit 2 for controlling data transfer of the physical layer circuit 1.

In the above-described isochronous communication system in the IEEE 1394 serial interface, for example, as shown in FIG. 12, a link layer circuit 2 is connected to a serial interface bus BS via a physical layer circuit 1. And the link layer circuit 2
MPEG Transporter and DVCR (Digital Vid
Application side circuit 3 such as eo Cassette Recorder)
Is connected.

[0019]

By the way, video data such as a movie or a television broadcast is supplied to the link layer circuit 2 via a set top box for digital satellite broadcasting, for example. A plurality of programs are included in one channel of the stream data to the box.

However, the signal processing circuit of the conventional IEEE 1394 serial interface cannot select and output only a specific program. Therefore, in order to extract and output only a specific program from the stream data, an external circuit must be provided, and a specific program must be extracted and input to the link layer circuit 2 here. When only a specific program is extracted, it is necessary to add information on the extracted program and transmit it to the serial interface bus. However, the signal processing circuit of the IEEE 1394 serial interface extracts and extracts the program. A configuration having a function of adding the information to the data has not been realized yet.

The present invention has been made in view of such circumstances, and a purpose thereof is to extract specific data only without requiring an external circuit, and to add information to the extracted data. It is to provide a signal processing circuit that can be added.

[0022]

According to the present invention, there is provided a signal processing circuit for transmitting stream data from an application as packet data to a serial interface bus in a predetermined time cycle. A data extraction circuit for extracting specified data from the stream data from the application side, and inserting specified data into a data area not extracted by the data extraction circuit, and using the extracted data and the inserted data as packet data as the serial interface A transmission circuit for transmitting to the bus.

Further, the present invention is a signal processing circuit for transmitting stream data from an application side as packet data to a serial interface bus in a predetermined time cycle. The signal processing circuit should be extracted from the stream data from the application side. Control means for designating data, holding means for temporarily storing insertion data and reading the stored insertion data when a timing signal is inputted, a data extraction circuit for extracting data specified by the control means, A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from the timing information of the data not extracted by the circuit; and inserting the insertion data read from the holding means into a data area not extracted by the data extraction circuit. And extract data Preliminary insertion data as packet data and a transmission circuit for transmitting to the serial interface bus.

Further, the present invention is a signal processing circuit for transmitting stream data from an application as packet data to a serial interface bus in a predetermined time cycle. The signal processing circuit should be extracted from the stream data from the application. Control means for designating data, holding means for temporarily storing insertion data and reading the stored insertion data when a timing signal is inputted, a data extraction circuit for extracting data specified by the control means, A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from the timing information of the data not extracted by the circuit; and inserting the insertion data read from the holding means into a data area not extracted by the data extraction circuit. , And extraction day And by adding the time information to be output the received data to the application side on the receiving side to insert data, and a transmission circuit for transmitting to the serial interface bus extraction data and insertion data as packet data.

The present invention also relates to a signal processing circuit for transmitting stream data from an application as packet data to a serial interface bus in a predetermined time cycle, comprising a storage means, Control means for specifying data to be extracted from the storage means, holding means for temporarily storing insertion data and reading the stored insertion data when a timing signal is input, and a data extraction circuit for extracting data specified by the control means. A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from timing information of data not extracted by the data extraction circuit; and an insertion read from the holding means in a data area not extracted by the data extraction circuit. Insert data, A first transmitting circuit that adds time information for outputting the received data to the application side on the receiving side to the extracted data and the inserted data and stores the extracted data and the inserted data in the storage unit; and a time information stored in the storage unit. If the time information does not exceed the time of arrival at the receiving side, the time information is transmitted as packet data to the serial interface bus, and it is expected that the time information will exceed the time of reaching the receiving side. And a second transmission circuit for stopping data transmission.

In the present invention, the transmission circuit or the first transmission circuit sets time information of the insertion data based on the timing information generated by the timing generation circuit.

In the present invention, the insertion data inserted by the transmission circuit or the first transmission circuit is information data on the extracted data.

According to the present invention, the data extraction circuit extracts specified data from the stream data from the application. Then, in the transmission circuit, specified data is inserted into the data extracted by the data extraction circuit and the data area not extracted by the data extraction circuit, and the extracted data and the inserted data are transmitted to the serial interface bus as packet data.

Further, in the transmission circuit or the first transmission circuit, time information for outputting the reception data to the application side on the reception side is added to the extracted data and the insertion data.

The extracted data and the insertion data to which the time information has been added by the first transmission circuit are temporarily stored in the storage means. Then, in the second transmission circuit, the data added with the time information stored in the storage unit is read,
If the time information is not expected to exceed the time of arrival at the receiving end, the read data is transmitted as packet data to the serial interface bus. On the other hand, if the time information is expected to exceed the time of arrival at the receiving side, data transmission can be stopped.

[0031]

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

This signal processing circuit comprises a link layer circuit 10, a physical layer circuit 20, and a CPU 30 as a host computer. The link layer circuit 10 includes an application-side circuit 40.
Is connected. As shown in FIG. 1, the application-side circuit 40 includes an MPEG transporter 41, a D / A
(Digital / Analog) converter 42 and IEC958 digital audio circuit 43. Also, 44
Indicates a PLL circuit as a clock supply circuit.
In the following, the application side circuit 4
This will be described as a transporter 41.

The link layer circuit 10 controls the asynchronous transfer and the isochronous transfer and controls the physical layer circuit 20 under the control of the CPU 30. Specifically, as shown in FIG. 1, the link core (Lin
k Core)) 101, host interface circuit (HOST I /
F) 102, Application interface circuit (API
/ F) 103, transmission FIFO (AT
-FIFO) 104, FIFO for receiving asynchronous communication
(AR-FIFO) 105, insert packet buffer (IP
B) 106, a cryptographic processing circuit (CPH) 107, a transmission pre-processing circuit for isochronous communication (T
XOPRE) 108, isochronous communication post-processing circuit (TXOPRO) 109 as a second transmitting circuit, isochronous communication receiving pre-processing circuit (TXIPRE) as a first receiving circuit
110, a reception post-processing circuit (TXIPRO) 111 for isochronous communication as a second receiving circuit, a transmission FIFO (IT-FIFO) 112 for isochronous communication, a reception FIFO (IR-FIFO) 113 for isochronous communication, and holding means Configuration register (Con
configuration Register, hereinafter CFR
114).

In the circuit of FIG. 1, the host interface circuit 102, the transmission FIFO 104, and the reception FIFO 1
05 and the link core 101 constitute an asynchronous communication system circuit. Then, the application interface circuit 103, the encryption processing circuit 107, the pre-transmission processing circuit 108, the post-transmission processing circuit 109, and the pre-reception processing circuit 1
10, post-reception processing circuit 111, transmission FIFO 112,
The reception FIFO 113 and the link core 101 constitute an isochronous communication system circuit.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit for the packets with the physical layer circuit 20 that directly drives the IEEE1394 serial bus BS, and is reset every 125 μs. It comprises a cycle timer, a cycle monitor and a CRC circuit. Then, time data such as a cycle timer is supplied to the isochronous communication processing circuit through the CFR 111.

The host interface circuit 102 mainly includes a CPU 30 as a host computer and a transmission F
Arbitration of writing and reading of asynchronous communication packets with the IFO 104 and the reception FIFO 105, and arbitration of transmission and reception of various data between the CPU 30 and the CFR 114 are performed. For example, when extracting an arbitrary stream (for example, specific program data) from the MPEG transport stream data from the application-side circuit 40 from the CPU 30, the register PID (P
rogram ID) to the PI of the desired stream program data
The value of D is set. When the CPU 30 needs to insert, for example, insert packet data, which is an insert packet to be added as program information, into stream data extracted from MPEG transport stream data, the register I of the CFR 114
The logic “1” is set in PTxGo. Further, for example, from the CPU 30, a plurality of modes (key; key) described later for encrypting the isochronous packet are set, and one of the set encryption modes is selected, and the encryption processing circuit 107 should encrypt the selected mode. If the encryption key selection information is
It is set in the CFR 114 through the host interface 102. Further, for example, the CPU 30 sets the time stamp delay time Txdelay set in the SPH (source packet header) of the isochronous communication packet in the CFR 114 through the host interface 102.

Application interface circuit 10
3 is an application side circuit 40, for example, MPEG
It performs arbitration of transmission and reception of data before and after encryption including the transporter 41, the encryption processing circuit 107, and control signals. Then, for example, the MPEG transporter 4
When transmitting arbitrary program data to the serial interface bus BS from digital satellite broadcast channel data transmitted as transport stream data from No. 1, stream data having a value set in the register PID of the CFR 114 is extracted. Further, when any data is selected and extracted, the application interface circuit 103 uses the timing information of the unselected stream data in the series of transport stream data to extract the unextracted stream data area. To generate an insertion timing signal for inserting the insert packet data.

FIG. 2 is a block diagram showing a configuration example of a stream data extraction system circuit in the application interface circuit 103, and FIG. 3 is a timing chart of the circuit in FIG. Stream data extraction system circuit 103A
As shown in FIG. 2, a PID filter 1031, a timing generation circuit 1032, and a multiplexer 103
3.

The PID filter 1031 extracts specific stream data specified by the value set in the register PID of the CFR 114 from channel data of digital satellite broadcasting transmitted as transport stream data.

The timing generation circuit 1032 inserts insert packet data into the stream data area not extracted by the PID filter 1031 from the timing information of the stream data not selected from the series of transport stream data. A timing signal S1032 is generated and output to the insert packet buffer 106 and the multiplexer 1033.

The multiplexer 1033 inputs the stream data extracted by the PID filter 1031 to the encryption processing circuit 107 and, when the timing signal S 1032 is input active, reads the stream data from the insert packet buffer 106 instead of the output data of the PID filter 1031. The inserted insert packet is input to the encryption processing circuit 107.

The transmission FIFO 104 includes IEEE13
Asynchronous communication packets to be transmitted to the 94 serial bus BS are stored, and the
The asynchronous communication packet transmitted through the EE1394 serial interface bus BS is stored.

In the insert packet buffer 106,
Desired packet data is written from the CPU 30.
Further, for example, the application interface circuit 1
03, when arbitrary program data is extracted from digital satellite broadcast channel data transmitted as transport stream data from the MPEG transporter 41 and transmitted to the serial interface bus BS, information on the extracted stream data is transmitted. Written as an insert packet. Then, when the insert packet buffer 106 receives the timing signal S1032 in the timing generation circuit 1032 of the application interface circuit 103, the insert packet buffer 106
03 to the multiplexer 1033.

The insert packet buffer 106
Has a capacity of, for example, 188 bytes. Data of up to 188 bytes is valid, and data exceeding this capacity is not transmitted. If the data to be transmitted is 188 bytes or less, data other than the written data is set to "1" and transmitted. The data once written in the insert packet buffer 106 retains its value until data is written again. The data written in the insert packet buffer 106 is encrypted by the encryption processing circuit 107 and transmitted to the transmission FI
The data is transferred to the FO 112. At the time of the transfer, the CF
The register IPTxGo of R114 is set to “1”,
When the transfer is completed, “0” is automatically set and C
By confirming this, the PU 30 confirms the transfer end.

At the time of data transmission, the encryption processing circuit 107 uses the encryption key selection information set by the CPU 30 in the CFR 114 to convert one of the encryption modes (keys) set in the CFR 114 from the CPU 30 into one encryption key. The data to be transmitted input via the application interface circuit 103 is encrypted by, for example, a predetermined common key encryption method using the selected and selected encryption key, and output to the transmission pre-processing circuit 108. Further, the encryption processing circuit 107 detects an encryption mode (key) used for encrypting the encrypted data input via the post-reception processing circuit 111, and converts the encrypted data based on the encryption key information. The data is decrypted and output to the application interface circuit 103.

Here, an example of the encryption mode and the encryption key will be described with reference to FIG. As shown in FIG. 4A, there are three types of encryption modes: mode A, mode B, and mode C. In addition, there is no encryption. The contents of the encryption modes A, B, and C are as follows. Encryption mode A does not allow copying (Never Cppy),
Encryption mode B permits copying only once (Copy Once),
In the encryption mode C, no further copying is permitted and encryption is not performed (No MOre Copy). Also, the encryption key includes
As shown in FIG. 4B, an even key (Even) key and an odd key
(Odd) There are two types of keys. Therefore, there are six types of encryption keys for performing encryption: mode A, odd number, mode A, even number, mode B, odd number, mode B, even number, mode C, odd number, mode C, even number.

FIG. 5 is a block diagram showing a configuration example of the encryption processing circuit 107. As shown in FIG. 5, the encryption processing circuit 107 includes an encryption mode selection circuit 1071, an encryption mode detection circuit 1072, a multiplexer 1073, and an encryption engine circuit 1074.

At the time of data transmission, the encryption mode selection circuit 1071 determines the CPU 30 based on the encryption key selection signal (information) S114 set in the CFR 114 from the CPU 30.
, Selects one of the six encryption modes (key; key) set in the CFR 114 and outputs it to the encryption engine circuit 1074. At the time of data reception, based on the encryption key selection signal S1072 from the encryption mode detection circuit 1072, of the six encryption modes (key; key) set in the CFR 114 from the CPU 30.
One encryption key is selected and output to the encryption engine circuit 1074.

The encryption mode detection circuit 1072 detects an encryption mode (key) used for data encryption from the encryption information input via the post-reception processing circuit 111, and outputs the detection result to an encryption key selection signal S1072. Is output to the encryption mode selection circuit 1071.

The multiplexer 1073 inputs the transmission data via the application interface circuit 103 to the encryption engine circuit 1074 at the time of transmission, and inputs the reception data encrypted by the post-reception processing circuit 111 to the encryption engine circuit 1074 at the time of reception. .

At the time of transmission, the encryption engine circuit 1074 encrypts the transmission data input via the multiplexer 1073 based on the encryption key designated by the encryption mode selection circuit 1071 and transmits the encrypted data together with the encrypted information to the transmission preprocessing circuit 108. Upon reception, the received data input via the multiplexer 1073 is decrypted based on the encryption key specified by the encryption mode selection circuit 1071 and is output to the application interface circuit 103.

The pre-transmission processing circuit 108 is the encryption processing circuit 1
07 to receive the encrypted data to be transmitted, and
For isochronous communication according to the 1394 standard, the data length is adjusted in quadlet (4 byte) units, and a source packet header (SPH) of 4 bytes (+4 bits) is added and stored in the transmission FIFO 112.

The transmission pre-processing circuit 108 includes a transmission FIFO
When storing the transmission data in the 112, as shown in FIG. 6A, 4 bits (32 to 36 bits) are added to a 4 byte (0 to 31 bits) source packet header,
The encryption information is set and stored using three bits of 33 bits, 34 bits, and 35 bits of the additional bits, and, as shown in FIG. 6B, 4 bytes (0 to 0) of the data area. Similarly, the data payload (Data Payload) indicating the maximum length of 31 bits has 4 bits (32 to 3 bits).
6 bits), and encryption information is set and stored using 3 bits of the additional bits, 33 bits, 34 bits, and 35 bits.

The mode of the encryption information is bit [35: 3].
4], and the key type is indicated by bit [33].
Are indicated by one bit, and depending on the contents, these three bits are
In FIG. 4, they are set as sy [3: 2] and sy [1]. However, bit 32 is unused. That is,
[111] for an even key in mode A, [101] for an even key in mode B, [011] for an even key in mode C, and [110] for an odd key in mode A ], In the case of an odd key in mode B, [10
0], and in the case of an odd key in mode C, it is set to [010]. In the case of no encryption, bit [35:
34]

[00] is set. At this time, bit [3
3] has no meaning.

Further, the transmission preprocessing circuit 108 sets a time stamp for determining the data output time on the receiving side when adding the source packet header. This setting is performed as follows. First, the application side circuit 4
0, for example, the value of the internal cycle register is latched at the timing of receiving the final data of the packet from the MPEG transporter 41. Next, the delay time Txdelay set in the CFR 114 from the CPU 30 via the host interface 102 is added to the value of the cycle register. Then, the added value is inserted (set) as a time stamp into the source packet header of the received packet. Note that when insert packet data is inserted, the time stamp of the insert packet is the time stamp of the insert packet gap (Insertion gap) shown in FIG.
t Pocket Gap) time is set.

FIG. 6A is a diagram for explaining a specific configuration of the time stamp in the source packet header. As shown in FIG. 6A, the time stamp for determining the data output time on the receiving side represents the current time in 25 bits. That is, the time stamp is composed of 25 bits, and the lower 12 bits are the cycle offset CO.
(cycle-offset) area, upper 13 bits are allocated as a cycle count CC (cycle-count) area.
The cycle offset is 0-3071 (12b 1011
11111111) (clock CLK = 24.576 MHz), and the cycle count is 0 to 7999 (13b 1111100111111).
Is counted for one second. Therefore, in principle, the lower 12 bits of the time stamp do not indicate 3072 or more, and the upper 13 bits do not indicate 8000 or more.

The post-transmission processing circuit 109 includes a transmission FIFO.
8 and 11, a 1394 header and CIP headers 1 and 2 are added to the data including the source packet header stored in 112 and output to the transmission circuit of the link core 101. Specifically, as shown in FIG.
Data-length indicating the data length, channel indicating the number of the channel to which this packet is transferred (any of 0 to 63)
, A 1394 header composed of tcode representing a processing code, and sy representing encryption information, and as shown in FIG. 11, an SID (Source no.
de ID) area, DBS (Dat
a Block Size) area, FN (Fraction Number) area for the number of data divisions in packetization, QPC (Quadlet Padding) for the number of quadlets of padding data
Count) area, an SPH area for a flag indicating the presence or absence of a source packet header, and a DBC area for a counter for detecting the number of isochronous packets.
An IP header 1, an FMT area for a signal format indicating the type of data to be transferred, and an FDF (Format Dependent) used corresponding to the signal format.
Field), a CIP header 2 composed of an area is added.

The encryption information sy set in the 1394 header is assigned three bits [3, 2, 1] of the 1394 header. The contents are FIFO11
2 is set based on the encryption information added to the source packet header stored in. In the encryption information, the mode is indicated by two bits of bits [3: 2], and the type of key is indicated by one bit of bit [1].
The bits are set as sy [3: 2] and sy [1] in FIG. That is, [111] when the mode A is an even key, and [10] when the mode B is an even key.
1], [011] for an even key in mode C, [110] for an odd key in mode A, [100] for an odd key in mode B, and [100] for an odd key in mode C. Is set to [010]. In the case of no encryption, bits [3: 2] are

[00] is set. At this time, bit [1] has no meaning.

Also, the post-transmission processing circuit 109 may be insignificant when the packet arrives at the receiving side even if the packet is transmitted due to the relationship between the time stamp value TS and the current time CT. Performs a so-called late (LATE) process that does not transmit the packet. Since the value of the time stamp of the insert packet is the time of the packet gap generated by the timing generating circuit 1032 of the application interface circuit 103, it is the time of the packet gap that determines the LATE processing of the insert packet. .

The pre-reception processing circuit 110
1 receives an isochronous communication packet transmitted on the IEEE 1394 serial bus BS via the H.1, and analyzes the contents of a 1394 header, CIP headers 1, 2 and the like of the received packet, and a 4-byte (+4 bit) source packet header ( SPH), and stores it in the reception FIFO 113.

The reception pre-processing circuit 110 includes a reception FIFO.
When storing the received data in 113, the encryption information set in bits 3, 2, and 1 of the sy area of the 1394 header of the received packet is added to the source packet header and data to be stored in the same manner as in the pre-transmission processing 108. I do.
That is, as shown in FIG. 6A, 4 bytes (0 to 3)
4 bits (32 to 32 bits) in the source packet header of 1 bit
36 bits), encryption information is set and stored by using three bits of 33 bits, 34 bits, and 35 bits of the additional bits, and at the same time, as shown in FIG.
As shown in (4), 4 bits (32 to 36 bits) are added to a data payload (Data Payload) indicating the maximum length of 4 bytes (0 to 31 bits) of the data area, and 33 bits of the additional bits are added. 34 bits, and 35
The encryption information is set and stored using the three bits.

The mode of the encryption information is bit [35: 3].
4], and the key type is indicated by bit [33].
Are indicated by one bit, and depending on the contents, these three bits are
In FIG. 2, they are set as sy [3: 2] and sy [1]. However, bit 32 is unused. That is,
[111] for an even key in mode A, [101] for an even key in mode B, [011] for an even key in mode C, and [110] for an odd key in mode A ], In the case of an odd key in mode B, [10
0], and in the case of an odd key in mode C, it is set to [010]. In the case of no encryption, bit [35:
34]

[00] is set. At this time, bit [3
3] has no meaning.

The post-reception processing circuit 111 includes a reception FIFO.
113 reads the source packet header and data stored in the storage unit 113, and adds the added encryption information to the encryption processing circuit 1.
07, and outputs the encrypted data to the encryption engine circuit 1074 via the multiplexer 173. The post-reception processing circuit 111
Reads the time data of the time stamp of the source packet header stored in the FIFO 113 and compares the read time stamp data (TS) with the cycle time (CT) of the cycle timer in the link core 101 at the time of data reading. If the cycle time CT is larger than the time stamp data TS, the data decrypted by the encryption engine circuit 1074 is transmitted to the application interface circuit 103, for example, as an MPEG transport stream data.
Output to the EG transporter 41.

Next, the transmission operation and the reception operation of the isochronous communication packet transmitted through the IEEE 1394 serial interface bus BS will be described.

First, the CPU 30 sets a plurality of modes (key; key) for encrypting the isochronous packet in the CFR 114. And IEEE 1394
When transmitting an isochronous communication packet to the serial interface bus BS, one of the set encryption modes is selected, and encryption key selection information to be encrypted by the encryption processing circuit 107 is transmitted from the CPU 30 through the host interface 102. Set to CFR114.
Further, the CPU 30 sets the time stamp delay time Txdelay set in the SPH (source packet header) of the isochronous communication packet in the CFR 114 through the host interface 102.

In parallel with this, MP of the application side circuit 40 by the MPEG transporter 41, for example.
The EG transport stream data is transmitted to the encryption processing circuit 1 via the application interface circuit 103.
07.

When an arbitrary stream (for example, specific program data) is extracted from the transport stream data, the CPU 30 sends the CFR 11
4, the value of the PID of the desired stream program data is set in the register PID (Program ID). Also, C
When the PU 30 needs to insert insert packet data, which is an insert packet to be added as information of the program, into the stream data extracted from the MPEG transport stream data, for example, the CF 30
The logic “1” is set in the register IPTxGo of R114.

Then, the PI set in the CFR 114
The value of D is supplied to the application interface circuit 103. Application interface circuit 10
In 3, the PID filter 1031 extracts specific stream data specified by a value set in the register PID of the CFR 114 from channel data of digital satellite broadcasting transmitted as transport stream data. The extracted stream data is input to the encryption processing circuit 107 via the multiplexer 1033. In addition, application interface circuit 1
03, in the timing generation circuit 1032, the PID is obtained from the timing information of the stream data not selected from the series of transport stream data.
An insertion timing signal S1032 for inserting the insert packet data into the stream data area not extracted by the filter 1031 is generated and output to the insert packet buffer 106 and the multiplexer 1033.

In the insert packet buffer 106,
In response to the insertion timing signal S1032, the information data of the extracted stream data written from the CPU 30 is read and input to the encryption processing circuit 107 via the multiplexer 1033.

In the encryption processing circuit 107, at the time of transmission, transmission data via the application interface circuit 103 is input to the encryption engine circuit 1074 via the multiplexer 1073. Further, in the encryption mode selection circuit 1071, based on the encryption key selection signal (information) S114 set in the CFR 114 from the CPU 30, C
One of the six encryption modes (key; key) set in the CFR 114 from the PU 30 is selected,
The information is supplied to the encryption engine circuit 1074.

In the encryption engine circuit 1074, the transmission data input via the multiplexer 1073 is
The data is encrypted based on the encryption key specified by the encryption mode selection circuit 1071 and output to the transmission pre-processing circuit 108.

The pre-transmission processing circuit 108 receives the encrypted data to be transmitted by the encryption processing circuit 107, and
A source packet header (SPH) of 4 bytes (+4 bits) whose data length is adjusted in quadlets (4 bytes) for isochronous communication of the E1394 standard
And is stored in the transmission FIFO 112. In the source packet header, a time stamp for determining the data output time on the receiving side is set. This setting is performed as follows. First, the value of the internal cycle register is latched at the timing when the final data of the packet is received from the application side circuit 40, for example, the MPEG transporter 41. Next, the delay time Txdelay set in the CFR 114 from the CPU 30 via the host interface 102 is added to the value of the cycle register. Then, the added value is inserted into the source packet header of the received packet as a time stamp (setting).
Is done. When the insert packet data is inserted, the time stamp of the insert packet is set to the insert packet gap (Insert Pc) shown in FIG.
ket Gap) time is set.

At this time, in storing the transmission data in the transmission FIFO 112, the transmission pre-processing circuit 108 adds 4 bits (32 to 36 bits) to the 4-byte (0 to 31 bits) source packet header. , 34 bits of the additional bits, and 3
The encryption information is set using 3 bits of 5 bits, and 4 bits (32 to 36 bits) are also added to the data payload (Data Payload) indicating the maximum length of 4 bytes (0 to 31 bits) of the data area. Are added, and the encryption information is set and stored using three bits of the additional bits, 33 bits, 34 bits, and 35 bits.

The transmission data stored in the FIFO 112 is read by the post-transmission processing circuit 109, and the data including the source packet header is added to the 1394 header,
The IP headers 1 and 2 are added and output to the transmission circuit of the link core 101. At this time, the encryption information sy set in the additional bits is the bit [3, 3
2,1]. The contents are set based on the encryption information added to the source packet header stored in the FIFO 112.

Further, in the post-transmission processing circuit 109, when a packet is transmitted and the packet arrives at the receiving side due to the relationship between the time stamp value TS and the current time CT, the time has passed and the packet becomes meaningless. , A LATE process that does not transmit the packet is performed.

The packet data input to the transmission circuit of the link core 101 is transmitted to the physical layer circuit 2
0 is transmitted as an isochronous communication packet to the IEEE 1394 serial interface bus BS.

The isochronous communication packet transmitted through the IEEE 1394 serial bus BS and having the encryption information set in the 1394 header is input to the reception pre-processing circuit 110 via the physical layer circuit 10 and the link core 101. .

The pre-reception processing circuit 110 analyzes the contents of the received packet, such as the 1394 header, CIP headers 1 and 2, and stores the source packet header and data in the FIFO 113
Is written to. At this time, the reception preprocessing circuit 110 adds 4 bits (32 to 36 bits) to a 4-byte (0 to 31 bits) source packet header when storing the reception data in the reception FIFO 113,
The encryption information is set using 3 bits of 33 bits, 34 bits and 35 bits of the additional bits, and 4 bytes (0 to 31 bits) of the data area
Similarly, 4 bits (32 to 36 bits) are added to a data payload (Data Payload) indicating the maximum length of the data, and the encryption information is generated using 3 bits of 33 bits, 34 bits, and 35 bits of the additional bits. Set and stored.

The source packet header and the received data stored in the FIFO 113 are read out by the post-reception processing circuit 111, and the encryption information of the additional bits is supplied to the encryption mode detection circuit 1072 of the encryption processing circuit 107, The encrypted data is supplied to the encryption engine circuit 1074 via the multiplexer 173. In the post-reception processing circuit 111, the time data of the time stamp of the source packet header stored in the FIFO 113 is read, and the read time stamp data (TS) and the cycle time (CT) by the cycle timer in the link core 101 are read. ), And when the cycle time CT is larger than the time stamp data TS, a data output instruction is supplied to the encryption engine circuit 1074 of the encryption processing circuit 107.

In the encryption processing circuit 107, the encryption mode detection circuit 1072 uses the encryption information added to the encrypted data input via the post-reception processing circuit 111 to determine the encryption used for encrypting the data. The mode (key) is detected. The detection result is output to the encryption mode selection circuit 1071 as the encryption key selection signal S1072. In the encryption mode selection circuit 1071,
Based on the encryption key selection signal S1072, the six encryption modes (key; k
ey), one of the encryption keys is selected, and the information is supplied to the encryption engine circuit 1074.

The encryption engine circuit 1074 decrypts the received data input via the multiplexer 1073 based on the encryption key specified by the encryption mode selection circuit 1071. Then, the decoded data is output to the MPEG transporter 41 as, for example, MPEG transport stream data via the application interface circuit 103 at the time designated by the post-reception processing circuit 111.

As described above, according to the present embodiment, the CFR 114 is transmitted to the application interface circuit 103 from digital satellite broadcast channel data transmitted as transport stream data.
A PID filter 1031 for extracting specific stream data specified by the value set in the register PID of
Insertion timing signal S1032 for inserting insert packet data into a stream data area not extracted from the timing information of stream data not selected from the series of transport stream data
And a timing generation circuit 1032 for generating the data and outputting the data to the insert packet buffer 106, and reading out the insert packet from the insert packet buffer 106 by the insert timing signal S1032, without requiring an external circuit. There is an advantage that specific data can be extracted and information can be added to the extracted data.

In the present embodiment, at the time of data transmission, based on the encryption key selection information set in the CFR 114 by the CPU 30, one of the encryption modes (keys: key) set in the CFR 114 by the CPU 30 is used. The data to be transmitted input through the application interface circuit 103 is encrypted by, for example, a predetermined common key encryption method using the encryption key, and output to the pre-transmission processing circuit 108 and the post-reception processing circuit 111 is selected. A cryptographic processing circuit for detecting an encryption mode (key) used for encrypting the encrypted data input through the interface, decrypting the encrypted data based on the encryption key information, and outputting the decrypted data to the application interface circuit 103 Since 107 is provided, digital data transmitted or received between different devices Prevents unauthorized copying, moreover an advantage of realizing a good isochronous communication.

In this embodiment, MPEG transport stream data has been described as an example of application-side data. However, it is needless to say that the present invention is not limited to this, and can be applied to digital data such as digital audio. .

[0085]

As described above, according to the present invention,
There is an advantage that it is possible to realize a signal processing circuit capable of extracting specific data only without requiring an external circuit and adding information to the extracted data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an MPEG signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

FIG. 2 is a block diagram showing a configuration example of a stream data extraction circuit in an application interface circuit according to the present invention.

FIG. 3 is a timing chart of the circuit of FIG. 2;

FIG. 4 is a diagram illustrating an example of an encryption mode and an encryption key according to the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a cryptographic processing circuit according to the present invention.

FIG. 6 is a diagram illustrating one form of encryption information added when storing encrypted data in a FIFO;

FIG. 7 is a diagram illustrating an example of setting encryption information in a 1394 header at the time of transmission.

8A and 8B are diagrams showing the byte size of one source packet in isochronous communication, where FIG. 8A shows the packet size under DVB specification and FIG. 8B shows the packet size under DSS specification.

FIG. 9 is a diagram showing an example of a correspondence relationship between original data and data to be actually transmitted when data is transmitted by isochronous communication of the IEEE 1394 standard.

FIG. 10 is a diagram showing a format of a source packet header.

FIG. 11 is a diagram illustrating a basic configuration example of an isochronous communication packet.

FIG. 12 is a block diagram showing a basic configuration of an isochronous communication system circuit in the IEEE 1394 serial interface.

[Explanation of symbols]

10: link layer circuit, 101: link core (Link
Core)), 102: Host interface circuit (Host I /
F), 103 ... Application interface circuit (A
PI / F), 103A ... stream data extraction system circuit, 1
031: PID filter, 1032: timing generation circuit, 1033: multiplexer, 104: FIFO for transmission (AT-FIFO) for asynchronous communication, 105: FIFO for receiving (AR-FIFO) for asynchronous communication, 106: insert packet buffer (IPB) ), 107: encryption processing circuit, 1071: encryption mode selection circuit, 1072: encryption mode detection circuit, 1073: multiplexer, 1074
... Encryption engine circuit, 108 ... Transmission preprocessing circuit for isochronous communication (TXOPRE), 109 ... Transmission post-processing circuit for isochronous communication (TXOPRO), 110 ... Reception preprocessing circuit for isochronous communication (TXPRE), 111 ... Post-processing circuit (TXIPRO, 112: FIFO for transmitting isochronous communication (IT-FIFO), 113: FIFO for receiving isochronous communication (IR-FIFO), 114: Configuration register (CFR), 20: physical layer circuit, 30 CPU, 40 application circuit, 41 MPEG transporter, 42 D /
A converter, 43 ... IEC958 digital audio circuit, 44 ... PLL circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (12)

[Claims] 1. A signal processing circuit for sending stream data from an application as packet data to a serial interface bus in a predetermined time cycle, and extracting specified data from the stream data from the application. A signal processing circuit comprising: a data extraction circuit; and a transmission circuit for inserting specified data into a data area not extracted by the data extraction circuit, and transmitting the extracted data and the inserted data as packet data to the serial interface bus. 2. The insertion data inserted by the transmission circuit is information data on the extracted data.
A signal processing circuit as described. 3. A signal processing circuit for transmitting stream data from an application side as packet data to a serial interface bus in a predetermined time cycle, and designates data to be extracted from the stream data from the application side. Control means, insertion data is temporarily stored, and holding means for reading stored insertion data when a timing signal is inputted; a data extraction circuit for extracting data specified by the control means; and a data extraction circuit which is not extracted by the data extraction circuit A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from the timing information of the data; and inserting the insertion data read from the holding means into a data area not extracted by the data extraction circuit to extract extracted data. And insert Signal processing circuit having a data as packet data and a transmission circuit for transmitting to the serial interface bus. 4. The insertion data inserted by the transmission circuit is information data relating to the extracted data.
A signal processing circuit as described. 5. A signal processing circuit for transmitting stream data from an application side as packet data to a serial interface bus in a predetermined time cycle, and designates data to be extracted from the stream data from the application side. Control means, insertion data is temporarily stored, and holding means for reading stored insertion data when a timing signal is inputted; a data extraction circuit for extracting data specified by the control means; and a data extraction circuit which is not extracted by the data extraction circuit A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from the timing information of the data; inserting the insertion data read from the holding means into a data area not extracted by the data extraction circuit; And insert Signal processing circuit and a transmission circuit for transmitting by adding time information to be output the received data to the application side on the receiving side over data, the extracted data and the insertion data as packet data to the serial interface bus. 6. The signal processing circuit according to claim 5, wherein said transmission circuit sets time information of said insertion data based on timing information generated by said timing generation circuit. 7. The insertion data inserted by the transmission circuit is information data on the extracted data.
A signal processing circuit as described. 8. The data inserted in the transmission circuit is information data on the extracted data.
A signal processing circuit as described. 9. A signal processing circuit for transmitting stream data from an application as packet data to a serial interface bus in a predetermined time cycle, wherein the signal processing circuit is to extract from the storage means and the stream data from the application. Control means for designating data; holding means for temporarily storing insertion data and reading the stored insertion data when a timing signal is input; a data extraction circuit for extracting data designated by the control means; A timing generation circuit for generating a timing for reading the insertion data stored in the holding means from the timing information of the data not extracted by the circuit; and inserting the insertion data read from the holding means into a data area not extracted by the data extraction circuit. , And extraction day A first transmitting circuit for adding time information to output received data to the application side on the receiving side to the data and the insertion data, and storing the data in the storage means; and data to which the time information stored in the storage means is added. If the time information does not exceed the time of arrival at the receiving side, it is transmitted as packet data to the serial interface bus, and the time information is expected to exceed the time of reaching the receiving side. And a second transmission circuit for stopping data transmission. 10. The signal processing circuit according to claim 9, wherein said first transmission circuit sets time information of said insertion data based on timing information generated by said timing generation circuit. 11. The signal processing circuit according to claim 9, wherein the insertion data inserted by the first transmission circuit is information data on the extracted data. 12. The signal processing circuit according to claim 10, wherein the insertion data inserted by the first transmission circuit is information data on the extracted data.