JP2000156421A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a structure, wherein the gate length of the field-effect transistor of a semiconductor circuit part is not subjected to restrictions on the base width of the bipolar transistor of a protective circuit part. SOLUTION: An n+ drain region 26a and an n+ impurity region 12b are isolated from each other by a field oxide film 18b. The region 26a is connected with a wiring layer 36b via an n-type well 14 and the region 12b. As a protective circuit part 100 has a Zener diode 8, the diode 8 can be made to break out a Zener breakdown before a parasitic diode 38 breaks out an avalanche breakdown. As a result, a current using a surge, such as static electricity, is made to flow to a bipolar transistor 2 without being made to flow to a MOS transistor 4 and the electrostatic breakdown of the transistor 4 is prevented from being caused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device provided with a protection circuit unit for protecting a semiconductor circuit unit from surges such as static electricity.

[0002]

2. Description of the Related Art In a semiconductor device, an input / output circuit portion and the like are prevented from being electrostatically damaged by surges such as static electricity.
It is necessary to increase SD (electrostatic discharge) withstand voltage. As a background technology for increasing the ESD withstand voltage, a technology disclosed in Japanese Patent Application Laid-Open No. 7-202126 is known. This background technology will be described with reference to FIG. FIG. 13 is a sectional view of a semiconductor device according to this background art.

In this semiconductor device, an output transistor 802 is provided in a P well 801 formed in a semiconductor substrate.
And a bipolar transistor (BP) 804 are formed. M of N-type LDD (Lightly Doped Drain) structure
The output transistor 802 which is an OSFET has a gate electrode 806, and has an N ⁺ region 810 as a source region and an N ⁺ region 812 as a drain region. Bipolar transistor (BP) 804 has N ⁺ region 812 as a collector region, P well 801 as a base region, and N ⁺ region 814 as an emitter region. Here, N ⁺ region 810 is connected to a GND line (ground potential) via wiring layer 820. The N ⁺ region 812 is connected to a pad 830 (an output terminal, an input / output terminal, an input terminal, etc.) via a wiring layer 822. N ⁺ region 814 is connected to a GND line or a given discharge line via wiring layer 824.

A feature of this background art is that the gate length (effective channel length) L of the output transistor 802 is longer than the base width (effective base width) BW of the bipolar transistor (BP) 804. By doing so, when a high voltage pulse (surge) 832 is applied to pad 830, instead of parasitic bipolar transistor 802 constituted by N ⁺ region 812, P well 801 and N ⁺ region 810, bipolar transistor 804
Can be turned on. As a result, a large current can be prevented from flowing through the parasitic bipolar transistor 802, and the output transistor 802 (particularly, the gate insulating film) can be prevented from being electrostatically damaged.

[0005]

As described above, in this background art, the gate length L of the output transistor 802 is
By making the base width longer than the base width BW of the bipolar transistor 804, a current caused by a surge flows through the bipolar transistor 804.

Accordingly, in this background art, the gate length L of the output transistor 802 is
, Which cannot be made smaller than the base width BW. Due to this restriction, for example, the gate length L cannot be set to the minimum dimension in the design rule, which hinders miniaturization of the semiconductor device.

The present invention has been made to solve such a problem, and an object of the present invention is to restrict the gate width of a field-effect transistor in a semiconductor circuit portion to the limitation on the base width of a bipolar transistor in a protection circuit portion. An object of the present invention is to provide a semiconductor device having a structure that does not receive the semiconductor device.

[0008]

The present invention comprises a semiconductor circuit portion formed on a semiconductor substrate, and a protection circuit portion formed on the semiconductor substrate for preventing surge breakdown of the semiconductor circuit portion. Wherein the semiconductor circuit portion includes a field-effect transistor, wherein the field-effect transistor has a first region of a first conductivity type in which a channel region is formed, and first and second regions of a second conductivity type. 2 Sources /
And a drain region, wherein the protection circuit portion includes a bipolar transistor, a zener diode, an element isolation insulating layer, and a second conductive type connection region, and the bipolar transistor has a second conductive type second region, A first conductive type third region and a second conductive type fourth region; a wiring layer is electrically connected to the second region; and the zener diode is connected to the second region and the first conductive type. A fifth region, wherein the element isolation insulating layer includes the second region and the first region.
And the connection region electrically connects the second region and the first source / drain region.

The reason why the semiconductor device according to the present invention having the above-described structure can flow a current (hereinafter, referred to as a current) due to a surge of static electricity or the like to a protection circuit portion and prevent electrostatic breakdown of the semiconductor circuit portion. I do. The field effect transistor has a parasitic diode formed by a junction between the first source / drain region and the first region of the first conductivity type. According to the semiconductor device of the present invention, since the semiconductor device includes the Zener diode, it is possible to cause the Zener diode to undergo Zener breakdown before the parasitic diode undergoes avalanche breakdown. Therefore, current flows from the second region through the Zener diode. The bipolar transistor is turned on by the voltage drop, and the current is discharged to the outside through the fourth region.

As described above, according to the semiconductor device of the present invention, there is no restriction that the gate length of the field effect transistor must be longer than the base width of the bipolar transistor. Therefore, for example, the gate length can be set to the minimum size according to the design rule, whereby the semiconductor device can be miniaturized.

In this specification, the first source /
The drain region means a region that performs at least one of a source region and a drain region. Second
Have the same meaning.

In the semiconductor device according to the present invention, it is preferable that the semiconductor circuit section and the protection circuit section have a silicide layer. First, the reason why the silicide layer is formed in the semiconductor circuit portion will be described, and then, the reason why the protection circuit portion preferably has a silicide layer will be described.

To miniaturize a semiconductor device, a MOS
As the planar dimensions of the transistor are reduced, the depth of the source / drain regions needs to be reduced. However,
When the depth of the source / drain region is reduced, the resistance of the source / drain region increases. Therefore, in order to suppress this, a salicide structure in which a silicide layer is formed in a self-aligned manner on the surface of the source / drain region is employed.

[0014] The silicide layer is formed in the semiconductor circuit section for the above reasons. Forming the silicide layer only in the semiconductor circuit portion and not in the protection circuit portion complicates the patterning of the silicide layer. Therefore, the silicide layer is also formed in the protection circuit portion.

In the structure provided with the silicide layer, the fifth region is formed in the third region, and the first region has a first conductivity type impurity concentration of the first region. It is desirable that the concentration be higher than the type impurity concentration.

This makes it possible to prevent the junction between the second region and the third region from easily undergoing dielectric breakdown. The reason will be described below.

Since the resistance of the silicide layer is smaller than the resistance of the second region, the current flowing through the wiring layer flows through the silicide layer. If the first-conductivity-type impurity concentration in the fifth region is lower than the first-conductivity-type impurity concentration in the third region, the current flowing through the silicide layer is increased by the junction (Zener diode) between the second and fifth regions. Most of the current flows into the junction between the second region and the third region near the silicide layer. As a result, this joint may cause dielectric breakdown.

According to the semiconductor device of the present invention, the fifth
Since the first-conductivity-type impurity concentration in the region is higher than the first-conductivity-type impurity concentration in the third region, most of the current flows through the junction (zener diode) between the second and fifth regions, and the vicinity of the silicide layer It is possible to prevent current from concentrating on the junction between the second region and the third region. Therefore, the junction between the second region and the third region can be prevented from easily undergoing dielectric breakdown.

In the semiconductor device according to the present invention, the protection circuit section includes an interlayer insulating layer, and the interlayer insulating layer includes
A contact hole formed on the second region;
The wiring layer is formed in the contact hole,
It is desirable that the distance between the contact hole and the element isolation insulating layer is a minimum dimension according to a design rule.

The semiconductor device according to the present invention prevents electrostatic breakdown of the field-effect transistor by flowing a current through the Zener diode. When a current flows through the Zener diode, heat is generated at the junction of the Zener diode. In the semiconductor device according to the present invention, by setting the distance between the contact hole and the element isolation insulating layer to the minimum dimension in the design rule, the influence of the heat on the contact portion between the wiring layer and the second region is reduced. are doing. Note that the influence of heat means that the contact portion is broken by the heat, thereby causing a leak current in the semiconductor substrate.

In the semiconductor device according to the present invention, it is preferable that a Zener voltage of the Zener diode is lower than an avalanche breakdown voltage of a parasitic diode including the first source / drain region and the first region.

By doing so, it is possible to surely cause the Zener diode to undergo the Zener breakdown before the avalanche breakdown of the parasitic diode.

In the semiconductor device according to the present invention, it is preferable that a Zener voltage of the Zener diode is lower than a snapback voltage of a parasitic diode including the first source / drain region and the first region.

By doing so, the current can be stably discharged through the bipolar transistor.

In the semiconductor device according to the present invention, it is preferable that a Zener voltage of the Zener diode is equal to or higher than an absolute maximum rated voltage of the semiconductor device.

By doing so, the leak current in the drain region during normal operation can be effectively reduced.

In the semiconductor device according to the present invention, it is preferable that a Zener voltage of the Zener diode is controlled by a first conductivity type impurity concentration in the fifth region.

In this manner, control for setting the Zener voltage to a desired value can be easily realized.

In the semiconductor device according to the present invention, the semiconductor circuit section includes, for example, an input / output circuit section, an input circuit section, and an output circuit section.

In the semiconductor device according to the present invention, the semiconductor device includes an electrode portion, the electrode portion is formed on the semiconductor substrate, and the electrode portion is electrically connected to an external wiring by bonding. Preferably, the semiconductor circuit portion and the electrode portion are electrically connected via the protection circuit portion.

Since the semiconductor device is electrically connected to an external element through the electrode portion, a current caused by a surge such as static electricity flows into the semiconductor device through the electrode portion. According to this, since the semiconductor circuit portion and the electrode portion are electrically connected via the protection circuit portion, it is possible to prevent the current flowing into the semiconductor device via the electrode portion from flowing into the semiconductor circuit portion. it can.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Device Structure} FIG. 1 is a sectional view of an input / output circuit section of a semiconductor device according to a first embodiment of the present invention. FIG.
1 is a plan view of a semiconductor device according to a first embodiment of the present invention. The structure of the semiconductor device according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 2, the semiconductor device 600 has a chip shape. The semiconductor device 600 includes the logic circuit unit 50
0, an input / output circuit unit 300 and a pad 400.
Logic circuit section 500, input / output circuit section 300, and pad 4
00 is formed on a silicon substrate which is an example of a semiconductor substrate.

The logic circuit section 500 is located at the center of the surface of the silicon substrate.

There are a plurality of input / output circuit units 300, which are located on the surface of the silicon substrate so as to surround the logic circuit unit 500. The input / output circuit unit 300 is an example of a semiconductor circuit unit.

There are a plurality of pads 400, and the input / output circuit 3
It is located on the surface of the silicon substrate which is further outside the area of 00. Each pad 400 is connected to each input / output circuit unit 300
It corresponds to. The pad 400 is bonded. The pad 400 is an example of an electrode unit.

Next, referring to FIG.
Will be described. The input / output circuit unit 300 includes the protection circuit unit 100 and the transistor forming unit 200. In the first embodiment, the protection circuit section is formed in the input / output circuit section. However, the protection circuit section may be formed on a silicon substrate separately from the input / output circuit section. This means
This also applies to the second embodiment described later.

The details of the protection circuit section 100 will be described. The protection circuit section 100 includes the bipolar transistor 2, the Zener diode 8, the field oxide layer 18a, the field oxide layer 18b, and the n-type well 14.

First, the bipolar transistor 2 will be described. In the p-type well 15 of the p-type silicon substrate 10,
The n ⁺ -type impurity regions 12a, 12b
Are formed. N ⁺ -type impurity region 12a serves as an emitter region of bipolar transistor 2. N ⁺ -type impurity region 12b serves as a collector region of bipolar transistor 2. P-type region 15a is formed by n ⁺ -type impurity region 12a and n ⁺ -type impurity region 12a.
The p-type well 15 is located between the impurity regions 12b. The p-type region 15a serves as a base region of the bipolar transistor 2. The n ⁺ -type impurity region 12b is an example of a second region of the second conductivity type, the p-type region 15a is an example of a third region of the first conductivity type, and the n ⁺ -type impurity region 12a is a second region of the second conductivity type.
It is an example of a conductivity type fourth region.

On n ⁺ type impurity regions 12a and 12b,
Silicide layers 20a and 20b are formed respectively. A field oxide layer 18a is formed on the surface of p-type silicon substrate 10. n ⁺ -type impurity region 12a and n ⁺
Type impurity region 12b is separated by field oxide layer 18a.

The Zener diode 8 includes a p ⁺ -type impurity region 16 and an n ⁺ -type impurity region 12b. The p ⁺ -type impurity region 16 is the p-type region 15 under the field oxide layer 18a.
a. Part of the p ⁺ -type impurity region 16 is n ⁺
A junction is formed with a part of the side part and the bottom part of the mold impurity region 12b. The p ⁺ -type impurity region 16 is a field oxide layer 18
No contact with a.

The n-type well 14 is formed in the p-type well 15. One end of the n-type well 14 is in contact with the n ⁺ -type impurity region 12b below the n ⁺ -type impurity region 12b. The other end of the n-type well 14 is in contact with the n ⁺ -type drain region 26a below the n ⁺ -type drain region 26a. The n ⁺ type drain region 26a is a MOS transistor 4
It is a component of. The MOS transistor 4 will be described later. The n-type well 14 is an example of a connection region.

A field oxide layer 18b is formed on the surface of the n-type well 14. N ⁺ -type impurity region 12b and n ⁺ -type drain region 26a are separated by field oxide layer 18b. Field oxide layer 18b is an example of an element isolation insulating layer.

Next, the transistor forming section 200 will be described in detail. A plurality of MOS transistors
A transistor is formed. In this drawing, a MOS transistor 4 is shown. A circuit for input / output control is constituted by these MOS transistors.

The structure of the MOS transistor 4 will be described. The MOS transistor 4 has a gate electrode 22, n ⁺
A drain region 26a and an n ⁺ -type source region 26b.

The n ⁺ type drain region 26a and the n ⁺ type source region 26b have an LDD structure. The n ⁺ -type drain region 26a and the n ⁺ -type source region 26b are formed in the p-type well 15 of the p-type silicon substrate 10 with an interval therebetween. Silicide layers 20c and 20c are formed on n ⁺ -type drain region 26a and n ⁺ -type source region 26b, respectively.
e is formed.

The gate electrode 22 is located on the p-type region 15b via the gate oxide layer 28. The p-type region 15b is the p-type well 15 located between the n ⁺ -type drain region 26a and the n ⁺ -type source region 26b. A channel region is formed in p-type region 15b. The p-type region 15b is an example of a first region.

The gate electrode 22 comprises a polysilicon layer 24,
Silicide layer 20d located on polysilicon layer 24
And are laminated. Sidewall oxide layers 30a and 30b are formed on one side surface and the other side surface of the gate electrode 22, respectively.

N ⁺ type drain region 26a and p type region 15
The parasitic diode 38 is constituted by b. Parasitic bipolar transistor 6 is constituted by n ⁺ type drain region 26a, p type region 15b and n ⁺ type source region 26b.

Next, the upper layers of the protection circuit section 100 and the transistor formation section 200 will be described. Protection circuit section 1
A silicon oxide layer 32 is formed on the p-type silicon substrate 10 so as to cover the transistor 00 and the transistor forming section 200. The silicon oxide layer 32 is an example of an interlayer insulating layer.
In the silicon oxide layer 32, a contact hole 34a exposing a part of the silicide layer 20a,
A contact hole 34b exposing a part of b is formed.

On the silicon oxide layer 32, a wiring layer 36a,
36b is located. The wiring layers 36a and 36b are made of, for example, an aluminum alloy. The wiring layer 36a is grounded. The wiring layer 36a is embedded in the contact hole 34a, and is electrically connected to the n ⁺ -type impurity region 12a via the silicide layer 20a. Wiring layer 36
b is electrically connected to the pad 400. Wiring layer 3
6b is buried in the contact hole 34b and is electrically connected to the n ⁺ -type impurity region 12b via the silicide layer 20b.

Note that no contact hole is formed on the n ⁺ -type drain region 26a (silicide layer 20c), and the drain voltage to the n ⁺ -type drain region 26a is
The voltage is applied through the wiring layer 36b, the n ⁺ -type impurity region 12b, and the n-type well 14. On the other hand, a contact hole is formed on n ⁺ type source region 26b (silicide layer 20e) at a location different from the cross section. In this contact hole, a wiring layer electrically connected to n ⁺ type source region 26b is formed.

{Equivalent Circuit} FIG. 3 is an equivalent circuit diagram of the input / output circuit of the semiconductor device according to the first embodiment of the present invention. An equivalent circuit of the input / output circuit unit of the semiconductor device according to the first embodiment will be described with reference to FIG. Pad 40
The wiring (wiring layer) 36b from 0 is electrically connected to the input / output circuit unit 300. The input / output circuit unit 300 includes the protection circuit unit 100 and the transistor forming unit 200.

The protection circuit section 100 includes the bipolar transistor 2 and the Zener diode 8. The emitter and base of bipolar transistor 2 and the anode of Zener diode 8 are electrically connected to ground line V _SS . The collector of bipolar transistor 2 and the cathode of Zener diode 8 are electrically connected to wiring (wiring layer) 36b from pad 400.

The transistor forming portion 200 has an n-type MO
A plurality of S transistors 4 and a plurality of p-type MOS transistors are formed. The wiring (wiring layer) 36b from the pad 400 is electrically connected to these MOS transistors via the protection circuit section 100.

{Operation of Protection Circuit} The operation of the protection circuit unit 100 will be described with reference to FIG. 1 and FIG. The current due to the surge such as static electricity is supplied to the pad 400 and the wiring (wiring layer).
The current flows into the n ⁺ -type impurity region 12b via the gate 36b. Since the protection circuit section 100 has the Zener diode 8,
Before the parasitic diode 38 undergoes avalanche breakdown, the Zener diode 8 can be caused to undergo Zener breakdown. Therefore, current flows from Zener diode 8 from n ⁺ type impurity region 12b. As a result, the bipolar transistor 2 is turned on by the voltage drop, and the current is discharged to the outside through the n ⁺ -type impurity region 12a. By the above operation, the transistor forming section 200
Of the MOS transistor is prevented.

As described above, in the semiconductor device according to the first embodiment, the Zener diode 8 is caused to undergo Zener breakdown before the parasitic diode 38 undergoes avalanche breakdown, so that current does not flow through the MOS transistor 4, It flows to the bipolar transistor 2. Therefore, according to the semiconductor device of the first embodiment, there is no restriction that the gate length of the MOS transistor 4 must be longer than the base width of the bipolar transistor 2, and the gate length can be reduced. As a result, according to the semiconductor device according to the first embodiment, the semiconductor device can be made compact while securing a high ESD withstand voltage.

Also, as shown in FIG. 1, the first embodiment
In the semiconductor device according to the embodiment, p ⁺Type impurity region 16
Is the p-type impurity concentration of the p-type region 15a.
taller than. This gives n⁺-Type impurity region 12b and p-type
In order to prevent the dielectric breakdown of the joint 44 in the region 15a easily.
can do.

That is, the resistance of the silicide layer 20b is n
Since it is smaller than the resistance of ⁺ type impurity region 12b, wiring layer 3
The current flowing through 6b flows through the silicide layer 20b. If the p-type impurity concentration of p ⁺ -type impurity region 16 is lower than the p-type impurity concentration of p-type region 15a, silicide layer 2
The current flowing through 0b does not flow much into the Zener diode 8, and most of the current flows into the junction 44 near the silicide layer 20b. As a result, the joint 44 may cause dielectric breakdown.

According to the semiconductor device according to the first embodiment, the p-type impurity concentration of the p ⁺ -type impurity region 16 which is a component of the Zener diode 8 is the same as that of the p-type region 15a which is a component of the bipolar transistor 2. Is higher than the p-type impurity concentration of p ⁺ -type impurity region 1
6, and the current can be prevented from being concentrated on the junction 44 near the silicide layer 20b. Accordingly, it is possible to prevent the dielectric breakdown of the joint portion 44 easily.

The operation of the protection circuit section and the effect of the semiconductor device described above can be said to be applied to a second embodiment described later.

{Setting of Zener Voltage} When no Zener diode is provided, when a high voltage pulse (surge) is applied to the drain region, the parasitic diode in the drain region undergoes avalanche breakdown. At this time, as indicated by E1 in FIG. 4, the drain voltage becomes VAB (avalanche breakdown voltage). Thereafter, when the parasitic bipolar transistor BPP is turned on, the drain voltage falls from VAB to VSB (snapback voltage) as shown by E2 in FIG. Such a phenomenon in which the drain voltage decreases is called snapback.

In the first embodiment, as shown by E3 in FIG. 4, the Zener voltage VZ of the Zener diode 8 (see FIG. 1) is lower than the avalanche breakdown voltage VAB of the parasitic diode 38 (see FIG. 1). It is set lower (VZ <VAB). By doing so, it is possible to surely cause the Zener diode 8 to undergo Zener breakdown before the parasitic diode 38 undergoes avalanche breakdown, and to turn on the bipolar transistor 2 instead of the parasitic bipolar transistor 6. .

More preferably, as shown by E4 in FIG. 4, the Zener voltage VZ is set lower than the snapback voltage VSB of the parasitic diode 38 (VZ <
VSB). By doing so, current can be stably discharged to the bipolar transistor 2 side. That is, by setting VZ <VSB, the drain voltage can be clamped to a voltage lower than the snapback voltage VSB when a high voltage pulse is applied. If the drain voltage can be clamped to a voltage lower than VSB in this manner, it is possible to reliably guarantee that the parasitic bipolar transistor 6 will not be turned on even if the parasitic diode 38 has avalanche breakdown for some reason. As a result, it is possible to effectively prevent the current discharge path from changing from the bipolar transistor 2 side to the parasitic bipolar transistor 6 side, and to reliably prevent the electrostatic breakdown of the MOS transistor 4.

The Zener voltage V of the parasitic diode 38
It is desirable that Z be equal to or higher than the absolute maximum rated voltage VAM of the semiconductor device as shown by E3 or E4 in FIG. That is, it is desirable that VAB> VZ ≧ VAM or VSB> VZ ≧ VAM. By doing so, high ESD
It is possible to prevent a leak current from flowing into the p-type region 15a via the Zener diode 8 during normal operation while ensuring the withstand voltage.

[0066] In the {control Zener voltage} first embodiment, the Zener voltage VZ of FIG 4, p ⁺ -type impurity regions 1
6 is controlled by the impurity concentration. Thereby, VA
The zener voltage VZ can be controlled so that B> VZ ≧ VAM or VSB> VZ ≧ VAM.

FIG. 5A shows an X-axis in a direction along the surface of the semiconductor device and a Y-axis in a direction orthogonal to the X-axis as shown in FIG.
The distribution example of the impurity concentration at Y = 0.1 μm when the axis is taken is shown. The junction of the Zener diode is shown in FIG.
Is formed at the boundary indicated by F1. The Zener voltage VZ is equal to the n ⁺ -type impurity concentration (F2
reference. For example, arsenic A for forming the n ⁺ -type impurity region 12b
s) and the p ⁺ -type impurity concentration at this boundary (see F3. For example, boron BF ₂ forming the p ⁺ -type impurity region 16)
Concentration).

FIG. 6 shows that the n ⁺ -type impurity concentration is 2.0 × 10
The relationship between the p ⁺ -type impurity concentration and the Zener voltage when the voltage is fixed at ²⁰ cm ⁻³ is shown. As shown in FIG. 6, for example, in order to set the Zener voltage VZ to 9 V, it is sufficient to set the p ⁺ -type impurity concentration to about 3.0 × 10 ¹⁷ cm ⁻³ . Similarly, in order to set the Zener voltage VZ at 7 V and 5 V, respectively, the p ⁺ -type impurity concentration is set to 6.0 × 10 ¹⁷ c
It can be seen that m ⁻³ , about 1.0 × 10 ¹⁸ cm ⁻³ suffices. That is, as the p ⁺ -type impurity concentration is increased,
The Zener voltage VZ decreases.

By controlling the p ⁺ -type impurity concentration in this manner, the zener voltage VZ can be easily adjusted to a desired value.

{Method for Manufacturing Device} A method for manufacturing the input / output circuit portion of the semiconductor device according to the first embodiment shown in FIG. 1 will be described with reference to FIGS. 1, 7 to 11.

First, as shown in FIG. 7, field oxide layers 18a and 18b having a predetermined pattern are formed in the p-type well 15 of the p-type silicon substrate 10 by using the LOCOS method.

Next, as shown in FIG. 8, a resist 40 is formed so as to cover the p-type silicon substrate 10. The resist 40 has an opening 40a for exposing the field oxide layer 18b and the p-type well 15 around the field oxide layer 18b. Using the resist 40 as a mask, the n-type
Type ions (eg, phosphorus) are selectively implanted, and n
Form a mold well 14. Note that the n-type well 14 may be formed first, and the field oxide layers 18a and 18b may be formed later.

Next, as shown in FIG. 9, the gate oxide layer 28 is
A polysilicon layer 24 (gate electrode) is formed.

Next, as shown in FIG. 10, n-type ions (for example, phosphorus) are selectively ion-implanted using the field oxide layers 18a and 18b and the polysilicon layer 24 (gate electrode) as a mask to form an LDD structure. To form an n-type low-concentration region. Then, sidewall oxide layers 30a and 30b are formed on the side surfaces of the polysilicon layer 24 (gate electrode) by using a known method. Then, using the field oxide layers 18a and 18b, the polysilicon layer 24 (gate electrode), and the sidewall oxide layers 30a and 30b as masks, n-type ions (for example, phosphorus) are selectively ion-implanted to form n ⁺ -type impurity regions. 12a, 12b, an n ⁺ type drain region 26a, and an n ⁺ type source region 26b are formed.

Next, as shown in FIG.
Is formed so that the p-type silicon substrate 10 is covered. Les
The dist 42 comprises the field oxide layers 18a and n⁺Type impurities
Has an opening 42a for exposing the boundary with the region 12b
You. Using the resist 42 as a mask, the p-type silicon substrate 1
Selectively implant p-type ions (eg, arsenic) to 0
Then p⁺A type impurity region 16 is formed. This gives p⁺
Type impurity region 16 and n ⁺Type impurity region 12b.
A Zener diode 8 is formed.

In this manufacturing method, the n ⁺ -type impurity region 12b and the p ⁺ -type impurity region 16, which are components of the Zener diode 8, are formed continuously. Thereby, a Zener diode 8 having a good junction can be formed. In other words, if another step is inserted between the step of forming n ⁺ -type impurity region 12b and the step of forming p ⁺ -type impurity region 16, the formation of the junction of Zener diode 8 may be adversely affected. The step of forming the p ⁺ -type impurity region 16 may be performed first, and the step of forming the n ⁺ -type impurity region 12b may be performed later.

Returning to the description of the manufacturing process. As shown in FIG. 1, silicide layers 20a to 20e are formed by using a known method.
To form Next, a silicon oxide layer 32 is formed using a CVD method so as to cover the p-type silicon substrate 10.

Then, the contact holes 34 are formed in the silicon oxide layer 32 by using photolithography and etching.
a and 34b are formed.

Then, an aluminum alloy layer is formed on the silicon oxide layer 32 and in the contact holes 34a and 34b by sputtering.

Finally, the aluminum alloy layer is patterned using photolithography and etching to form wiring layers 36a and 36b. Through the above steps, the input / output circuit portion of the semiconductor device is completed.

[Second Embodiment] FIG. 12 is a sectional view of a protection circuit portion of a semiconductor device according to a second embodiment of the present invention. The configuration other than the protection circuit unit is the same as the semiconductor device according to the first embodiment. Portions having functions substantially similar to those of the semiconductor device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. The main differences from the semiconductor device according to the first embodiment will be described, and description of other points will be omitted.

The semiconductor device according to the present invention prevents the electrostatic breakdown of the MOS transistor by flowing a current through the Zener diode 8. When a current flows through the Zener diode 8, heat is generated at the junction of the Zener diode 8. Incidentally, a contact portion between the wiring layer and the impurity region is weak to heat. Therefore, it is necessary to minimize the influence of heat on the contact portion.

Therefore, in the semiconductor device according to the second embodiment, the distance d between the contact hole 34b and the field oxide layer 18b is set to the minimum dimension according to the design rule. Thereby, the distance between the contact portion 46 and the Zener diode 8 can be increased. Therefore, the influence of the heat received from the Zener diode 8 on the contact portion 46 can be reduced, and the possibility of contact destruction can be reduced (or eliminated).

In the first and second embodiments,
Although the n ⁺ -type impurity region 12a is grounded, the present invention is not limited to this, and the n ⁺ -type impurity region 12a may be connected to the high potential side.

[Brief description of the drawings]

FIG. 1 is a sectional view of an input / output circuit unit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of an input / output circuit unit of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram for describing setting of a Zener voltage VZ.

FIGS. 5A and 5B are diagrams for explaining the impurity concentration distribution; FIG.

FIG. 6 is a diagram showing a relationship between a p-type impurity concentration and a Zener voltage.

FIG. 7 is a cross-sectional view of the silicon substrate showing a first step of the method of manufacturing the input / output circuit portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view of the silicon substrate showing a second step of the method for manufacturing the input / output circuit portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the silicon substrate showing a third step of the method for manufacturing the input / output circuit portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view of the silicon substrate showing a fourth step of the method for manufacturing the input / output circuit portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a sectional view of the silicon substrate showing a fifth step of the method for manufacturing the input / output circuit part of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a sectional view of a protection circuit section of a semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-202126.

[Explanation of symbols]

2 Bipolar transistor 4 MOS transistor 6 Parasitic bipolar transistor 8 Zener diode 12a, 12b n ⁺ type impurity region 14 n type well 15a, 15b p type region 16 p ⁺ type impurity region 18a, 18b Field oxide layer 20a-20e Silicide layer 26an ⁺ Type drain region 26 b n ⁺ type source region 34 b contact hole 36 b wiring layer 38 parasitic diode 44 junction 46 contact section 100 protection circuit section 200 transistor formation section 300 input / output circuit section 400 pad 600 semiconductor device

Claims (10)

[Claims] 1. A semiconductor device comprising: a semiconductor circuit portion formed on a semiconductor substrate; and a protection circuit portion formed on the semiconductor substrate for preventing surge destruction of the semiconductor circuit portion. The semiconductor circuit portion includes a field effect transistor, wherein the field effect transistor has a first conductivity type first region in which a channel region is formed, a second conductivity type first and second source / drain regions, The protection circuit section includes a bipolar transistor, a Zener diode, an element isolation insulating layer, and a connection region of a second conductivity type. The bipolar transistor has a second region of a second conductivity type, and a first conductivity type. A third region and a fourth region of a second conductivity type, wherein a wiring layer is electrically connected to the second region, and the Zener diode comprises a second region and a first conductivity type. A fifth region, wherein the element isolation insulating layer separates the second region and the first source / drain region; and the connection region connects the second region and the first source / drain region. A semiconductor device that is electrically connected. 2. The semiconductor device according to claim 1, wherein the semiconductor circuit portion and the protection circuit portion have a silicide layer. 3. The impurity according to claim 1, wherein the fifth region is formed in the third region, and a first conductivity type impurity concentration of the fifth region is a first conductivity type impurity of the third region. A semiconductor device higher than the concentration. 4. The contact circuit according to claim 1, wherein the protection circuit section includes an interlayer insulating layer, wherein the interlayer insulating layer has a contact hole formed on the second region. The semiconductor device, wherein the wiring layer is formed in the hole, and a distance between the contact hole and the element isolation insulating layer is a minimum dimension according to a design rule. 5. The Zener diode according to claim 1, wherein a Zener voltage of the Zener diode is lower than an avalanche breakdown voltage of a parasitic diode including the first source / drain region and the first region.
Semiconductor device. 6. The semiconductor according to claim 1, wherein a Zener voltage of the Zener diode is lower than a snapback voltage of a parasitic diode including the first source / drain region and the first region. apparatus. 7. The semiconductor device according to claim 1, wherein a Zener voltage of the Zener diode is equal to or higher than an absolute maximum rated voltage of the semiconductor device. 8. The semiconductor device according to claim 1, wherein a Zener voltage of the Zener diode is controlled by a first conductivity type impurity concentration of the fifth region. 9. The semiconductor device according to claim 1, wherein the semiconductor circuit section includes an input / output circuit section, an input circuit section, or an output circuit section. 10. The semiconductor device according to claim 1, wherein the semiconductor device includes an electrode portion, wherein the electrode portion is formed on the semiconductor substrate, and the electrode portion is electrically connected to an external wiring by bonding. A semiconductor device, wherein the semiconductor circuit section and the electrode section are electrically connected via the protection circuit section.