JP2000152647A - System interconnection inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system interconnection inverter which can accurately form waveform of an output current, even if changes occur in the input voltage to the inverter and in the system voltage. SOLUTION: The high-frequency switching of a switching element of an inverter 5 is controlled, so that the upper limit and lower limit of the command value are generated in the predetermined hysteresis width for the command value forming the waveform of an output current is with a command value upper limit generating means 13 an a command value lower limit generating means 14, and an output reactor current of an output reactor 6a detected with an output reactor current detecting means 12 is maintained between the command value upper limit and command value lower limit. When the output reactor current becomes lower than the command value lower limit, a switching element Q1 is turned on and the switching element Q2 is turned off. When such an output reactor current exceeds the command value upper limit, the switching element Q1 is turned off, while the Q2 is turned on. The output reactor current takes values between the command upper limit and lower limit, and the average current thereof becomes an output, current depending on the command value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grid-connected inverter for linking DC power from a solar cell, a fuel cell, or the like to a system and supplying it as AC power.

[0002]

2. Description of the Related Art A conventional system interconnection inverter will be described below with reference to the drawings. FIG. 11 is a block diagram showing a configuration of an example of a conventional system interconnection inverter.

Conventionally, a grid-connected inverter inputs DC power from a DC input power supply 1 and outputs 50 Hz or 60 Hz.
And supplies AC power to the system 2. The system interconnection inverter includes a boost converter 3 for boosting the input voltage Vin to a voltage higher than the system voltage VAC, an intermediate-stage capacitor 4 for removing a high-frequency component of the boosted voltage, and an inverter for shaping the output current into a sine wave. 5 and a filter 6 for removing high-frequency noise from the output of the inverter 5, and are connected to the system 2. In particular, the boost converter 3 includes a smoothing capacitor 3a for smoothing an input voltage, a DC reactor 3b for accumulating energy, a boost switching element 3c, and a boost diode 3d.
The inverter 5 has a full bridge configuration using four switching elements Q1 to Q4.

The operation of the above configuration will be described with reference to the drawings. FIG. 11 is a waveform chart showing the operation of the conventional example. 11A shows a reference wave and a triangular wave, FIG. 11B shows a gate signal of the switching element Q1,
(C) shows the gate signal of the switching element Q2, (d) shows the gate signal of the switching element Q3, and (e) shows the gate signal of the switching element Q4. The output current io of the grid-connected inverter is detected by the output current detection means 7 and compared with a sine waveform command value output from the current command means 8.
The difference is output as a reference wave by the error amplifier 9,
The comparator 10 compares the triangular wave with the triangular wave generated by the triangular wave generating means 11, and determines on / off of the switching elements Q1 and Q2 according to the magnitude of the triangular wave and the reference wave.
When system voltage VAC of system 2 is positive, switching element Q
When the switch 1 and the switching element Q4 are turned on, a current flows through the system 2. On the contrary, when the system voltage VAC is negative, the switching element Q2 and the switching element Q3 are turned on. As shown in FIG. 12, the switching elements Q1 and Q2 perform high-frequency switching, and the switching elements Q3 and Q4 switch at the commercial frequency. The same applies to the case where high frequency switching is simultaneously performed by a combination of the switching element Q1 and the switching element Q4 or a combination of the switching element Q2 and the switching element Q3.

Since the triangular wave operates at a constant frequency, for example, when the reference wave is a sine wave, the input voltage of the inverter 5 (here, the voltage of the intermediate-stage capacitor 4, ie, the intermediate-stage voltage VM) Is constant, the average value of the output voltage of the inverter 5 is controlled to be a sine wave. Therefore, the waveform of the output current is determined by selecting the reference wave. At this time, the operating frequency of the inverter 5 matches the operating frequency of the triangular wave. The output voltage of the inverter 5 has a high frequency component removed by a filter 6 including an output reactor 6a and a filter capacitor 6b.

[0006]

In such a conventional grid-connected inverter, the DC input voltage Vin is
When the AC value is lower than the maximum value, the boost converter 3 and the inverter 5 are required in order to realize the power factor 1 operation by linking to the grid 2, and a means for further improving the efficiency of the equipment. In the case where the capacity of the intermediate-stage capacitor 4 is reduced to several hundred μF or less to partially limit the operation of the boost converter 3, the ripple of the intermediate-stage voltage VM is large and unstable. Also, in a high-speed feedback control that adopts a PWM method in which the on / off time of the switching elements Q1 to Q4 is determined by comparing a triangular wave having a constant frequency with a reference wave, and the obtained output current io is detected and compared with a command value, It is necessary to compensate for the phase lag of the output current io due to the filter 6, and an accurate active filter is indispensable to realize the compensation. Moreover, the above-mentioned instability of the input voltage (here, the intermediate stage voltage VM) and various fluctuations of the system 2 (voltage, frequency, and phase)
Is added, it is difficult to perform stable control to generate an output current io with little distortion.

The present invention solves the above-mentioned problems, and uses a command value or a filter having a special waveform even when there is a fluctuation in the intermediate stage voltage VM, a ripple, a fluctuation in the system, or a phase delay due to the filter 6. It is an object of the present invention to provide a grid-connected inverter that can operate stably without being affected by the above-mentioned fluctuations and can accurately shape a waveform.

[0008]

According to a first aspect of the present invention, there is provided a DC reactor, a step-up switching element, and a step-up diode. Converter that outputs a DC intermediate-stage voltage by boosting the voltage, an intermediate-stage capacitor that removes high-frequency components in the intermediate-stage voltage and has a capacitance of several hundred μF or less, and four switching elements configured in a full bridge An inverter that outputs an AC current from the intermediate stage voltage by the switching of the filter, a filter that removes a high-frequency component of the AC current by an output reactor and a capacitor, and outputs the output current to an AC system, and the input voltage is The voltage is boosted by the boost converter only during a period lower than the absolute value of the system voltage, and In a system interconnection inverter that converts DC power input from an input power supply into AC power and outputs the AC power to the system, a command value upper limit and a command value lower limit with a predetermined hysteresis width with respect to a command value for shaping the output current. Wherein a high-frequency switching of the switching element of the inverter is controlled in a hysteresis manner such that an output reactor current flowing through the output reactor is kept within a hysteresis width between the command value upper limit and the command value lower limit. System inverter.

According to the present invention, the intermediate stage voltage operates stably with respect to the instability of the intermediate stage voltage and various fluctuations of the system voltage, frequency, phase and the like. It is possible to provide a grid-connected inverter capable of shaping the output current into a sine wave without using a special command value even when the power supply has a convex shape and a large amount of ripples.

According to a second aspect of the present invention, a second command value upper limit and a second command value lower limit are provided with a predetermined hysteresis width with respect to a command value for shaping the DC reactor current flowing through the DC reactor of the boost converter. In a period during which the boost converter boosts, the high frequency of the boost switching element of the boost converter is maintained so that the DC reactor current is maintained within a hysteresis width between the second command value upper limit and the second command value lower limit. Hysteresis control of the switching is performed, and during a period in which the boost converter is not boosted, the high-frequency switching of the switching element of the inverter is performed such that the output reactor current flowing through the output reactor is kept within a hysteresis width between a command value upper limit and a command value lower limit. 2. The grid-connected inverter according to claim 1, wherein the inverter is controlled in a hysteresis manner. A.

With this configuration, when the input voltage is lower than the absolute value of the system voltage, the boost converter can perform waveform shaping. Therefore, each switching element of the four-bridge full-bridge inverter can only perform switching operation at a low frequency. Accordingly, a reduction in the loss of the inverter is achieved, and it is possible to provide a system-linked inverter in which the entire device is reduced in size and weight due to improvement in efficiency and downsizing of the heat sink.

According to a third aspect of the present invention, in the first or second aspect, the hysteresis width is made variable in accordance with the DC input voltage, the effective value of the system voltage, and the output power. It is a related system interconnection inverter.

Thus, the operating frequency in the hysteresis operation can be kept within a predetermined range in accordance with the DC input voltage, the effective value of the system voltage, and the output power, and the change in the operating frequency is reduced. And
It is possible to provide a system interconnection inverter capable of optimally designing electrical components such as a switching element, a capacitor, a DC reactor, and an output reactor.

According to a fourth aspect of the present invention, there is provided a system interconnection according to any one of the first to third aspects, wherein the hysteresis width is made variable in a commercial cycle in accordance with the absolute value of the system voltage. It is an inverter.

Thus, the operating frequency in the hysteresis operation can be made substantially constant within one cycle of the system, and it is possible to provide a grid-connected inverter that can be designed to have an optimum operating frequency.

According to a fifth aspect of the present invention, an overcurrent upper limit corresponding to an overcurrent and an undercurrent lower limit corresponding to an undercurrent are provided outside a hysteresis width for determining an instruction value upper limit and a command value lower limit, The system interconnection inverter according to any one of claims 1 to 4, wherein an overcurrent exceeding the upper limit of the overcurrent and an undercurrent falling below the lower limit of the undercurrent are forcibly returned to the normal hysteresis control. .

Thus, even if an overcurrent or an undercurrent occurs during the hysteresis operation, it is possible to forcibly return to the normal hysteresis operation, and even if an erroneous operation such as deviating from the hysteresis width occurs, the safety is maintained. And a system interconnection inverter capable of continuing operation.

According to a sixth aspect of the present invention, there is provided an on-time detecting means for detecting the on-time of all the switching elements constituting the inverter and the boost converter. A system interconnection inverter according to any one of claims 1 to 5, wherein an upper limit is set for an operation frequency by not being turned off until exceeding.

As a result, since the operating frequency of the hysteresis operation does not exceed a predetermined value, a malfunction is less likely to occur, and a grid-connected inverter that operates stably can be provided.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention according to claim 1, the output reactor current detecting means is means for detecting a current flowing in a DC reactor provided in a filter, and is constituted by a current transformer or the like. This current directly indicates a change in the current output from the inverter. The command value upper limit generating means is a value obtained by adding a predetermined value to a command value for shaping the output current, that is, a command value upper limit generating means, and the command value lower limit generating means subtracts a predetermined value from the command value. This is a means for generating a value, that is, a command value lower limit. The point is that the output reactor current has a limit to repeatedly increase and decrease within a predetermined width with respect to the command value. The width between the command value upper limit and the command value lower limit is referred to as a hysteresis width, but is not limited to a constant width.

The upper limit comparator is means for comparing the value of the output reactor current with the upper limit of the command value. In the embodiment, when the output reactor current exceeds the upper limit of the command value, the upper limit comparator outputs a reset signal to the flip-flop. . The lower limit comparator is a means for comparing the value of the output reactor current with the lower limit of the command value. In the embodiment, when the output reactor current becomes smaller than the lower limit of the command value, the lower limit comparator outputs a set signal to the flip-flop. In short, it functions to monitor so that the output reactor current is between the upper limit of the command value and the lower limit of the command value. The flip-flop is a unit that is turned on or off in response to the set signal or the reset signal, and provides a gate signal that turns on or off a switching element in the inverter. By each of the above means, the inverter performs a hysteresis operation centering on the command value, that is, decreasing the current when the value exceeds the command value upper limit, and increasing the current when the value becomes smaller than the command value lower limit. And outputs a DC reactor current having a waveform according to. The other components are the same as in the conventional example.

In the present invention according to claim 2, the second command value upper limit generating means and the second command value lower limit generating means determine the second command value upper limit and the second command value lower limit provided for the command value, respectively. This is similar to the command value upper limit and the command value lower limit in the first embodiment. A second upper limit comparator,
The same applies to the second lower limit comparator and the second flip-flop. The DC reactor current detecting means is a means for detecting the current of the DC reactor in the boost converter, shows the change of the current output from the boost converter to the inverter as it is, and is equivalent to the control using the output reactor current in the first embodiment. Serve for purpose. In the embodiment, an example is shown in which the inverter does not shape the waveform during the boosting period. Therefore, the waveform of the command value for the DC reactor current has the same sine waveform as the waveform of the command value for the output reactor current. It is not something to be done.

According to the present invention, when the output reactor current increases from the lower limit of the command value to the upper limit of the command value, for example, when the switching element Q1 is turned on and the current flows, the output from the intermediate stage voltage VM is output. Voltage Vo
(= Absolute value of the system voltage VAC), the inductance L1 with respect to the potential difference (VM-Vo).
Through the output reactor, the current increases at the rise of (VM-Vo) / L1, that is, at the slope. Further, when the output reactor current decreases from the upper limit of the command value toward the lower limit of the command value, for example, when the switching element Q2 is turned on and the current flows, the intermediate stage voltage VM is cut off and the output voltage Vo goes from the output voltage Vo to zero potential. As a result, the current decreases at the fall of Vo / L1 via the inductance L1, that is, at the slope. Therefore, the transition time from the command value lower limit to the command value upper limit or from the command value upper limit to the command value lower limit is substantially a value obtained by dividing the hysteresis width by the above slope.

In this case, the reciprocal of the total time of the transition time from the lower limit of the command value to the upper limit of the command value at a certain time and the transition time from the upper limit of the command value to the lower limit of the command value at the time is defined as the operating frequency at that time. The operating frequency depends on the absolute value and effective value of the intermediate stage voltage VM, the system voltage VAC, the hysteresis width, and the like. Conversely, the operating frequency can be set to fall within a predetermined range by making the hysteresis width variable correspondingly.

In the present invention according to claim 4, the rising slope of the output reactor current from the lower limit of the command value to the upper limit of the command value is larger near zero of the system voltage VAC than near the peak. Therefore, by setting the hysteresis width near the peak to be smaller than the hysteresis width near zero, the operating frequency of the hysteresis operation can be made substantially constant. The same can be applied to the waveform shaping during the boosting operation of the boost converter.

In the invention according to claim 5, the overcurrent detecting means detects an overcurrent exceeding the upper limit of the command value of the output reactor current, and the undercurrent detecting means detects the undercurrent of the output reactor current below the lower limit of the command value. Is detected. The overcurrent upper limit comparator compares a predetermined overcurrent upper limit that is larger than the command value upper limit with the output reactor current, and outputs a reset signal to the flip-flop if it exceeds. The undercurrent lower limit comparator compares a predetermined undercurrent lower limit smaller than the command value lower limit with the output reactor current, and outputs a set signal to the flip-flop when the lower limit is lower than the command value lower limit. Therefore, it functions to forcibly return to the normal hysteresis operation. Note that the same can be applied to the case of shaping the waveform during the boosting operation of the boosting converter.

In the present invention according to claim 6, the on-time detecting means detects the on-time of the switching element of the inverter and, if less than a predetermined minimum on-time Ton min, continues the on-state of the switching element. In the embodiment, the set signal is output to the flip-flop until Ton min is reached. It functions to prevent the operating frequency of the hysteresis operation from becoming too high. This function is effective especially when the rising slope of the current is large near the zero voltage of the system voltage.

Hereinafter, embodiments of the present invention will be described.

[0029]

(Embodiment 1) Hereinafter, Embodiment 1 of a system interconnection inverter of the present invention will be described with reference to the drawings.
This embodiment relates to claim 1.

FIG. 1 is a block diagram showing the configuration of this embodiment. The same components as those in FIG. 11 are denoted by the same reference numerals, and detailed description will be omitted. This embodiment differs from the conventional example in that the filter 6 is provided with an output reactor current detecting means 12 for detecting the output current of the inverter 5 in place of the output current detecting means 7 and a command value for generating an upper limit of the command value. Upper limit generating means 13, command value lower limit generating means 14 for generating a lower limit of the command value, and output reactor current detecting means 1
Upper limit comparator 1 for comparing the output of 2 with the upper limit of the command value
5, a lower limit comparator 16 for comparing the output of the output reactor current detecting means 12 with the lower limit of the command value, and a flip-flop 17.

The operation of the above configuration will be described with reference to the drawings. FIG. 2 is a waveform chart showing the operation of the present embodiment. In FIG. 2, (a) is the upper limit of the command value (hereinafter, referred to as the upper limit)
Command value upper limit) and command value lower limit (hereinafter referred to as command value lower limit), (b) is the gate signal of switching element Q1, (c) is the gate signal of switching element Q2,
(D) shows the gate signal of the switching element Q3, and (e) shows the gate signal of the switching element Q4.

Since the intermediate stage voltage VM must be at least several tens of volts higher than the system voltage VAC in order to inject power into the system 2, for example, when the input voltage Vin is D
When the system voltage VAC is AC200V at C200V, the voltage is boosted for a period of 4 to 5 ms around the peak of the system voltage VAC,
The boosting is not performed during a period in which the absolute value of the other system voltage VAC is sufficiently smaller than the input voltage Vin. Furthermore, since the capacitance of the intermediate-stage capacitor 4 is reduced, it is not smoothed in terms of low frequency.
Can be maintained within about several tens of volts. As a result, the intermediate stage voltage VM has a partially convex waveform.

In the inverter 5 to which the intermediate stage voltage VM is input, the switching element Q4 is turned on,
During the half-wave period of the commercial frequency when 3 is off, the output reactor current detecting means 1 controls the current of the output reactor 6a constituting the filter 6 to be substantially sinusoidal.
2, the output reactor current is detected. If the output reactor current becomes smaller than the lower limit of the command value, the output of the flip-flop 17 is set, and the switching element Q1 is turned on and the switching element Q2 is turned off. As a result, the output reactor current increases. Conversely, when the output reactor current is larger than the command value upper limit, the output of the flip-flop 17 is reset, the switching element Q1 is turned off and the switching element Q2 is turned on, and the output reactor current decreases.

By the above operation, the output reactor current transitions between the command value upper limit and the command value lower limit. Here, when the command value is a sine wave, the average value of the output reactor current is a sine wave. The high-frequency component of the output reactor current can be removed by the filter capacitor 6b.

As described above, according to the present embodiment, in a system interconnection inverter in which the intermediate stage capacitor 4 is as small as several hundred μF or less, high-frequency switching in the boost converter 3 is partially performed within one cycle of the system 2. Intermediate stage voltage VM
Can be provided with a system interconnection inverter capable of shaping the output current io into a substantially sinusoidal waveform even when is partially convex.

In this embodiment, the inverter 5 performs the operation of switching the output of the half-bridge inverter that performs high-frequency switching at the commercial frequency. However, the same effect can be obtained even when all the four switching elements Q1 to Q4 perform high-frequency switching. Needless to say, it can be obtained.

(Embodiment 2) Hereinafter, Embodiment 2 of a system interconnection inverter of the present invention will be described with reference to the drawings. This embodiment relates to claim 2.

FIG. 3 is a block diagram showing the configuration of this embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. This embodiment is different from the first embodiment in that all of the waveform shaping of the output current io is performed by the inverter 5.
When the boost converter 3 performs a boost operation in a period in which the input voltage Vin is lower than the absolute value of the system voltage VAC, the waveform is shaped by using hysteresis control for the high-frequency switching.

In FIG. 3, reference numeral 18 denotes a system voltage V of the system 2.
System voltage detecting means for detecting AC; 19, input voltage detecting means for detecting the input voltage Vin of the input power supply 1; 20, input / output voltage comparator for comparing the absolute value of the system voltage VAC with the input voltage Vin; DC reactor current detecting means for detecting DC reactor current iLd of DC reactor 3b in boost converter 3, 22 is a second command value upper limit generating means for generating a second command value upper limit as an upper limit of the command value, and 23 is a lower limit of the command value A second command value lower limit generating means for generating a second command value lower limit, 24 a second upper limit comparator for comparing the second command value upper limit with the DC reactor current iLd, 25 a second command value lower limit and the DC The second lower limit comparator 26 for comparing the reactor current iLd with the second lower limit comparator 25 is set or reset based on the comparison result of the second upper limit comparator 24 and the comparison result of the second lower limit comparator 25. Flip-flops 27 are switching switching means for switching the switching of the switching elements Q1 to Q4 by the flip-flop 17 and the switching of the boosting switching element 3c by the second flip-flop 26 according to the comparison result of the input / output voltage comparator 20.

The operation in the above configuration will be described with reference to the drawings. FIG. 4 is a waveform chart showing the operation of this embodiment. In FIG. 4, (a) is a command value, a command value upper limit,
(B) is the gate signal of the switching element Q1 in the inverter 5, (c) is the gate signal of the switching element Q2, and (d) is the switching element Q3.
(E) shows the gate signal of the switching element Q4, (f) shows the gate signal of the transistor QF in the boosting switching element 3c, and (g) shows the input voltage Vin and the absolute value of the system voltage VAC.

The system interconnection inverter controls the output reactor current to a sine wave using the command upper limit and the command lower limit during a period when the absolute value of the system voltage VAC is lower than the input voltage Vin. Further, a DC reactor current detecting means 21 is provided, and the detected DC reactor current is
4 and the second lower limit comparator 25, and compares them with the second command value upper limit and the second command value lower limit, respectively, to generate a gate signal for driving the boosting switching element by the second flip-flop 26. . Also, the input / output voltage comparator 20
Compares the system voltage VAC from the system voltage detecting means 18 with the input voltage Vin from the input voltage detecting means 19, and when the input voltage Vin is generally higher than the absolute value of the system voltage VAC,
The inverter 5 is selected by the switching switching means 27, and the hysteresis control is performed by the upper limit of the command value and the lower limit of the command value.
When it is lower than in, the boost converter 3 is selected and the hysteresis control based on the second command value upper limit and the second command value lower limit is performed.

When the boost converter 3 performs the hysteresis control, the DC reactor current detecting means 21 detects the DC reactor current, and when the DC reactor current becomes smaller than the command value lower limit of the second command value lower limit generating means 23. Sets the output of the second flip-flop 26, and sets the transistor QF of the boosting switching element 3c.
Is turned on. As a result, the DC reactor current increases. On the other hand, if the DC reactor current is larger than the second command value upper limit of the second command value upper limit generating means 22,
The output of the flip-flop 26 is reset, the transistor QF is turned off, and the DC reactor current decreases.
At this time, the output current decreases. With these actions,
The DC reactor current during the period in which boost converter 3 performs the boost operation is maintained between the second command value upper limit and the second command value lower limit, and is output to inverter 5.

With the above operation, the command value upper limit, the command value lower limit, the second command value upper limit, and the second command value lower limit are appropriately set, whereby the average value of the output current io is shaped into a sine wave. . The high-frequency components accompanying the transition of the DC reactor current and the output reactor current are removed by the intermediate stage capacitor 4 and the filter 6.

As described above, according to this embodiment, by controlling the DC reactor current of the boost converter 3, when the input voltage Vin is substantially lower than the absolute value of the system voltage VAC, the waveform can be shaped by the boost converter 3. In this case, since the inverter 5 performs only the switching of the low frequency, the loss can be reduced, the efficiency can be improved, and the whole device can be reduced in size and weight with the downsizing of the heat sink.

(Embodiment 3) Hereinafter, Embodiment 3 of a system interconnection inverter of the present invention will be described with reference to the drawings. This embodiment relates to claim 3. Note that the configuration of the present embodiment is the same as FIG. 1 when shown in a block diagram, and the drawing is omitted.

The operation in the above configuration will be described.
FIG. 5 is a waveform chart showing the operation of this embodiment. When a certain output current is to be obtained, the voltage hysteresis width between the command value upper limit and the command value lower limit for the command value of the output reactor current is VH1, the intermediate stage voltage is VM, the output voltage is Vo, and the inductance of the output reactor is L1. Then, the output reactor current iL1 increases at a gradient of (VM-Vo) / L1. If the intermediate stage voltage VM or Vo changes, the on-time of the boosting switching element 3c is kept constant while the output reactor current iL1 is kept constant by changing the hysteresis width to newly set VH2. Becomes possible. For example, by increasing the hysteresis width when the intermediate stage voltage VM increases, and decreasing the hysteresis width when the intermediate stage voltage VM decreases, the hysteresis width is changed in accordance with the change in the slope, and the on-time is kept constant. Can be kept. The off time is Vo
Since the current decreases with the slope of / L1, the off time can be made substantially constant.

As described above, according to this embodiment, the range of the operating frequency can be limited by adjusting the hysteresis width with respect to changes in the input voltage Vin, the system voltage VAC, and the output power. It is possible to provide a grid-connected inverter capable of shaping the output current io into a sine wave while reducing the possibility of occurrence of a malfunction.

(Embodiment 4) Hereinafter, Embodiment 4 of a system interconnection inverter of the present invention will be described with reference to the drawings. This embodiment relates to claim 4. In addition, if the configuration of the present embodiment is shown in a block diagram, it is the same as FIG. 3, and the drawing is omitted.

The operation in the above configuration will be described.
FIG. 6 is a waveform chart showing the operation of this embodiment. In FIG. 6, (a) is a command value, a command value upper limit, and a command value lower limit,
(B) shows details near the peak of the system voltage VAC,
(C) shows details of the system voltage VAC near zero.

When the hysteresis width is constant, the potential difference between the intermediate stage voltage VM and the output voltage Vo becomes large near the absolute value of the system voltage VAC, and the slope of the output reactor current in the increasing direction becomes large. The operating frequency is higher than near the VAC peak. Therefore, FIG.
As shown in (a), by increasing the hysteresis width near the peak and increasing it near zero, the operating frequency can be kept constant within one cycle of the sine wave.

As described above, according to the present embodiment, the operating frequency becomes substantially constant by varying the hysteresis width of the output reactor current in accordance with the absolute value of the system voltage VAC. It is possible to provide a grid-connected inverter that can be designed and that also achieves low noise.

In this embodiment, the case where the waveform is formed by the output reactor current of the inverter 5 has been described.
It goes without saying that the same applies to the case where the waveform is formed by the DC reactor current of boost converter 3.

(Embodiment 5) Hereinafter, a fifth embodiment of a system interconnection inverter according to the present invention will be described with reference to the drawings. This embodiment relates to claim 5.

FIG. 7 is a block diagram showing the configuration of this embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. The present embodiment is different from the first embodiment in that the output reactor current
And an undercurrent detection means 29, and an overcurrent upper limit comparator 30 and an undercurrent lower limit comparator 31 for comparing with an output reactor current are provided. The overcurrent detecting means 28 detects an overcurrent of the output reactor current exceeding the upper limit of the command value, and the undercurrent detecting means 29 detects an undercurrent of the output reactor current below the lower limit of the command value.

The operation in the above configuration will be described.
FIG. 8 is a waveform chart showing the operation of this embodiment. In FIG. 8, (a) shows a command value upper limit, a command value lower limit, a command value, an overcurrent upper limit, and an undercurrent lower limit, and (b) shows details near a peak.

Normally, the output reactor current transitions within the hysteresis width VH1, but when it reaches the upper limit of the command value and the switching element Q1 must be turned off, it keeps on for some reason. In this case, in this embodiment, the overcurrent detecting means 28 detects the overcurrent of the output reactor current,
Compares the output reactor current with the overcurrent upper limit having a width of VHL provided outside the hysteresis width, outputs a reset signal to the flip-flop 17, and forcibly turns off the switching element Q1. Conversely, when the output reactor current deviates from the hysteresis width of the command value lower limit and continues to be in the off state, the undercurrent detection means 29 and the undercurrent lower limit comparator 31 determine that the abnormality is below the lower limit of the undercurrent, and the forced operation is performed. The switching element Q1 is turned on.

As described above, according to the present embodiment, it is possible to provide a system interconnection inverter that can safely continue operation even if a malfunction occurs in the hysteresis control of the output reactor current.

Although the operation of the switching element Q1 of the inverter 5 has been described in the present embodiment, the same applies to the case where the waveform is shaped by the boost converter 3.

(Embodiment 6) Hereinafter, Embodiment 6 of a system interconnection inverter of the present invention will be described with reference to the drawings. This embodiment relates to claim 6.

FIG. 9 is a block diagram showing the configuration of this embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. This embodiment is different from the first embodiment in that the switching element Q1 or Q3
Is provided with on-time detecting means 32 for detecting the on-time.

The operation in the above configuration will be described.
FIG. 10 is a waveform chart showing the operation of this embodiment. 10A shows the command value upper limit, the command value lower limit, and the command value, and FIG. 10B shows details near the peak. In FIG. 10, normally, the output reactor current has a hysteresis width V
H1 transitions, the input voltage Vin, the intermediate stage voltage VM
Even if the on-time corresponding to the hysteresis width is set in accordance with the conditions such as the system voltage VAC and the output power, the on-time detected by the on-time detecting means 32 is the predetermined minimum on-time Ton min , The set signal is output to the flip-flop 17 and
Until the time exceeds Ton min, the on state of the switching element Q1 is continued. This prevents the operating frequency of the hysteresis operation from becoming extremely high.

As described above, according to the present embodiment, the operation frequency does not exceed a predetermined value when the hysteresis control of the output reactor current is performed, so that a malfunction is less likely to occur and a system that can safely operate. An interconnection inverter can be provided.

[0063]

According to the first aspect of the present invention, there is provided a DC reactor, a boosting switching element, and a boosting diode, and boosts an input voltage from a DC input power supply by high-frequency switching of the boosting switching element. A boost converter that outputs a DC intermediate-stage voltage, an intermediate-stage capacitor that removes high-frequency components in the intermediate-stage voltage, has a capacitance of several hundred μF or less, and performs switching of four switching elements configured in a full bridge. An inverter that outputs an AC current from the intermediate stage voltage; and a filter that removes a high-frequency component of the AC current by an output reactor and a capacitor and outputs the AC current as an output current to an AC system. Boosted by the boost converter only in a period lower than the value,
In a system interconnection inverter that converts DC power input from the input power supply to AC power and outputs the AC power to the system, a command value upper limit and a command value lower limit with a predetermined hysteresis width with respect to a command value for shaping the output current. And a system wherein the high-frequency switching of the switching element of the inverter is subjected to hysteresis control so as to keep the output reactor current flowing through the output reactor within a hysteresis width between the command value upper limit and the command value lower limit. By using an interconnected inverter, it operates stably with respect to the instability of the intermediate stage voltage and various fluctuations of the system voltage, frequency, phase, etc. Therefore, the capacitance of the intermediate stage capacitor is reduced to several hundred μF or less. In the system interconnection inverter with the above configuration, even if the intermediate stage voltage is partially convex,
By using a sine wave as the command value without using a special waveform for the command value, the output current can be made substantially a sine wave.

According to a second aspect of the present invention, a second command value upper limit and a second command value lower limit are provided with a predetermined hysteresis width with respect to a command value for shaping the DC reactor current flowing through the DC reactor of the boost converter. In a period during which the boost converter boosts, the high frequency of the boost switching element of the boost converter is maintained so that the DC reactor current is maintained within a hysteresis width between the second command value upper limit and the second command value lower limit. Hysteresis control of the switching is performed, and during a period in which the boost converter is not boosted, the high-frequency switching of the switching element of the inverter is performed such that the output reactor current flowing through the output reactor is kept within a hysteresis width between a command value upper limit and a command value lower limit. 2. The grid-connected inverter according to claim 1, wherein the inverter is controlled in a hysteresis manner. By can reduce the loss in the inverter, therefore, enables miniaturization of the heat sink, it is possible to provide a system interconnection inverter small and light.

According to a third aspect of the present invention, in the first or second aspect, the hysteresis width is made variable in accordance with the DC input voltage, the effective value of the system voltage, and the output power. By using the related grid-connected inverter, the operating frequency in the hysteresis operation can be within a predetermined range corresponding to the DC input voltage, the effective value of the system voltage, and the output power, and the change in the operating frequency is reduced. In addition, it is possible to provide a system interconnection inverter capable of simplifying a filter and optimally designing an electric component such as a switching element, a capacitor, a DC reactor, and an output reactor.

According to a fourth aspect of the present invention, there is provided a system interconnection according to any one of the first to third aspects, wherein the hysteresis width is variable in a commercial cycle in accordance with the absolute value of the system voltage. By using the inverter, the operation frequency in the hysteresis operation can be made substantially constant within one cycle of the system, and a system interconnection inverter that can be designed to have an optimum operation frequency can be provided.

According to a fifth aspect of the present invention, an overcurrent upper limit corresponding to an overcurrent and an undercurrent lower limit corresponding to an undercurrent are provided outside a hysteresis width for determining an instruction value upper limit and a command value lower limit, The system interconnection inverter according to any one of claims 1 to 4, wherein an overcurrent exceeding the overcurrent upper limit and an undercurrent falling below the undercurrent lower limit are forcibly returned to the normal hysteresis control. Therefore, even if an overcurrent or undercurrent occurs during the hysteresis operation, it is possible to forcibly return to the normal hysteresis operation, and even if a malfunction such as deviating from the hysteresis width occurs, the operation can be safely performed after that. A continuous grid-connected inverter can be provided.

According to a sixth aspect of the present invention, there is provided an on-time detecting means for detecting the on-time of all the switching elements constituting the inverter and the boost converter. The operating frequency of the hysteresis operation does not exceed a predetermined value by employing the system interconnection inverter according to any one of claims 1 to 5, wherein the operating frequency is not turned off until exceeding the upper limit. Therefore, a malfunction is less likely to occur, and a grid-connected inverter that operates stably can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a system interconnection inverter according to a first embodiment of the present invention;

FIG. 2 is a waveform chart showing the operation of the embodiment.

FIG. 3 is a block diagram showing a configuration of a system interconnection inverter according to a second embodiment of the present invention;

FIG. 4 is a waveform chart showing the operation of the embodiment.

FIG. 5 is a waveform chart showing the operation of the system interconnection inverter according to the third embodiment of the present invention.

FIG. 6 is a waveform chart showing an operation of a system interconnection inverter according to a fourth embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a system interconnection inverter according to a fifth embodiment of the present invention;

FIG. 8 is a waveform chart showing the operation of the embodiment.

FIG. 9 is a block diagram showing a configuration of a system interconnection inverter according to a sixth embodiment of the present invention;

FIG. 10 is a waveform chart showing the operation of the embodiment.

FIG. 11 is a block diagram showing a configuration of a conventional grid-connected inverter.

FIG. 12 is a waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 input power supply 2 system 3 boost converter 3a smoothing capacitor 3b DC reactor 3c boost switching element 3d boost diode 4 intermediate stage capacitor 5 inverter 6 filter 6a output reactor 6b filter capacitor 7 output current detecting means 8 current command means 9 error amplifier 10 Comparator 11 Triangular wave generating means 12 Output reactor current detecting means 13 Command upper limit generating means 14 Command lower limit generating means 15 Upper limit comparator 16 Lower limit comparator 17 Flip-flop 18 System voltage detecting means 19 Input voltage detecting means 20 Input / output voltage comparison Unit 21 DC reactor current detecting means 22 Second command value upper limit generating means 23 Second command value lower limit generating means 24 Second upper limit comparator 25 Second lower limit comparator 26 Second flip-flop 27 Switching switching means 28 Overvoltage Current detecting means 29 Undercurrent detecting means 30 Overcurrent upper limit comparator 31 Undercurrent lower limit comparator 32 On time detecting means Vin Input voltage VM Intermediate stage voltage Vo Output voltage VAC System voltage VH1, VH2 Hysteresis width io Output current iL1 Output reactor current iLd DC reactor current Q1, Q2, Q3, Q4 Switching element QF transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takaaki Okude 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Kiyoshi Izaki 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Kenji Ito 1006, Kadoma Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. 1006, Kadoma, Kadoma, Fumonma-shi Matsushita Electric Industrial Co., Ltd. (72) Inventor Taketoshi Sato 1006, Kadoma, Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F term (reference) 5G066 HA30 HB05 5H007 AA02 AA08 BB07 CA01 CB02 CB04 CB05 CC0 3 CC12 DA03 DA05 DA06 DC02 DC04 DC05 FA03 FA04 FA13

Claims (6)

[Claims] 1. A booster comprising a DC reactor, a boosting switching element, and a boosting diode, boosting an input voltage from a DC input power supply by high-frequency switching of the boosting switching element and outputting a DC intermediate stage voltage. A converter, an intermediate-stage capacitor having a capacity of several hundred μF or less for removing high-frequency components in the intermediate-stage voltage, and an alternating current output from the intermediate-stage voltage by switching four switching elements configured in a full bridge. An inverter, and a filter that removes a high-frequency component of the AC current with an output reactor and a capacitor and outputs the AC current as an output current to an AC system, and the boost converter only during a period in which the input voltage is lower than the absolute value of the system voltage. DC power input from the input power supply to AC power In the system interconnection inverter that outputs the output current to the system, a command value upper limit and a command value lower limit are provided with a predetermined hysteresis width for a command value for shaping the output current, and an output reactor current flowing through the output reactor is provided. ... A system interconnection inverter in which high-frequency switching of a switching element of the inverter is controlled in a hysteresis manner so as to maintain a hysteresis width between the command value upper limit and the command value lower limit. 2. A second command value upper limit and a second command value lower limit with a predetermined hysteresis width for a command value for shaping a DC reactor current flowing through a DC reactor of a boost converter, and the boost converter boosts the voltage. In the period, the DC reactor current is increased by the second command value upper limit and the second command value upper limit.
Hysteresis control is performed on the high-frequency switching of the boosting switching element of the boost converter so as to maintain the hysteresis width between the command value lower limit and the output reactor current flowing through the output reactor during the period in which the boost converter does not boost. 2. The system interconnection inverter according to claim 1, wherein the high-frequency switching of the switching element of the inverter is hysteresis controlled so as to keep the hysteresis width between the upper limit of the value and the lower limit of the command value. 3. The system interconnection inverter according to claim 1, wherein the hysteresis width is made variable in accordance with the DC input voltage, the effective value of the system voltage, and the output power. 4. The system interconnection inverter according to claim 1, wherein the hysteresis width is variable in a commercial cycle in accordance with the absolute value of the system voltage. 5. An overcurrent upper limit corresponding to an overcurrent and an undercurrent lower limit corresponding to an undercurrent are provided outside a hysteresis width for determining an instruction value upper limit and a command value lower limit. 5. The system interconnection inverter according to claim 1, wherein a normal hysteresis control is forcibly returned to a current and an undercurrent lower than the undercurrent lower limit. 6. 6. An on-time detecting means for detecting on-time of all switching elements constituting an inverter and a boost converter, wherein the on-time detecting means does not turn off until the on-time of a switching element which is flowing a current exceeds a predetermined value. The system interconnection inverter according to any one of claims 1 to 5, wherein an operating frequency is provided with an upper limit by: