JP2000150862A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a Controlled-NOT circuit to a general purpose Si-LSI by applying a voltage to at least one gate electrode for changing charge distribution in at least two fine structures. SOLUTION: The manufacturing method of an embodiment is described. First, a device region is formed on a p-Si substrate 7. Then, gate oxidation is made, and a thermal oxide film 8 for forming quantum dot structure is subjected to patterning. Ion implantation is performed while resist is allowed to remain, and the regions of a source 9 and a drain 10 are formed. Then, after poly Si is deposited, a quantum dot structure of 0.1 μm or less that becomes a target bit 1 and a control bit 2, a gate electrode 3 of the target bit, and a gate electrode 4 for the control bit are subjected to patterning. In this case, to further reduce the size of a quantum size, the quantum dot structure is manufactured, thermal oxidation is made again, quantum dot surface is oxidized, and the transmission part can be further reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device that performs a logical operation.

[0002]

2. Description of the Related Art Quantities that directly use quantum mechanical wave functions
The child computer is D. Deutsch (Proc.
R. Soc. London, Ser A 40
0, p97 (1985))
I have. For example, according to the conventional factorization algorithm,
Is approximately exponential with increasing number of inputs
Is known to increase, W.
Shor (1994 Proc. 35th An)
n. Symp. Foundation of Co
mputer Science (IEEE Compu
ter Society, Los Alamos, p
124) is a polynomial step of the number of inputs (eg, c ₁N + c
₂N²+ C₃N³. . . Times (c₁, C₂, C₃. . . Is
Algorithm that can be factored by a constant
By showing by computer, quantum computer
The usefulness of data has become widely recognized. other
On the other hand, quantum computers are expected to be applied to cryptography
I have. This is the wave function in quantum computers
(1) Deciphering by considering things as individual signals
Generating an impossible signal, (2) there is an eavesdropper
Necessary for cryptography to recognize its existence when
It is known to fulfill important properties. this
Regarding (2), as soon as the eavesdropper contacts the signal, the quantum power
‘Observation’ is performed and the wave function changes
Is the essence of which is impossible to copy completely
Is used to the maximum (no-cloning logic
Theory). This is a classic encryption using a classic 0 or 1 signal
It was thought impossible.

The logical operation in this quantum computer is realized as a change in a wave function. First, when representing bits, particularly in a two-level system, two basis functions | 0>
And | 1> and an arbitrary number, a and b, φ = a | 0> + b
| 0>. For example, a state representing an integer N first represents N in binary:

(Equation 1) It is described as follows. The logical operation in the quantum computer is to apply a unitary transformation (unitary matrix), which is a change of the system, to this wave state. The unitary matrix may take various forms depending on the type of calculation. Among them, a control-NOT circuit is considered to be particularly basic and important (for example, A.I.
Barenco et. al: Phys. Re
v. Lett. Vol. 74, p4083 (1
995)). It consists of two bits (two-level system), when that one control bit longer one of the two bits referred to as the target bit, Controlled-NOT operation C ₁₂ relates to the control bit and the target bit It is put as follows:

(Equation 2) I mean

(Equation 3) Expressed as a matrix

(Equation 4) become that way. The controlled-NOT circuit is characterized by (1) what is called a measurement gate, which enables nondestructive measurement, and (2) which enables swapping of the state of two bits. Plays an important role in quantum cryptography (CH Bennett eta)
l. : Phys. Rev .. Lett. Vol.
29 p 1895 (1993)).

As a system for realizing this quantum computer, an ion trap system (JI Cirac et.
al. (Phys. Rev. Lett. Vol.
74, p4091 (1995)) and a proposal using NMR (NA Gershenfeld et a).
l. Science Vol. 275 p350
(1997)). J. I. Cirac
et al. (Phys. Rev. Lett. Vo
l. 74, p4091 (1995), a controlled-N using a cold ion trap.
OT is described in Monroe et al. (Phys. Re
v. Lett. Vol. 50, p 4714 (199
5)) have conducted experimental verification. FIG. 8 shows a system for realizing a controlled-NOT using the dipole-dipole interaction between two adjacent quantum dots (A. Barencoet. Al: Ph).
ys. Rev .. Lett. Vol. 74, p4
083 (1995)). FIG. 8A shows the energy levels of two quantum dots in the presence of an external electric field when there is an interaction between the quantum dots (left) and when there is no interaction between them (right). ) Shows a resonance spectrum, and a broken line shows a controlled-NOT operation when the quantum dot 1 is a control bit and the quantum dot 2 is a target bit. The quantum dot 2 makes a transition between | 0> and | 1> only when the first quantum dot 1 is in the state | 1> when a pulse wave of π having a frequency ω ₂ + / ω is applied. I understand. Here, / ω is ω bar.

As described above, some controlled-
Although a system for realizing NOT operation has been proposed, for example, it is difficult to form a microchip in an element using light such as an ion trap, and there are essential problems such as difficulty in coupling with a conventional LSI. Even in the case of a cryptographic circuit, it has been necessary to make it into an electronic device in order to incorporate it as a chip in an ordinary personal computer. Also, Qua
ntum Cellular Automaton (Q
CA), a proposal (CSL) in which four or five sets of quantum dots are arranged as cells of a basic unit in a large number in the same plane, and an output signal is taken for an input signal.
ent et al: Nanotech. Vol.
4, p49 (1993), Appl. Phys
s. Lett. Vol. 62, p714 (19
93)), however, in this proposal, the interaction between cells, which is the principle of circuit operation, is a classical mechanical Coulomb interaction, and the quantum mechanical operation required by a quantum computer is impossible. there were. Also, in this proposal, the number of electrons in the cell is limited to a certain number in the cell, and it is essential that the cell is confined, and operation becomes impossible if other than a certain number of electrons are injected or removed. ,
The problem was that it was extremely difficult to create.

[0006]

SUMMARY OF THE INVENTION The present invention has been devised in view of the above, and is a semiconductor device capable of connecting a controlled-NOT circuit, which is the most basic logic circuit in a quantum computer, to a general-purpose Si-LSI. It is possible to realize in.

[0007]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention comprises two or more microstructures made of a conductive material having a size of 0.1 μm or less, and an electrical device having a junction capacitance of 0.1 μF or less. And at least two gate electrodes connected to the gate electrode, and applying a specific voltage to the one or more gate electrodes changes a charge distribution in at least two of the microstructures. . Further, the semiconductor element of the present invention forms two or more fine structures of 0.1 μm or less made of a conductor and is electrically connected to the fine structures so that the junction capacitance is 0.1 μF or less. A gate electrode;
It has a second gate electrode electrically connected to two or more of the microstructures not connected to the first gate electrode so that a junction capacitance is 0.1 μF or less. Further, the semiconductor element of the present invention has four or more microstructures made of a conductor formed on a substrate via an insulating film, is electrically connected to two or more of the microstructures, and has a junction capacitance of 0.1 μF. It is characterized by having one or more of the following first gate electrodes, a second gate electrode formed on the microstructure and an insulator over the first gate electrode. The semiconductor element of the present invention is characterized in that the microstructure, the first gate electrode, and the second gate electrode are formed over a semiconductor substrate with an insulating film interposed therebetween, and have a source electrode and a drain electrode. I do.

Further, the semiconductor device of the present invention has the fine structure,
The first gate electrode and the second gate electrode are formed on a semiconductor substrate via an insulating film, and have a source electrode and a drain electrode. Further, the semiconductor device of the present invention comprises two or more fine structures of 0.1 μm or less made of a conductor, and a charge supply layer electrically connected to the fine structures so that the connection capacitance is 0.1 μF or less. And one or more gate electrodes formed on the microstructure via an insulator, and applying a specific voltage to the gate electrode changes charge distribution in at least two of the microstructures. It is characterized by doing. That is, the present invention uses a plurality of gate electrodes and a plurality of microstructures (quantum dots) of 1 micron or less connected to each gate electrode as basic components.
FIG. 2 shows the principle of operation of claim 1 of the present invention in which four quantum dots (a target bit 1 composed of two quantum dots and a control bit 2 composed of two quantum dots) and two gate electrodes 3 are used.
4 is schematically shown. The gate electrode and the quantum dot may be made of different materials. Here, one of the four quantum dots connected to the gate electrode is made smaller. As a result, in the band diagram of the quantum dot, as shown in the figure, the energy level between the quantum dots from the gate electrode is large. When a voltage is applied to the gate electrode, electrons are injected into the quantum dot from the gate electrode. However, since the quantum dot is sufficiently small, it is allowed to exist only at discrete energy levels in the quantum dot. In addition, due to the so-called Coulomb blockade effect between electrons, a large voltage is required for two or more electrons to enter the quantum dot system, effectively limiting the number of electrons entering the quantum dot system to one Is done.

A voltage is applied to the gate electrode to inject electrons. When the injected electrons are present in the quantum dots from the gate electrode, the state | 1> is entered, and the electrons enter the quantum dots far from the gate electrode. The case is set to the | 0> state (FIG. 2B). Next, the voltage V is applied to the gate electrode 4 for the control bit.
₂ (c) and (d) show band diagrams of the target bit 1 connected to the target bit gate electrode 3 when electrons are injected into the control bit ₂ by adding ₂ to FIG. When the position of the electron injected into the control bit 2 is (c), the bottom of the band in the quantum dot representing the | 0> state in the target bit 1 rises due to the Coulomb repulsion of the electron, and conversely, (d) In this case, the bottom of the band in the quantum dot representing the | 1> state of target bit 1 rises. Here, the gate electrode 3 for the target bit
To inject electrons into the target bit 1. The voltage V ₁ applied to the target bit gate electrode 3 is changed to the energy in the two quantum dots in the target bit 1 when the electrons of the control bit 2 are in the state of | 1>, that is, in the state of FIG. The voltages are such that the levels match (FIG. 2
(E)). In the above system, Controlled-NOT in whether to use voltages _{V 1} to the first gate electrode
It is shown that the operation is possible as follows.

(1) When the control bit is | 0> The electrons in both bits are in (a) or (c) of FIG. In this case, since high energy level outside the quantum dot when viewed from the gate electrode of the target bit 1 from the beginning as shown in FIG. 3 also applying a voltage V ₁ (b), the two quantum dots within the target bit 1 The energy levels do not match. Therefore, the electrons in the target bit 1 do not move, and FIG.
In addition, (c) becomes (d) (| 0> | 0> → | 0> | 0
>, | 1> | 0> → | 1> | 0>). (2) When the control bit is | 1> The electron distribution in both bits is as shown in FIGS. Here, when applying the voltages V ₁ energy level of the quantum dots within the target bits as shown in FIG. 2 (e) match, electrons 3 from (e) (f), from (g) (h ). At this time, | 0> | 1> → | 1> | 1>, | 1
> | 1> → | 0> | 1> has been performed.
As described above, the controlled-NOT operation is realized in this system. Note that the first gate electrode and the second gate electrode can alternate roles. FIG. 5 schematically shows an example of the structure of claim 3 of the present invention, in which the role of a control bit is realized by an upper gate 7 formed on a quantum dot system via an insulating film 11. is there. Here, the upper gate 6 for control bits is installed above two quantum dots (control bits) of the four quantum dot systems (FIGS. 5A and 5B). At this time, the upper gate need not be strictly right above, but may be obliquely above and away from the quantum dot system. When a voltage is applied to the gate electrode by the upper gate, first electrons are first injected toward the control bit. Here, by further applying a voltage to the gate electrode, electrons enter the target bit.

In the present invention, since the gate electrode for injecting charges into the quantum dots is formed in the same plane as the gate electrode, the effect of the presence or absence of charges in the quantum dots on the current is sensitive. It is. Further, in the present invention, the formation of an inversion layer or a weak inversion layer in the enhancement type is affected by the presence or absence of charges in the quantum dots,
Further, in the depletion type, charge is injected into the quantum dots and depleted, so that a change in the current flowing through the channel layer and a shift in the threshold can be observed. Further, the present invention can also be used in a state where the state under the quantum dot is not completely inverted, in a sub-threshold region. Further, in the present invention, the presence or absence of the electric charge in the quantum dot can be used even if there is a short channel effect which becomes a problem in a normal MOS device because the change in the current flowing in the channel layer is observed.

[0012]

FIG. 1 shows a first embodiment of the present invention. The manufacturing method of this embodiment will be described. First, an element region is formed on the p-Si substrate 7 by the LOCOS method or the STI method. Next, gate oxidation is performed to pattern a thermal oxide film 8 having a thickness of about 3 nm for forming a quantum dot structure. Next, while the resist remains, ion implantation is performed to form source 9 and drain 10 regions. Next, after poly-Si is deposited by LPCVD or the like, a quantum dot structure of 0.1 μm or less serving as a target bit 1 and a control bit 2 and a gate electrode 3 for a target bit are formed.
The control bit gate electrode 4 is patterned using EB or the like. Here, after a quantum dot structure is manufactured in order to further reduce the size of the quantum dot, thermal oxidation can be performed again to oxidize the surface of the quantum dot and further reduce the conductive portion thereof. In the production of this quantum dot structure, an element having a large surface migration, such as amorphous Si, may be deposited and then heat-treated to form a mass. At this time, particles accelerated by using FIB or the like may be injected into a portion where quantum dots are to be formed, and may be damaged.

When a metal such as Al is used for the quantum dots, fine metal particles which can be formed at an early stage of deposition by a sputtering method may be used. At this time, oxidize the surface thinly,
A thin oxide film of about several nm can be formed on the surface of the quantum dot, and the operation speed can be adjusted. An interlayer insulating film is formed thereon, a contact hole is opened, and an electrode portion is connected to an external electrode. FIG. 4 shows a second embodiment of the present invention. First, the element region is set to L on the p-Si substrate 7.
It is formed by the OCOS method or the STI method. Next, gate oxidation is performed to pattern a thermal oxide film 8 having a thickness of about 3 nm for forming a quantum dot structure. Next, while the resist remains, ion implantation is performed to form source 9 and drain 10 regions. Next, after depositing poly-Si by LPCVD or the like, target bits 1 and
The quantum dot structure of 0.1 μm or less as the control bit 2 and the first gate electrode 5 are patterned using EB or the like. Here, after a quantum dot structure is manufactured in order to further reduce the size of the quantum dot, thermal oxidation can be performed again to oxidize the surface of the quantum dot and further reduce the conductive portion thereof. In the production of this quantum dot structure, an element having a large surface migration, such as amorphous Si, may be deposited and then heat-treated to form a mass. At this time, particles accelerated by using FIB or the like may be injected into a portion where quantum dots are to be formed, and may be damaged.

When a metal such as Al is used for the quantum dots, metal fine particles which can be formed at the initial stage of deposition by sputtering may be used. At this time, oxidize the surface thinly,
A thin oxide film of about several nm can be formed on the surface of the quantum dot, and the operation speed can be adjusted. An interlayer insulating film is formed thereon, and a contact hole is opened. The difference from the first embodiment is that after forming the quantum dot system, CV
The SiO ₂ oxide film 11 as shown in FIG.
A second control bit gate electrode 6 is formed by LPCVD using poly Si and patterned, and then an interlayer insulating film is formed and connected to an external electrode. Next, the principle of sensing the electric charge distribution in the quantum dot by a change in current according to the present invention will be described using an embodiment. MO provided from gate electrode via oxide film
The S structure and the source and drain electrodes function to sense the charge distribution in the quantum dots. When electrons are injected into the quantum dot from the gate electrode, the current from the source electrode to the drain electrode is less likely to flow, since this corresponds to the rise of the Fermi surface in the dot. Voltages V ₁ to be used for the logic operation in the quantum dots is the number meV, because the threshold voltage is in the order of a few V, the control of both can be adjusted with a degree of freedom.

The electrons are shown in FIGS. 3 (a), (b), (f),
The current in the case where the current is distributed parallel to the source electrode and the gate electrode as shown in (g) and the current in the case where the current is smoothly distributed as shown in FIGS. 3 (c), (d), (e) and (h) are compared. In this case, since the current easily flows under the area where no electrons are present in the quantum dot, the current value is shown in FIGS. 3 (a), (b), (f),
In the case of (g), FIGS. 3 (c), (d), (e),
The flow is easier than in (h), and the threshold value of the gate electrode is small. Before and after multiplied by the voltages V ₁ in the present invention, when the current value is not changed, and current is also small 3
(C), FIG. 3 (a) if the current is large, the current value changes, FIG. 3 (e) if the flowing amount increases, and FIG. 3 (g) if the flowing amount decreases
Thus, the state in the quantum dot can be sensed. FIG. 6 shows an embodiment in which another quantum dot structure is provided below the quantum dot layer connected to the gate electrode. Through the thin oxide film on this substrate, the electrons flowing through the channel of the substrate into the created quantum dots by the voltage between the source and the drain and the voltage applied with some gate voltage, Acts on electrons in quantum dots connected to the gate electrode. Note that an insulating film is not necessarily required between the quantum dots on the substrate and the substrate. When the quantum dots are made of a metal material, they are substituted by a Schottky barrier. Further, in this embodiment, another quantum dot layer or a floating electrode may be provided between the quantum dot on the substrate and the quantum dot layer connected to the gate electrode.

FIG. 7A shows an embodiment in which auxiliary quantum dots are inserted between target bits and control bits. At this time, if a voltage at which the resonance levels of the two quantum dots in the target bit coincide with each other is applied to the target bit, as in FIG.
When a non-resonant voltage is applied while performing a controlled-NOT operation, the presence of an auxiliary bit generally causes

(Equation 5) Perform the operation that appears in. Where α, θ, φ are control bits,
The phase depends on the voltage of the target bit. This indicates a general rotation within the target bit. The electron distribution in the auxiliary bit is inverted with respect to the electron distribution in the control bit. Therefore, the distribution of electrons in the target bit is the same as that in the control bit for the target bit, that is,

(Equation 6) Is also included. FIG. 7B shows an element in which the distribution of electrons input to the quantum dots connected to the gate electrode performs an arithmetic operation according to the arrangement and size of the quantum dots existing between the gate electrodes. In the figure, the quantum dots indicated by white circles are smaller in size than the hatched quantum dots, so the position of the resonance quantum level is slightly higher.
In this embodiment, it is also possible to form an upper electrode structure above the quantum dot system via an insulating film, and to act on the quantum dot system. The symbol "A" in the figure indicates that the quantum dot has a different size from the other quantum dots. The quantum dots corresponding to the white circles may be quantum dots formed close to the substrate shown in FIG. Further, in the above embodiment, the quantum dot system and the gate electrode are formed on the channel between the source and the drain. However, as shown in FIG. 9, a current line for detecting the charge distribution in the quantum dot is provided in the quantum dot system. It may be a thing.

FIG. 10 shows an embodiment according to claim 6 of the present invention. As the manufacturing process, a normal CMOS manufacturing process can be basically used except for the portion where the quantum dots are formed. First, an element region is formed on a p-type Si substrate 15 by a LOCOS method, an STI method, or the like, similarly to a normal CMOS manufacturing process. After a first oxide film 16 having a thickness of about 2 nm is formed by thermal oxidation at a position where a gate electrode is to be formed, 6n
The first Si quantum dot layer 17 having a size of about m
A second oxide film 18 having a thickness of about 1 nm above the first Si quantum dot layer 17 is formed on the first Si quantum dot layer 17 by a CVD method. And the like. On the second oxide film 18, a second Si quantum dot layer 19 having a size of about 4 nm is formed. Next, the second Si quantum dot layer 19
An Si oxide film 20 having a thickness of about 8 nm is formed thereon by a CVD method or the like. Next, on the Si oxide film 20, poly-Si
Are formed by LPCVD or the like and patterned. After that, a source electrode 9 and a drain electrode 10 are formed by an ion plantation method. Further, an interlayer insulating film is formed thereon, and a contact hole is opened to electrically connect to another circuit.

The formation of the coupled quantum dots composed of the first and second quantum dots may be performed by the following method. After forming a first oxide film 16 having a thickness of about 2 nm by thermal oxidation,
LPCVD of the first poly-Si layer 17 having a size of about nm
It is formed by a method or the like. A second oxide film 18 having a thickness of about 2 nm or less is formed thereon by thermal oxidation, CVD, or the like.
Further, a second Si quantum dot layer 19 having a size of about 4 nm is formed thereon by LPCVD or the like. When these are heated at about 700 ° C., due to the stress in the Si quantum dots, the Si quantum dots are not oxidized, and the portions without the quantum dots are oxidized to the bottom to form coupled quantum dots. FIG. 10 shows a case in which the number of quantum dots is three or more in each of the upper and lower parts.
It becomes an controlled-NOT gate. Alternatively, a gate electrode 21 for controlling each coupled quantum dot may be provided above each coupled quantum dot as shown in FIG. 11, or as shown in FIG. 12, for each coupled quantum dot. On the gate electrode 21 to be controlled via an insulating film 22,
An upper gate electrode 23 for further controlling the current flowing through the channel may be provided. In FIGS. 10, 11, and 12,
Although the case where two quantum dots are formed in the direction perpendicular to the substrate is shown, three or more quantum dots may be formed in the direction perpendicular to the substrate.

In the present invention, poly-Si is used for the gate electrode. However, a metal such as silicide such as Ti or Co or Al or a magnetic material such as Fe, Co, Ni, PtCo or a compound thereof may be used. In forming silicide, about 20 nm of Ti is formed by EB evaporation after depositing about 20 nm of poly-Si by LPCVD. Here, RTA is performed at about 750 ° C. for about 30 seconds to perform silicidation. Next, only the structure patterned with poly-Si using sulfuric acid and hydrogen peroxide is left. Further, by performing a two-step annealing at about 800 ° C. for about 30 seconds, the C49 phase is converted to C54.
A low-resistance film of Ti silicide is formed by causing a phase transition to a phase. In the present invention, doping of the same type as the substrate (p type in the above) or different type (n
It is also possible to dope (of the type). In this embodiment, the Si oxide film is used as the oxide film.
A dielectric film such as iN or Zr oxide may be used. Further, after forming the first quantum dot layer 17, a second oxide film 18 is formed, and a different material from the second oxide film 18 is used without forming the second quantum dot layer 19. A third insulating film may be formed. In this case, the second oxide film 18 and the third
Since the insulating film is made of another material, a portion capable of accumulating charges is generated at these interfaces, and this portion replaces the second quantum dot layer 19. For example, a Si oxide film may be used as the second oxide film 18 and SiN may be used as the third insulating film.

Similarly, after forming the first oxide film 16,
The first oxide film 1 is formed without forming the first quantum dot layer 17.
A second insulating film may be formed using a material different from that of No. 6, and the second quantum dot layer 19 and the Si oxide film 20 may be formed thereon. Also in this case, since a portion capable of accumulating charge is generated at the interface between the first oxide film 16 and the second insulating film, this portion replaces the first quantum dot layer 17 and forms a coupled quantum dot. A similar effect can be obtained. Further, even when three or more coupled quantum dots are formed, 1
Instead of one or a plurality of quantum dots, a charge storage portion at an interface between different insulating films may be provided. In the present invention, it can be used as an LDD structure. Although the present invention has been described using a p-type Si substrate, an n-MOS structure of an n-type Si substrate, or an n-type or p-type SOI substrate may be used. FIG. 13 shows the sixth and seventh embodiments of the present invention, in which a heterojunction is used.
In FIG. 13A, n-type AlGaAs, GaAs, and p-type AlGaAs are formed on a GaAs substrate by using an MBE apparatus or the like.
Are deposited in the order of about 3 nm, about 2 nm, and about 2 nm, respectively, and a Ti / Au quantum dot connected to the gate electrode is patterned thereon. By applying a voltage to this gate electrode, a distribution of electrons is generated at the p-type AlGaAs / GaAs interface, and the quantum computer operates based on this interface electron distribution. The GaAs / n-type AlGaAs interface is connected to the source / drain electrodes, which controls the two-dimensional electron layer by quantum dots connected to the gate electrode, and is an example of a depletion type device.
The structure is such that a detection current reflecting the charge distribution in the quantum dot flows.

FIG. 13B shows an embodiment using a two-dimensional electron layer generated at the Si / SiGe interface. A SiGe layer is deposited on a Si substrate to a thickness of about 3 nm by a gas source MBE apparatus. Subsequently, the poly-Si quantum dot structure is patterned so as to be connected to the gate electrode. As described above, in the semiconductor device of the present invention, the quantum dots of each layer may be two-dimensionally arranged as well as one-dimensionally arranged on the substrate.

[0022]

The present invention provides means for realizing a controlled-NOT circuit which is one of the important basic operations of a quantum computer in a semiconductor electronic system which has not been realized conventionally, and is conventionally difficult. Control in the Si-LSI circuit
The d-NOT circuit and the sense line can be realized by a normal MOS fabrication process.

[Brief description of the drawings]

FIG. 1 shows a structure according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining the operation principle of the present invention.

FIG. 3 shows an example of the operation principle of the present invention.

FIG. 4 shows a structure according to a second embodiment of the present invention.

FIG. 5 schematically shows a structure according to a second embodiment of the present invention.

FIG. 6 schematically shows a structure according to a second embodiment of the present invention.

FIGS. 7A and 7B schematically show structures according to third and fourth embodiments of the present invention.

FIG. 8 shows a conventional example.

FIG. 9 schematically shows a structure of a current line in each embodiment of the present invention.

FIG. 10 schematically shows a structure according to a fifth embodiment of the present invention.

FIG. 11 schematically shows a structure according to a modification of the fifth embodiment of the present invention.

FIG. 12 schematically shows a structure according to a modification of the fifth embodiment of the present invention.

FIGS. 13 (a) and 13 (b) schematically show structures according to sixth and seventh embodiments of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Quantum dot used as a target bit, 2 ... Quantum dot used as a control bit, 3 ... Gate electrode for a target bit, 4 ... Gate electrode for a control bit, 5 ... First gate electrode which injects electric charge into a quantum dot system, Reference numeral 6: upper gate electrode for control bits, 7: Si substrate, 8: oxide film, 9: source electrode, 10: drain electrode, 11: interlayer insulating film, 12: insulating film formed on the substrate, 13: insulating film 12, quantum dots formed on 12, 14 auxiliary quantum dots, 15 p-type Si substrate, 16 first oxide film, 17 first quantum dot layer, 18 second oxide film, 19 ... Second quantum dot layer, 20: Si oxide film, 21: Gate electrode, 22: Insulating film, 23: Upper gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/778 21/338 29/812 // H01L 27/115 F term (Reference) 5F001 AA92 AB02 AB04 AB20 AC01 AD13 AD17 AD21 AD80 AF10 5F040 DC01 DC03 EA09 EB03 EC16 EF02 EK01 FC02 FC05 FC19 5F083 FZ10 HA06 JA33 JA36 PR34 5F102 FB10 GA00 GB01 GC01 GC05 GD10 GJ03 GJ05 GJ10 GQ01 GQ03 GR16 GT01 GT03 GT05 GT08 HC01 HC01

Claims (6)

[Claims] 1. A semiconductor device comprising: two or more microstructures of 0.1 μm or less made of a conductor;
F and one or more gate electrodes that are electrically connected to be less than or equal to F, and applying a specific voltage to one or more of the gate electrodes to provide a charge distribution in at least two of the microstructures. A semiconductor element characterized by the following: 2. The method according to claim 1, wherein two or more microstructures of 0.1 μm or less made of a conductor are formed, and the first microstructure is electrically connected to the microstructures so as to have a junction capacitance of 0.1 μF or less. Having a gate electrode and a second gate electrode that is electrically connected to the two or more microstructures that are not connected to the first gate electrode so that the junction capacitance is 0.1 μF or less. Characteristic semiconductor element. 3. Four or more fine structures made of a conductor are formed on a substrate via an insulating film, and are electrically connected to two or more of the fine structures. A semiconductor device comprising: one or a plurality of first gate electrodes; and the fine structure and a second gate electrode formed over the first gate electrode with an insulator interposed therebetween. 4. The semiconductor device according to claim 2, wherein the first gate electrode, the second gate electrode, and the fine structure are formed on a semiconductor substrate via an insulating film, and have a source electrode and a drain electrode. . 5. The semiconductor device according to claim 3, wherein said first gate electrode, said second gate electrode, and said fine structure are formed on a semiconductor substrate via an insulating film, and have a source electrode and a drain electrode. . 6. A microstructure composed of a conductor and having two or more microstructures of 0.1 μm or less, and the microstructure and a connection capacitance of 0.1 μm or less.
F, a charge supply layer electrically connected to be less than or equal to F, and one or more gate electrodes formed over the microstructure through an insulator, and a specific voltage is applied to the gate electrode. A semiconductor device, wherein the addition changes the charge distribution in at least two of the microstructures.