JP2000148511A - Interruption processor for microcomputer and its interruption processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time to be required from the active state of an interruption signal outputted from a peripheral unit up to the start of practical processing based on an interruption processing program. SOLUTION: An interruption processing base address pointer(IBAP) 8 is included in a peripheral unit 7 and a central processing unit(CPU) 1 reads out the IBAP simultaneously with the reading of a vector address from an interruption controller(INTC) 5, adds the value of the IBAP to the value of a program counter(PC') read out from a register bank 4 and writes the added value in a PC 2 built in the CPU 1 itself. Since an address indicated by 'PC+IBAP' is the leading address of a program for executing original interruption processing, the prescribed interruption processing can be immediately started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interrupt processing apparatus and an interrupt processing method for a microcomputer which performs interrupt processing by context.

[0002]

2. Description of the Related Art An INTC unit in a microcomputer receives an interrupt signal from a built-in peripheral unit or an external device and interrupts a CPU. CP
U accepts the interrupt request and permits the interrupt. Thereafter, the CPU reads the interrupt vector address from INTC.

A method using context switching is as follows.
This is a method that can perform interrupt processing at high speed. That is, a plurality of register banks are built-in, and when interrupt processing is performed, the register bank is switched to exchange data (PC or PSW) required by the CPU, thereby quickly performing interrupt processing.

In context switching, the vector address read from the INTC by the CPU stores the number of the register bank to be switched, and performs interrupt processing based on the contents of the register bank of the register bank number.

In the interrupt processing program, parameters necessary for processing are read from the peripheral unit that has output the interrupt, and the contents of the interrupt are determined from these parameters to determine which interrupt processing is to be executed.

FIG. 7 shows a configuration example of a conventional microcomputer interrupt processing apparatus. The conventional microcomputer includes a CPU 1, an INTC 5, a timer 7 as a peripheral unit, and an internal BUS 9 connected to each. In the example, only the timer 7 is used as the peripheral unit, but this is optional.

The interrupt signal INT output from the timer 7
When M becomes active, the INTC 5 receives this and activates the interrupt request signal INTRQ. When INTRQ is active, the CPU 1 activates the interrupt permission signal INTAK under the condition for accepting an interrupt.

After that, the CPU 1 reads a vector address from the INTC 5 via the internal BUS 9. In this case, since the timer 7 is the interrupt source, the vector address corresponding to the timer 7 is read.

Since the interrupt process is performed in accordance with the context, the address indicated by the read vector address includes
Information on which register bank is indicated is stored. The CPU 1 reads the register bank number and switches the register bank. At this time, CPU1
PC2 and PSW3 are replaced with the values PC 'and PSW' stored in the selected register bank 4.

Thereafter, the CPU 1 branches to an address indicated by PC 'and starts interrupt processing. In the interrupt processing program, parameters necessary for performing the interrupt processing are read from the timer 7. This parameter is, for example, a count value of a timer. By judging these parameters, it is determined which processing should be performed, and the processing jumps to the top of the processing program to be performed.

FIG. 8 is a flowchart for explaining the flow of the interrupt processing described so far, and FIG. 9 shows the structure of the interrupt processing program.

As described above, the microcomputer accepts an interrupt and performs an interrupt process. In order to perform the interrupt process at a high speed, the microcomputer performs an interrupt process in a context.

However, as described below, even when the interrupt source is the same, when a plurality of interrupt conditions exist, a branch destination is determined by a program, so that high-speed interrupt processing cannot be executed.

Specifically, when executing interrupt processing by context-based interrupt processing, a branch destination address is read from a register bank, and after branching, a branch condition parameter is further read from an interrupt source.
This parameter is determined by the program, and the program branches to the head address of the program to be processed. This requires a great deal of processing time by the program before reaching the execution of the original branch destination program.

[0015]

As described above, in the conventional interrupt processing in the context of a microcomputer, after switching register banks and branching to an interrupt program, a parameter for performing the interrupt processing is read from a peripheral unit. It is determined which interrupt processing is to be performed based on the value of the parameter, and the process is further branched to the target interrupt processing program to start the processing.

[0016] Therefore, there is a drawback that a long time is required from when the interrupt signal output from the peripheral unit becomes active to when the processing by the actual interrupt processing program is started, and the response of the interrupt processing is poor.

For example, in a microcomputer that controls a servomotor, the number of revolutions of the servomotor can be controlled by using an interrupt from a timer. But,
In the conventional microcomputer interrupt processing method,
Even when a context is used, it is necessary to read parameters from the timer and make a decision before starting the processing to be really executed. In this case, it takes a great deal of time since the program needs to determine the parameters until the interrupt is accepted and the actual processing is started. Therefore, when the timer is interrupted and the servomotor is controlled, there is a serious disadvantage that the servomotor control cannot be performed in time.

An object of the present invention is to reduce the time from when an interrupt signal output from a peripheral unit becomes active to when processing by an actual interrupt processing program is started, and to realize a microcomputer capable of high-speed interrupt processing. An object of the present invention is to provide an interrupt processing device and an interrupt processing method.

[0019]

SUMMARY OF THE INVENTION The present invention relates to an interrupt processing apparatus for a microcomputer which performs interrupt processing in context, in which a CPU reads parameters necessary for interrupt processing branch from an interrupt controller when an interrupt occurs and registers the register bank of the CPU. Is added to the branch destination address stored in the register, and the program branches directly to the start address of the interrupt processing program as a new branch destination address.

According to the present invention, in a microcomputer interrupt processing method for performing interrupt processing in context, when an interrupt occurs, a CPU reads parameters necessary for interrupt processing branch from an interrupt controller and stores the parameters in a register bank of the CPU. And adding a new branch destination address and branching directly to the start address of the interrupt processing program as a new branch destination address.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an interrupt processing device for a microcomputer according to the present invention. FIG. 2 is a block diagram illustrating a portion related to the present invention in the CPU.

The interrupt processing device of the microcomputer shown in FIG. 1 includes a central processing unit (CPU) 1, an interrupt controller (INTC) 5, a timer 7, and an internal BUS 9 for connecting each unit bidirectionally. It is configured.

The CPU 1 has a program counter (PC) 2, a PSW 3 and a register bank 4 therein, the INTC 5 has an interrupt processing base address pointer (IBAP) 6 therein, and the timer 7 has
An IBAP 8 is provided inside.

In this embodiment, only one peripheral unit (timer) is provided, but the number of peripheral units is arbitrary.

In FIG. 1, INTM is an interrupt request signal output from the timer 7, and INTRQ is
This signal is used to make an interrupt request to the CPU 1 when INTM input to TC5 is active.
K is an interrupt enable signal which becomes active at the interrupt enable timing in response to the active level of INTRQ input to the CPU 1.

FIG. 2 shows a register bank 4 in the CPU, a temporary register (TMPA) 11, a temporary register (TMPB) 12, and an adder (ALU) 1.
3 and PC2.

The difference between this embodiment and the conventional microcomputer shown in FIG. 7 is that an IBAP8 register is provided in the timer and an IBAP6 is similarly provided in the INTC. Further, the value of PC, which is the address of the branch destination, is
As shown in FIG. 2, PC ′ is read from the register bank 4 and stored in TMPA11, and the value of IBAP is changed to TMBPB.
12 and added by the ALU 13 to obtain.

Next, the operation of the first embodiment will be described with reference to FIGS. 1, 2, 3 and 4. FIG.
FIG. 4 is a flowchart illustrating the flow of an interrupt process according to the first embodiment, and FIG. 4 is a diagram illustrating an address map of an interrupt processing program.

Interrupt request signal I output from timer 7
NTM becomes active and issues an interrupt request to INTC5. The INTC 5 receives the interrupt request in response to the fact that the INTM has become active, and
Activate the interrupt request signal INTRQ for 1

Next, the value of IBAP8 in the timer 7 is stored in the IBAP6 in the INTC5 via the internal BUS9. This processing is executed by the CPU 1 even if the INTC 5 executes it.
May be performed.

Next, the CPU 1 outputs the interrupt enable signal I under the condition that the interrupt can be accepted (for example, when the condition for enabling the interrupt is satisfied in the process being executed).
Activate NTAK.

The CPU 1 reads the vector address and the value of IBAP6 from the INTC5. The value of IBAP6 is stored in TMPB12 shown in FIG. Since the interrupt process is performed by the context, the CPU 1 reads the register bank number from the address indicated by the read vector address. The CPU 1 switches to the register bank 4 indicated by the read register bank number.

In FIG. 2, the CPU 1 reads PC ′ in the register bank 4 and transfers it to the TMPA 11.
The value of the IBAP stored in the TMPA 11 and the TMPB 12 is added to the ALU 13 and the result is transferred to the PC 2. The old PC value is written into the register bank.

Next, PSW 'is read from the register bank and written to PSW3. The old PSW value is written to the register bank.

The CPU 1 branches to the address indicated by the value of the PC 2 and shifts to execution of interrupt processing. As shown in FIG. 4, the interrupt processing program to be executed is changed depending on the value of IBAP.

The IBAP provided in the timer holds an arbitrary value. For example, the IBAP may hold a read value of a certain timer or an arbitrary value written by the CPU.

FIG. 5 is a block diagram showing a second embodiment of an interrupt processing device for a microcomputer according to the present invention, and FIG. 6 is a flowchart for explaining the flow of interrupt processing.

The interrupt processing device of the microcomputer shown in FIG. 5 includes a CPU 1, an INTC 5, a timer 7
And an internal BUS 9 for connecting each unit bidirectionally.

The CPU 1 has a PC 2 and a PAW inside.
3, a register bank 4, and an IBAP 10. The timer 7 has an IBAP 8 therein.

In this embodiment, one timer is incorporated as a peripheral unit, but the number of peripheral units is arbitrary.

Next, the operation of the second embodiment will be described with reference to FIGS.

Interrupt request signal I output from timer 7
NTM becomes active and issues an interrupt request to INTC5. INTC5 activates an interrupt request signal INTRQ for CPU1.

The CPU 1 has an IBAP 8 in the timer 7
Value of IBAP10 in CPU 1 via internal BUS9
To be stored. Next, the CPU 1 activates the interrupt permission signal INTAK under the condition that the interrupt can be received (for example, when the condition for permitting the interrupt is satisfied in the executed processing).

CPU 1 reads the vector address from INTC5. Since the interrupt process is performed by the context, the CPU 1 reads the register bank number from the address indicated by the read vector address. CPU1
Switches to the register bank indicated by the read register bank number.

Next, the CPU 1 reads PC 'in the register bank 5, adds it to the value stored in the IBAP 10, and transfers the result to PC2. Old PC2 value and old P
The procedure for writing the value of SW3 to the register bank is the same as in the first embodiment. The CPU 1 branches to the address indicated by the value of the PC 2 and shifts to execution of interrupt processing.

In the embodiment described above, the IBAP 8 is provided in the peripheral unit, and when the CPU 1 reads the vector address from the INTC 5, the IBAP is read at the same time, and the value of the IBAP is read into the PC 'value read from the register bank 4 by the CPU 1. And writing to the PC 2 in the CPU 1 is performed. Since the address indicated by PC + IBAP is the start address of the program that executes the original interrupt processing, the predetermined interrupt processing can be started immediately. This improves the disadvantage that the response of the conventional interrupt processing is poor.

The difference between the second embodiment and the first embodiment shown in FIG. 1 lies in that the IBAP is built in the CPU 1. In this case, IBAP is added to INTC5.
Since there is no need to provide the above, there is an advantage that the size can be reduced in terms of hardware.

The IBAP provided in the CPU is CP
Since it may be a built-in memory accessible by U or a general-purpose register, there is an advantage that an increase in hardware is suppressed.

Further, the present invention can be implemented in any area as long as the CPU can read the IBAP.

Further, in the above-described embodiment, the IBAP is provided in the timer so that an arbitrary value of the timer can be written. However, the IBAP is also a place where the arbitrary value in the timer can be reflected. The present invention can be practiced without any problems.

[0052]

As described above, the microcomputer interrupt processing apparatus of the present invention reads the value of PC from the register bank by the interrupt processing by context, adds the value of IBAP read in advance, and calculates the result. By writing as a new PC, the period from the occurrence of an interrupt to the start of actual processing is extremely shortened, and there is a great effect that the response to the interrupt processing is improved.

In addition, the conditional branch judgment program which has been described at the head of the interrupt processing program becomes unnecessary, and the program area can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an interrupt processing device of a microcomputer according to the present invention.

FIG. 2 is a block diagram illustrating a portion related to the present invention in a CPU.

FIG. 3 is a flowchart illustrating a flow of an interrupt process according to the first embodiment;

FIG. 4 is a diagram showing an address map of an interrupt processing program.

FIG. 5 is a block diagram showing a second embodiment of the microcomputer interrupt processing apparatus of the present invention.

FIG. 6 is a flowchart illustrating a flow of an interrupt process according to the second embodiment;

FIG. 7 is a block diagram showing an example of a conventional microcomputer interrupt processing device.

FIG. 8 is a flowchart illustrating a flow of a conventional interrupt process.

FIG. 9 is a diagram showing the structure of a conventional interrupt processing program.

[Explanation of symbols]

Reference Signs List 1 Central processing unit (CPU) 2 Program counter (PC) 3 PSW 4 Register bank 5 Interrupt controller (INTC) 6, 8, 10 Interrupt processing base address pointer (IBAP) 7 Timer 9 Internal BUS 11 Temporary register (TMPA) 12 Temporary Register (TMPB) 13 Adder (ALU)

Claims (8)

[Claims] An interrupt processing device for a microcomputer which performs interrupt processing in a context. In a microcomputer, when an interrupt occurs, a CPU reads parameters necessary for interrupt processing branch from an interrupt controller.
An interrupt processing apparatus for a microcomputer, which adds a branch destination address stored in a U register bank and directly branches to a start address of an interrupt processing program as a new branch destination address. 2. The microcomputer according to claim 1, wherein the parameter read by the CPU at the time of interrupt processing is read directly from a peripheral unit instead of the interrupt controller and stored in the CPU. . 3. The method according to claim 2, wherein the parameter read by the CPU at the time of interrupt processing is stored in a location related to the peripheral unit that generated the interrupt.
3. The interrupt processing device of the microcomputer according to claim 1. 4. The microcomputer according to claim 2, wherein a location for storing the parameter read out by the CPU at the time of interrupt processing is a storage location accessible by the CPU. 5. A microcomputer interrupt processing method for performing interrupt processing in a context, wherein a CPU reads a parameter necessary for interrupt processing branch from an interrupt controller when an interrupt occurs, and
A microcomputer interrupt processing method characterized by adding a branch destination address stored in a U register bank and branching directly to a start address of an interrupt processing program as a new branch destination address. 6. The method according to claim 5, wherein the parameter read by the CPU at the time of interrupt processing is read directly from a peripheral unit in place of the interrupt controller and stored in the CPU. . 7. The apparatus according to claim 6, wherein the parameter read by the CPU at the time of interrupt processing is stored in a location related to the peripheral unit which generated the interrupt.
3. The interrupt processing method of the microcomputer according to 1. 8. The interrupt processing method according to claim 6, wherein a location for storing the parameter read by the CPU at the time of interrupt processing is a storage location accessible by the CPU.