JP2000138724A - Serial data communication equipment and communicating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a serial data communication equipment and a communicating method, which use two transmission lines consisting of a unidirectional data output transmission line and data input transmission line and perform transmission and reception in clock synchronization. SOLUTION: This device respectively uses a data output transmission line S5 for dedicated unidirectional communication and a data input transmission line R5 for dedicated unidirectional communication as two transmission lines, and the master side circuit part 1a of a transmission side has a transmission control part, which activates a transmission request which is generated inside the part 1a when transmission data from a central controller is inputted, makes the master side circuit part itself a transmission state and also is notified to a slave side circuit part 1b which is a transmission destination, receives a clock signal for reception transmission from the part 1b, in response to this activation from the line R5 and outputs serial data to the line S5 in synchronization with the clock signal for reception.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication apparatus and a communication method, and more particularly, to a serial communication using a unidirectional data output transmission line and a data input transmission line and transmitting data output from a master side circuit unit. A transmission request is sent to the slave side circuit unit with a transmission request that is output to the line and becomes high level during the data transmission period, and the data output transmission line is synchronized with the clock signal input from the slave side circuit unit via the data input transmission line. The present invention relates to a serial data communication device that outputs serial data and a communication method.

[0002]

2. Description of the Related Art Referring to FIG. 9A showing an example of device connection of an example of a conventional serial data communication device of this type and FIG. 9B showing a timing chart thereof, FIG. Is generally called a start-stop synchronization type, which enables simultaneous transmission and reception with only two transmission lines.
For example, referring to FIGS. 9A and 9B, each of the transmission-side data TXD of the master-side circuit unit 31 includes a transmission-side master-side circuit unit 31 and a reception-side slave-side circuit unit 32. It consists of a low-level period STB called a start bit at the head of the group of data and transmission data portions D0,..., D7, and the timing of both transmission and reception is adjusted based on the low-level period STB of the start bit.

Generally, in serial communication, there is a time lag between a transmission / reception request and a transmission / reception. That is, the transmission / reception request requires several clocks, whereas the transmission / reception request takes several tens to several tens clocks for one data.

At the time of this timing adjustment, clocks are counted from tens to several tens of times, and subsequent bit switching is also performed based on the low level period STB of the start bit. Therefore, the data can be transferred only at a speed that is ten to several tens times slower than the operation clock used for the internal circuit of the communication device. Referring to FIG. 10 (a) showing a connection example of a transmission / reception device in another conventional example and FIG. 10 (b) showing a timing chart thereof, this conventional example is generally called a clock synchronous system, and a master on the transmission side is used. The clock SDK of the master-side circuit unit 33 includes a low-level period STB of a start bit at the head of a group of clocks and a transmission data portion A0,. , A7, D0,..., D7, and the timing of both transmission and reception is adjusted based on the low level period STB of the start bit.

In this example, high-speed serial communication synchronized with a clock signal SDK is enabled. However, since a dedicated transmission line is required for the clock signal SDK,
When the transmission and reception transmission lines are combined, a total of three transmission lines are required.

Referring to FIG. 11A showing a connection example of a transmission / reception device in another conventional example, and FIG. 11B showing a timing chart thereof, this conventional example is generally called a serial bus, Master circuit 35 on the side, slave circuits 36 and 37 on the receiving side, and transmission line S
There are provided resistance elements RL1 and RL2 for pulling up CL and SDA to a high logic level.

In this method, serial communication can be performed between a plurality of devices, but serial data communication is performed by transferring an address for device selection and transmission / reception data in synchronization with a clock signal. However, both the clock signal and data terminals must be able to input and output, so a bus floating prevention circuit such as a pull-up resistor element is required to prevent the terminals from becoming undefined during input. And

[0008]

As described above, in the start-stop synchronization method of the conventional serial data communication apparatus, clocks are counted from dozens to tens of times at the time of timing adjustment, and at the time of bit switching thereafter. Since the operation is performed based on the low level period STB of the start bit, there is a drawback that the transfer can be performed only at a speed several tens times to several tens times slower than the operation clock used for the internal circuit of the communication device.

On the other hand, in the other clock synchronous system, a dedicated transmission line is required for the clock signal SDK, so that a total of three transmission lines are required when transmission and reception transmission lines are combined. Has the disadvantage of not leading to a reduction in

In the other serial bus system, both the clock signal terminal and the data terminal must be in a state where they can be input / output. Therefore, when data is input, the terminal is prevented from becoming undefined. There is a disadvantage that a bus floating prevention circuit such as a pull-up resistor element is required.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned disadvantages of the related art, and uses a unidirectional data output transmission line and a data input transmission line, and outputs data from a master side circuit section to a data output transmission line. Sends a transmission request to the slave side circuit unit with a transmission request signal that goes high during the data transmission period, and serial data is transmitted to the data output transmission line in synchronization with the clock signal input from the slave side circuit unit via the data input transmission line. An object of the present invention is to provide a serial data communication device and a communication method for outputting.

[0012]

A feature of the serial data communication apparatus according to the present invention is that in a serial data communication apparatus used for transmitting and receiving bidirectional serial data through two transmission lines, the two transmission lines are unidirectional. A data output transmission line dedicated to communication and a data input transmission line dedicated to one-way communication are used, and the transmission side master side circuit section is generated in the master side circuit section with the input of parallel data given from the central control unit. In addition, the master-side circuit unit itself is set to the transmission mode and a transmission request for notifying the slave-side circuit unit of the transmission destination is activated, and a reception request transmitted from the slave-side circuit unit in response to the activation is transmitted. A clock signal is received from the data input transmission line, and the parallel data is serially transmitted to the data output transmission line in synchronization with the reception clock. In that it has a transmission control means for converting output over data.

Further, the transmission control means includes a transmission FIFO buffer for inputting the transmission request and the parallel data from the central control unit, a first buffer for receiving the parallel data from the FIFO buffer, and a buffer for the transmission. A first shift register that converts the parallel data from the data into serial data and shifts out the data, and extracts a reception clock signal transmitted from the transmission destination in the transmission mode and outputs the signal to the first shift register. A transmission control circuit for outputting the transmission request and transmission completion signal, and converting serial data received from the transmission destination via the data input transmission line into parallel data and shifting and outputting the parallel data; Second
And a second buffer for receiving parallel data output from the shift register, and a second buffer for branching and extracting a reception clock transmitted to the destination in the reception mode, and outputting the extracted clock to the second shift register. A reception control circuit comprising two clock extraction circuits and outputting the reception completion signal and the parallel data; a reception FIFO buffer receiving the parallel data output from the reception control circuit and outputting the parallel data to the central control device; An arbitration circuit that receives the reception clock signal, the transmission completion signal, the reception completion signal, and the transmission request from the transmission destination and outputs a transmission mode signal and a reception mode signal, respectively, and receives serial data from the transmission destination A clock generation circuit for generating the reception clock signal for performing It may comprise a transceiver changeover circuit for output clock signal and the one of the serial data from the transmission control circuit to select in response to the transmission mode signal the data output transmission line.

Further, the transmission control means determines which of the transmission requests input from both the master side circuit section and the slave side circuit section is to be accepted, and determines the transmission mode in each circuit section. Alternatively, there may be provided an adjusting means for setting a state of the reception mode.

Further, when the master side circuit section and the slave side circuit section each make the transmission request with each other, the transmission operation from the master side circuit section and the transmission operation from the slave side circuit section are performed. So that
It is also possible to have a continuous operation control means for forcibly inserting a transmission period of the slave side circuit unit immediately after the transmission of the master side circuit unit to limit a continuous transmission operation of the master side circuit unit.

Further, at least one set of the transmission control means may be provided on the transmission side and the reception side, and serial data may be bidirectionally transmitted and received through two transmission lines using a dedicated line for unidirectional communication.

Further, the timing at which the slave-side circuit section arbitrarily delays the change timing of the reception clock signal sent from the slave-side circuit section at the time of data transmission of the master-side circuit section in accordance with the state of the master-side circuit section. Adjustment means can also be provided.

The serial data communication method according to the present invention is characterized in that, in the serial data communication method used for bidirectional transmission and reception of serial data by two transmission lines, a transmission request from a central control unit and a parallel data inputting operation. FIFO buffer means, first buffer means for receiving the parallel data from the FIFO buffer means, first shift register means for converting the parallel data from the buffer means into serial data and shifting and outputting the serial data, and a transmission mode. A first clock extracting means for extracting a reception clock signal transmitted from a transmission destination at a time and outputting the clock signal to the first shift register; a transmission control means for outputting the transmission request and a transmission completion signal; Parallel serial data received from the destination via the input transmission line Second shifting output is converted to over data
Shift register means, a second buffer means for receiving parallel data output from the shift register means, and a branch clock for receiving and transmitting a reception clock transmitted to the transmission destination in the reception mode to the second shift register. Receiving control means for outputting the reception completion signal and the parallel data, the receiving control means comprising: a second clock extracting means for outputting;
A reception FIFO buffer for receiving the parallel data output from the reception control means and outputting the parallel data to the central control device, the reception clock signal from the transmission destination, the transmission completion signal, the reception completion signal, and the transmission Arbitration means for receiving each request and outputting a transmission mode signal and a reception mode signal, clock generation means for generating the reception clock signal for receiving serial data from a transmission destination, and the reception clock signal and the transmission Transmission / reception switching means for selecting one of serial data from the control means in response to the transmission mode signal and outputting the selected data to the data output transmission line, and a data output transmission line dedicated to unidirectional communication as the two transmission lines; And a data input transmission line dedicated to one-way communication. In response to the activation of the transmission request, the transmission request is generated in the master-side circuit unit in accordance with the input of the real data, the master-side circuit unit itself is set to the transmission mode, and the slave-side circuit unit of the transmission destination is notified, and the transmission request is activated. The reception clock signal is transmitted from the slave side circuit unit and received from the data input transmission line, and the serial data is output to the data output transmission line in synchronization with the received reception clock signal. .

Further, the arbitration by the arbitration means of the master side circuit section maintains the wait state when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low logic level. When there is the transmission request in the wait state, the state transitions from the wait state to the transmission preparation period regardless of the signal level, and when the reception clock signal is received from the slave side circuit unit in response to the transmission request, Transition from the preparation period to the transmission mode to start transmission of the serial data, and when predetermined data transmission is completed, output the transmission completion signal and transition to the wait state, there is no transmission request, and the data When the signal level of the input transmission line is high, the mode is changed to the reception mode, and the reception clock is changed. At the same time as starting transmission of a serial signal to the slave side circuit section, starting serial data reception from the slave side circuit section, and upon completion of the serial data reception, generating the reception completion signal, shifting to the wait state and waiting. Thus, the transmission operation can be prioritized.

Further, the arbitration by the arbitration means of the slave side circuit unit is such that the wait state is maintained when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low level. And, when the signal level is high level, transition is made to the reception confirmation period, and during this reception confirmation period, the transmission of the reception clock signal to the master side circuit is started, and at the same time, the data is transmitted from the master side circuit. The reception is started, and when the data reception is completed, the reception completion signal is generated, the state is shifted to the wait state, and the standby state is maintained. In the wait state, the transmission request is issued, and the data input transmission line is When the signal level is constant at the low level, a transition is made from the wait state to the transmission preparation period. If the signal level becomes high during the transition to the wait state, the standby state is set, and if the signal level becomes constant at the low level during the transmission preparation period, the transition to the transmission preparation period may be performed to prioritize the reception operation. it can.

Further, the arbitration by the arbitration means of the master side circuit section is such that the wait state is maintained when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low level. When there is the transmission request in the state, the state is changed from the wait state to the transmission preparation period, and when the reception clock signal is received from the slave side circuit unit in response to the transmission request, the transmission period is changed from the preparation period to the transmission mode. Transition to start transmission of the serial data, and when predetermined data transmission ends, output the transmission completion signal and transition to the reception confirmation state. In this state, if the signal level is constant at the low level, the wait State, and if the signal level is high, transition to the reception mode to perform the reception. At the same time as starting to transmit a clock signal to the slave side circuit unit, serial data reception is started from the slave side circuit unit, and when the data reception is completed, the reception completion signal is generated, the state is shifted to the wait state, and standby is performed. When there is no transmission request, and when the data input signal is at a high level, by immediately transiting to the reception mode, when there is a transmission request from both the master side circuit unit and the slave side circuit unit, the master side It is also possible to force the slave-side circuit unit to perform the transmission operation immediately after the transmission operation of the circuit unit.

The master-side circuit section is provided with a plurality of the transmission preparation periods and the reception confirmation periods, respectively, so that when there is a transmission request from both the master-side circuit section and the slave-side circuit section, mutual timing adjustment is performed. Can also be performed.

Further, the arbitration by the arbitration means of the slave side circuit unit is such that when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low level, the wait state is maintained. When the signal level is at a high level and the transition from the wait state to the reception confirmation period, the reception clock signal is transmitted to the master side circuit unit, and the transition from the reception confirmation period to the reception mode is performed. When the reception of serial data is started and the predetermined data reception is completed, if there is no transmission request, the state immediately transitions to the wait state, and if there is the transmission request, a reception completion signal is output and the state transits to the transmission preparation period. In this state, if the signal level is high, the state is changed to the wait state, and the signal level is If it is a low level, transition to the transmission mode to start receiving the reception clock signal from the master side circuit unit and simultaneously start the serial data transmission to the master side circuit unit, and when the serial data transmission ends, the The master-side circuit unit generates a transmission completion signal, transitions to the wait state, waits, and when there is no transmission request, and when the data input signal is at a constant low level, immediately transitions to the transmission preparation period. When there is a transmission request from both the slave side circuit unit and the master side circuit unit, the slave side circuit unit can be forced to perform the transmission operation immediately after the reception operation of the master side circuit unit.

Furthermore, a plurality of the transmission preparation periods and the plurality of reception confirmation periods are provided in the slave side circuit portion, respectively, so that when there is a transmission request from both the master side circuit portion and the slave side circuit portion, a mutual timing is provided. Adjustments can also be made.

The slave-side circuit section arbitrarily delays the change timing of the reception clock signal sent from the slave-side circuit section at the time of data transmission of the master-side circuit section in accordance with the state of the master-side circuit section. You can also.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention uses two transmission lines, one-way data output transmission line and data input transmission line, in serial communication, and makes a transmission request by level output of the data output transmission line. The serial data is output from the data output transmission line in synchronization with the reception clock signal input from the data input transmission line to perform serial data communication. FIG. 1 is a block diagram showing a configuration of a master side circuit section as a transmitting side and a slave side circuit section as a receiving side of a communication device according to the present invention. FIG. It is a timing chart.

Referring to FIG. 1, this communication device comprises a master side circuit section 1a and a slave side circuit section 1b having the same configuration.
Consists of The master side circuit unit 1a includes a FIFO buffer,
Since a transmission control circuit (including a buffer, a shift register, and a clock extraction circuit), a clock generation circuit, an arbitration circuit, and a transmission / reception switching circuit are provided, the functions of these components will be described in advance.

The FIFO buffer is provided with a microcomputer or DSP (Digital) that is the original transmission / reception request source.
Although the transmission / reception data that the Signal Processor wants to handle is parallel, the transmission / reception device of the present invention performs serial communication, so that a time lag occurs between a transmission / reception request and transmission / reception. As described above, the time for one data is several clocks for the transmission / reception request,
Transmission / reception execution requires several tens to several tens of clocks.
Therefore, FIFO (First-In First-
An Out (first-in first-out) buffer has a function of alleviating a time lag between the transmission / reception request and the transmission / reception.

The transmission / reception control circuit has a function of converting parallel data from the transmission FIFO buffer 2 into serial data and outputting the serial data, and generating a transmission request and a transmission completion signal.

A buffer in the transmission / reception control circuit has a transmission F
It has a buffer function for preparing to set a value in a shift register for converting parallel data from the I / O buffer 2 to serial data.

The shift register in the transmission / reception control circuit has a function of converting parallel data into serial data by shifting the parallel data at the timing of a clock signal transmitted from the transmission destination.

The clock extraction circuit in the transmission / reception control circuit is
In the transmission control circuit, the clock signal sent from the destination is extracted when the transmission mode signal is active, and in the reception control circuit, the reception clock signal sent to the data output transmission line is active. It has a function to take out at the time.

The clock generation circuit has a function of generating a reception clock signal to be output to a device that transmits the data when receiving the data. Since the apparatus of the present invention transmits its own data in synchronization with the clock signal of the other party, it has a clock generation circuit for supplying a receiving clock signal to the other party when it is in the receiving state.

The arbitration circuit has an adjustment function of determining which of the transmission requests from both the master and the slave (both the transmission / reception partner) is to be accepted, and includes a transmission control circuit, a reception control circuit, and a transmission / reception switching circuit. To operate in the transmission mode or the reception mode.

The transmission / reception switching circuit has a selection function of outputting data from the transmission control circuit in the transmission mode and outputting a reception clock signal from the clock generation circuit during reception.

The configuration of the communication device includes a transmission FIFO buffer 2 for inputting a transmission request and transmission data (here, for example, 8-bit parallel) from a central control unit (not shown), and a parallel transmission buffer from the FIFO buffer 2. A first buffer 31 for receiving data, a first shift register 32 for shifting and outputting the received parallel data in synchronization with a reception clock signal received from a slave side circuit unit, and a slave side of a transmission destination in a transmission mode. Circuit part 1
a transmission control circuit 3 having a first clock extraction circuit 33 for extracting the reception clock signal transmitted from the transmission control signal b and outputting a transmission request signal and a transmission completion signal, respectively; A clock generation circuit 8 for generating a reception clock to be transmitted to the slave side circuit unit 1b via the transmission line S5, and a second clock for extracting a reception clock signal input from the data output transmission line S5 in the reception mode A second shift register 62 which receives an input signal of serial data from the extraction circuit 63 and the data input transmission line R5, converts the input signal into parallel data in synchronization with an output clock of the second clock extraction circuit 63, and outputs a parallel output of the shift register. And a second buffer 61 for receiving data. A reception control circuit 6 for outputting a reception completion signal generated at the end of reception, a reception FIFO buffer 7 for receiving parallel data from the reception control circuit 6 and outputting it as reception data to a central control unit; An arbitration circuit 4 that receives a reception completion signal, a transmission request, and a reception clock signal to output a transmission mode signal and a reception mode signal, respectively, and receives the reception clock signal and the serial data from the transmission control circuit 3 to generate a transmission mode signal. A transmission / reception switching circuit 5 for outputting a response to the data output signal transmission line S5.

Since the configuration of the slave side circuit section has the same components as those described above, the description of the configuration here is omitted.

Next, the operation of the serial data communication apparatus having the above-described configuration will be described focusing on the operation in the master 1a side transmission mode.

For example, when transmission data is written as parallel data from the microcomputer or the DSP to the transmission FIFO buffer 2 of the master side circuit unit, the transmission FIFO
The buffer 3 of the transmission control circuit 3 via the IFO buffer 2
Passed to 1. Transmission control circuit 3 to which the transmission data has been passed
Converts the received transmission data into serial data, for example, 8-bit data D0 to D7 in this case, and outputs the data, and also outputs a master-side transmission request to the arbitration circuit 4.

This transmission request is sent to the transmission FIFO buffer 2
This signal is generated when the transmission data is set in the buffer 31 of the transmission control circuit via the interface, and maintains a high level state until the end of the transmission data.

Since the transmission completion signal is active and the reception completion signal is in an inactive state, the transmission mode is arbitrated.
Is output.

In response to the transmission mode signal 6, the transmission / reception switching circuit 5 outputs a high-level signal for a transmission request to the transmission destination to the data output transmission line S5, and the master side circuit unit 1a operates during the transmission preparation period. enter. Upon receiving the high-level signal for the transmission request, the slave-side circuit unit on the transmission partner side activates the transmission mode signal in the arbitration circuit 4 and outputs the signal to the transmission-reception switching circuit 5, whereby the slave-side circuit unit confirms the reception. Enter the period.

When the transmission mode signal becomes active, the transmission / reception switching circuit 5 selects the reception clock signal and starts transmitting the reception clock signal to the data output transmission line R5. At this stage, the slave side circuit section 1b receives the reception clock signal. Enter the mode period.

The transmission control circuit 3 of the master side circuit section 1a extracts the reception clock signal output on the data output transmission line R5 because the transmission preparation circuit is currently in the transmission preparation period. Supply. The shift register 32 is synchronized with the extracted reception clock signal.
Starts a shift operation, and its data output is sent to the data output transmission line S5 via the transmission / reception switching circuit 5.
Simultaneously with the start of the data transmission, the master side circuit section 1a enters the transmission mode period.

The slave side circuit section 1b converts the serial data on the data input transmission line R5 into its own receiving clock S.
9, the data is taken into the shift register 62, converted into parallel data, and output to the FIFO buffer 7 via the buffer 61. The FIFO buffer 7 outputs the parallel data to the central controller as reception data.

On the other hand, the master side circuit section 1a outputs the data output D
When the transmission of 0 to D7 is completed, the transmission request output from the arbitration circuit 4 becomes constant low in synchronization with the clock input from the data input transmission line R5, and the signal level on the data output transmission line S5 also becomes constant low. At the same time, it enters a wait state.

At the clock timing when the signal level on the data output transmission line becomes constant at the low level, the slave side circuit unit 1b sends the last bit D7 of the received data D0 to D7.
Is read into the shift register to enter a wait state. The above basic operation is repeated every time data is transmitted.

The state of the basic operation is described by the master side circuit unit 1.
Referring to FIG. 3 showing an operation transition diagram of the arbitration circuit 4 in FIG. 3A, when there is no transmission request after reset and the signal level of the data input transmission line R5 is low, the wait 20 state is maintained. When there is a transmission request from the central control device in the wait 20 state, the arbitration circuit 4 of the master control device 1a transits to the transmission preparation state 21 regardless of the signal level of the data input transmission line R5, and thereafter changes to the transmission mode 22 state. Transition to. After the transmission is completed, the state transits to the wait 20 state and waits. If there is no transmission request during the wait 20 state and the signal level of the data input transmission line R5 is constant at the high level, the mode transits to the reception mode 23. Here, a clock signal for reception is transmitted from the master side circuit section 1a to the slave side circuit section 1b, and serial data reception from the slave side circuit section 1b is started in synchronization with the clock.

When the serial data reception is completed, the transmission operation can be prioritized by transiting to the wait 20 state and waiting.

On the other hand, the arbitration circuit 4 of the slave side circuit unit 1b
Referring to FIG. 4 showing an operation transition diagram of FIG.
Means that there is no transmission request from the central control unit in the wait 20 state, and there is a transmission request to the master side circuit unit 1a during a wait period in which the signal level of the data input transmission line R5 is constant at a low level. When R5 goes high, the state transits to the reception confirmation 24 state and the reception mode 23 state. Upon completion of reception, the state transits to the wait state 20.

When there is a transmission request from the central control unit in the wait 20 state, and there is no transmission request to the master side circuit unit 1a, and the data input transmission line R5 becomes low level, the process transits to the transmission preparation 21. Here, if the data input transmission line R5 remains at the low level, the state transits to the transmission mode 22 state. When the transmission is completed, the state transits to the wait state 20. When the data input goes high during the period of the transmission preparation 21, a transition is made to the wait state.

In other words, even if there is data to be transmitted, the slave side circuit section 1b enters the transmission state when the data input transmission line S5 is at a high level due to a transmission request from the central control unit to the master side circuit section 1a. Not be in the receiving state. By making such a transition, the receiving operation is prioritized. After the reception is completed, it returns to the wait state and waits.

With this function, when the master-side circuit unit 1a and the slave-side circuit unit 1b try to transmit at the same time, the transmission operation of the master-side circuit unit 1a is prioritized to guarantee the normal circuit operation of bidirectional communication.

As described above, when there is a transmission request during the wait period, a transmission request with a high level output is issued during preparation for transmission on the data output transmission line. When preparations for both transmission and reception are completed, a reception clock signal is transmitted from the reception side via the data input transmission line, and the transmission mode period begins.
During the transmission mode, serial data is output from the data output transmission line in synchronization with the reception clock signal sent from the data input transmission line. The effect that high-speed bidirectional serial communication can be performed can be obtained.

That is, by sharing the data and the clock as the data output and the clock input during the transmission and the clock output and the data input during the reception, bidirectional serial communication can be realized with a small number of transmission lines.

By using a data output and a clock input during transmission and a clock output and data input during reception, high-speed serial communication synchronized with the clock can be performed.
Communication can be performed at a speed several tens to several tens of times faster than when the clock is not synchronized.

Further, by switching between data output and clock input during transmission and between clock output and data input during reception, each of the two transmission lines may be unidirectional.
Therefore, compared to the case where tri-state wiring is required, the floating prevention circuit of the bus becomes unnecessary,
This contributes to a reduction in circuit scale and power consumption.

Next, a second embodiment will be described. Referring to FIG. 5 showing a timing chart for explaining the operation of the second embodiment and FIG. 6 showing a state transition diagram of the arbitration circuit according to the second embodiment, FIG. Since the transmission request of the master side circuit unit 1a is prioritized, there is a possibility that the transmission from the slave side cannot be performed forever when the transmission request on the master side continues continuously. In the second embodiment, when there is a transmission request from both the master side circuit unit 1a and the slave side circuit unit 1b,
Transmission from master side circuit section 1a and slave side circuit section 1b
, The slave side circuit section 1b can also reliably transmit.

That is, referring again to FIG. 5, when there is a transmission request from both the master side circuit section 1a and the slave side circuit section 1b, the master side circuit section 1a starts preparation for transmission and the slave side circuit section 1b receives the signal. Get ready. The master side circuit section 1a synchronizes with the serial data D0 to D in synchronization with the reception clock signal transmitted from the slave side circuit section 1b.
7 is transmitted to the data output transmission line S5. When the transmission is completed, the slave side circuit section 1b immediately enters the transmission preparation period, and the master side circuit section 1a enters the reception confirmation period. Since the transmission request of the slave side circuit section 1b is maintained at a high level, the master side circuit section 1a outputs a clock to enter the reception mode, and enters the slave side circuit section 1b to the transmission mode to input data.

Referring again to FIG. 6 to describe the above-described operation in the transition state of the adjustment circuit of the master side circuit section 1a,
There is no transmission request after reset and the data input transmission line R
When the signal level of No. 5 is constant at the low level, the state of wait 20 is maintained. When there is a transmission request from the central control unit in the wait 20 state, the arbitration circuit 4 of the master side circuit unit 1a
Transitions to the transmission preparation 21a state regardless of the signal level of the data input transmission line S5, and then transitions to the transmission mode 22 state. After the transmission is completed, the state immediately shifts to the reception confirmation 24a and 24b without going to the wait 20 state. Here, if the signal level of the data input transmission line R5 (data output of the slave side circuit unit 1b) is constant at the low level, the state transits to the wait 20 state.

If the data output of the slave side circuit section 1b is constant at a high level, the mode shifts to the reception mode, and when the reception is completed, the mode shifts to the wait 20 state. In the wait 20 state, if there is no transmission request and the signal level of the data input transmission line R5 is constant at a high level, the mode transits to the reception mode 23, and when the reception is completed, the mode transits to the wait 20 state again.

The two sets of the transmission preparation 21 and the reception confirmation 24 are provided, for example, when both the master-side circuit unit 1a and the slave-side circuit unit 1b make a transmission request at the same time. Is repeated to adjust the stride of the timing.

Referring again to FIG. 7 to confirm the transition state of the adjustment circuit of the slave side circuit section 1b, when there is no transmission request after reset and when the signal level of the data input transmission line R5 is constant at a low level, the state of wait 20 is established. To maintain. When there is a transmission request from the central control unit in the wait 20 state, the arbitration circuit 4 of the slave side circuit unit 1b transits to the reception confirmation 24a and 2ba states, and then transits to the reception mode 23 state. After completion of reception, if there is no transmission request, the state transits to the wait 20 state.

If there is a transmission request, the process immediately transits to transmission preparation 21. Here, if the signal level of the data input transmission line R5 (data output of the master side circuit section 1a) is constant at a high level, the state transits to the wait 20 state.

If the data input transmission line S5 of the slave side circuit section 1b is at a constant low level, the mode transits to the transmission mode 22, and when the transmission is completed, the mode transits to the wait 20 state. In the wait 20 state, if there is no transmission request and the signal level of the data input transmission line R5 is constant at the low level, the state transits to the transmission preparation state 21. When the transmission is completed, the state transits to the wait 20 state again.

By making such a transition, when there is a transmission request from both the master side circuit unit 1a and the slave side circuit unit 1b, transmission from the master side circuit unit 1a and transmission from the slave side circuit unit 1b are performed. By alternately continuing, the slave-side circuit unit 1b can also reliably transmit, thereby ensuring a normal bidirectional communication circuit operation.

Next, a third embodiment will be described.
Referring to FIG. 8 showing a timing chart for explaining the operation of the arbitration circuit 4 according to the third embodiment, in this embodiment, the master-side circuit unit 1 in the reception mode.
4 shows a timing chart when the reception clock signal transmitted from the slave side circuit unit 1b at the time of transmission of a is not clock pulses at equal intervals at the serial data D1 and D2. As shown in this embodiment, since the receiving side controls the transfer timing in the present invention,
For example, the receiving side can freely delay the transfer timing in accordance with the state of the receiving FIFO buffer such as the vacancy.

[0068]

As described above, the serial data communication and communication method according to the present invention is a serial data communication apparatus used for transmitting and receiving bidirectional serial data through two transmission lines. A data output transmission line dedicated to one-way communication and a data input transmission line dedicated to one-way communication are used, respectively, and the master side circuit part on the transmission side is connected to the master side circuit part with the input of parallel data given from the central controller. Activates a transmission request that is generated and sets the master-side circuit unit itself to the transmission mode and notifies the slave-side circuit unit of the transmission destination, and a reception request transmitted from the slave-side circuit unit in response to this activation. A clock signal is received from a data input transmission line, and parallel data is converted to serial data and output to a data output transmission line in synchronization with a reception clock. Because it has a feeding control means, the data output and a clock input at the time of transmission, the sharing of data and clock to the clock output and the data input at the time of reception,
Bidirectional serial communication can be realized with a small number of transmission lines of two transmission lines. Also, by using a data output and a clock input during transmission and a clock output and a data input during reception, high-speed serial communication synchronized with the clock can be performed. Communication can be performed at a speed several tens to several tens of times faster than when the clock is not synchronized.

Furthermore, by switching between data output during transmission and clock output during clock input reception, the two wirings may be unidirectional. Compared to the case where tri-state wiring is required, a floating prevention circuit for the bus is not required, which contributes to a reduction in circuit size and power consumption.

[0070]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a serial data communication device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the serial data communication device of the present invention.

FIG. 3 is a state transition diagram of an adjustment circuit in a master side circuit unit 1a used for a basic configuration.

FIG. 4 is a state transition diagram of a modification of the adjustment circuit in the slave side circuit section 1b used in the basic configuration.

FIG. 5 is a timing chart for explaining the operation of the second embodiment of the serial data communication device of the present invention.

FIG. 6 is a state transition diagram of another modification of the adjustment circuit in the master side circuit section 1a used for the basic configuration.

FIG. 7 is a state transition diagram of another modification of the adjustment circuit in the slave side circuit section 1b used for the basic configuration.

FIG. 8 is a timing chart for explaining an operation of the serial data communication device according to the third embodiment of the present invention.

FIG. 9 is a configuration diagram illustrating an example of a conventional serial data communication device.

FIG. 10 is a configuration diagram showing another example of a conventional serial data communication device.

FIG. 11 is a configuration diagram showing still another example of a conventional serial data communication device.

[Explanation of symbols]

 1a Master side circuit section 1b Slave side circuit section 2 Transmission FIFO buffer 3 Transmission control circuit 4 Arbitration circuit 5 Transmission / reception switching circuit 6 Reception control circuit 7 Reception FIFO buffer 8 Clock generation circuit 20 Weight 21 / 21a Transmission preparation 22 Transmission mode 23 Reception mode 24a, 24b, 2ba Reception confirmation 31, 61 Buffer 32, 62 Shift register 33, 63 Clock extraction circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takashi Kuwahara 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term within NEC Icy Microcomputer Systems Co., Ltd. 5K034 AA01 AA11 AA15 DD01 EE06 EE08 FF01 HH05 HH23 HH24 MM05 NN13 PP01 5K047 AA16 BB05 GG03 GG06 GG11 HH17 LL04 LL05 MM26 MM27

Claims (14)

[Claims] 1. A serial data communication device used for transmitting and receiving bidirectional serial data through two transmission lines, wherein the two transmission lines are a data output transmission line dedicated to unidirectional communication and a data input transmission line dedicated to unidirectional communication. Each transmission line is used, and the transmission-side master-side circuit section is generated in the master-side circuit section in response to the input of parallel data given from the central control unit, and the transmission circuit is set while the master-side circuit section itself is in the transmission mode. Activate a transmission request for notifying the previous slave side circuit unit, receive a reception clock signal transmitted from the slave side circuit unit in response to this activation from the data input transmission line, and Transmission control means for converting the parallel data into serial data and outputting the serial data to the data output transmission line in synchronization with a clock; Serial data communication device. 2. A transmission FIFO buffer for receiving the transmission request and the parallel data from the central control unit, a first buffer receiving the parallel data from the FIFO buffer, and a transmission buffer. A first shift register that converts the parallel data from the data into serial data and shifts out the data, and extracts a reception clock signal transmitted from the transmission destination in the transmission mode and outputs the signal to the first shift register. A transmission control circuit for outputting the transmission request and transmission completion signal, and converting serial data received from the transmission destination via the data input transmission line into parallel data and shifting and outputting the parallel data; A second shift register and a second buffer for receiving parallel data output from the shift register; And a second clock extraction circuit for branching and extracting a reception clock transmitted to the transmission destination in the reception mode, extracting the reception clock, and outputting the extracted clock to the second shift register. , A reception FIFO buffer that receives the parallel data output from the reception control circuit and outputs the parallel data to the central controller, the reception clock signal from the transmission destination, and the transmission completion signal ,
An arbitration circuit that receives the reception completion signal and the transmission request, and outputs a transmission mode signal and a reception mode signal, a clock generation circuit that generates the reception clock signal for receiving serial data from a transmission destination, 2. The serial data communication device according to claim 1, further comprising a transmission / reception switching circuit for selecting one of a reception clock signal and serial data from the transmission control circuit in response to the transmission mode signal and outputting the selected signal to the data output transmission line. . 3. The transmission control means determines which of the transmission requests input from both the master-side circuit unit and the slave-side circuit unit is to be accepted, and sets a transmission mode in each circuit unit. 3. The serial data communication device according to claim 2, further comprising adjusting means for setting the reception mode. 4. A transmission operation from the master-side circuit unit and a transmission operation from the slave-side circuit unit when the transmission request is made from both the master-side circuit unit and the slave-side circuit unit. 3. The serial device according to claim 2, further comprising a continuous operation control unit for forcibly inserting a transmission period of the slave side circuit unit immediately after the transmission of the master side circuit unit so as to limit the continuous transmission operation of the master side circuit unit. Data communication device. 5. The transmission system according to claim 2, wherein at least one set of the transmission control means is provided on the transmission side and the reception side, and serial data is bidirectionally transmitted and received through two transmission lines using a dedicated line for unidirectional communication. Serial data communication device. 6. A timing in which the slave-side circuit unit arbitrarily delays a change timing of a reception clock signal sent from the slave-side circuit unit during data transmission of the master-side circuit unit in accordance with a state of the master-side circuit unit. 3. The serial data communication device according to claim 2, further comprising adjusting means. 7. A serial data communication method for transmitting and receiving bidirectional serial data via two transmission lines, comprising: a transmission FIFO buffer means for inputting a transmission request and parallel data from a central control unit;
A first receiving the parallel data from the O buffer means;
And a first means for converting the parallel data from the buffer means into serial data and shifting and outputting the serial data.
And a first clock extracting means for extracting a reception clock signal transmitted from the transmission destination in the transmission mode and outputting the extracted clock signal to the first shift register. Transmission control means for outputting, second shift register means for converting serial data received from the transmission destination via the data input transmission line into parallel data, and shifting and outputting the parallel data; and second shift register means for receiving parallel data output from the shift register means. And a second clock extracting means for branching and extracting a receiving clock transmitted to the destination in the receiving mode and extracting the same and outputting the same to the second shift register. Reception control means for outputting parallel data, and receiving the parallel data output from the reception control means. A reception FIFO buffer to be output to the central control unit, and output a transmission mode signal and a reception mode signal upon receiving the reception clock signal, the transmission completion signal, the reception completion signal, and the transmission request from the transmission destination, respectively. Arbitration means, a clock generation means for generating the reception clock signal for receiving serial data from a transmission destination, and transmitting one of the reception clock signal and the serial data from the transmission control means to the transmission mode signal. Transmission / reception switching means for selecting and outputting to the data output transmission line in response to the data transmission line, and a data output transmission line dedicated to one-way communication and a data input transmission line dedicated to one-way communication as the two transmission lines, respectively. ,
In response to the parallel data input from the central control unit, the transmission request is generated in the master side circuit unit, the master side circuit unit itself is set in the transmission mode, and the slave side circuit unit of the transmission destination is notified, and the transmission is performed. In response to the activation of the request, the reception clock signal is transmitted from the slave side circuit unit and received from the data input transmission line, and the data output transmission line is synchronized with the received reception clock signal. A serial data communication method comprising outputting serial data. 8. The arbitration means of the arbitration means of the master side circuit section maintains a wait state when there is no transmission request after reset and when the signal level of the data input transmission line is constant at a low logic level. When there is the transmission request in the wait state, the state transitions from the wait state to the transmission preparation period regardless of the signal level, and when the reception clock signal is received from the slave side circuit unit in response to the transmission request, Transition from the preparation period to the transmission mode to start transmission of the serial data, and when predetermined data transmission is completed, output the transmission completion signal and transition to the wait state, there is no transmission request, and the data When the signal level of the input transmission line is at a high level, a transition is made to the reception mode and the reception clock signal is transmitted. And starting serial data reception from the slave side circuit unit at the same time as starting transmission of the signal to the slave side circuit unit, and when the serial data reception is completed, generating the reception completion signal and transitioning to the wait state to wait. 8. The serial data communication method according to claim 7, wherein the transmission operation is prioritized by: 9. The arbitration by the arbitration means of the slave side circuit section is such that the wait state is maintained when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low level. And, when the signal level is high level, transition is made to the reception confirmation period, and during this reception confirmation period, the transmission of the reception clock signal to the master side circuit is started, and at the same time, the data is transmitted from the master side circuit. The reception is started, and when the data reception is completed, the reception completion signal is generated, the state is shifted to the wait state, and the standby state is maintained. In the wait state, the transmission request is issued, and the data input transmission line is When the signal level is constant at the low level, a transition is made from the wait state to the transmission preparation period, and during this transmission preparation period, 8. The receiving operation is prioritized by making a transition to the wait state when the signal level becomes high and making it wait, and when the signal level becomes constant to a low level during the transmission preparation period, making a transition to the transmission preparation period. Serial data communication method. 10. The arbitration means of the arbitration means of the master side circuit section maintains the wait state when the transmission request is not issued after reset and the signal level of the data input transmission line is constant at a low level. When there is the transmission request, the transition from the wait state to the transmission preparation period is performed, and when the reception clock signal is received from the slave side circuit unit in response to the transmission request, the transition from the preparation period to the transmission mode is performed. Then, the transmission of the serial data is started, and when the predetermined data transmission is completed, the transmission completion signal is output and the state is shifted to the reception confirmation state. In this state, if the signal level is constant at the low level, the wait state is set. To the receiving mode if the signal level is high. At the same time as starting to transmit a signal to the slave side circuit unit, serial data reception is started from the slave side circuit unit, and when the data reception is completed, the reception completion signal is generated, the state is shifted to the wait state, and the wait state is set. When there is no transmission request and the data input signal is at the high level, the mode is immediately shifted to the reception mode, and when there is a transmission request from both the master side circuit unit and the slave side circuit unit, the master side circuit is 8. The serial data communication method according to claim 7, wherein the slave-side circuit section is forcibly transmitted immediately after the transmission operation of the section. 11. The master-side circuit unit is provided with a plurality of the transmission preparation periods and the reception confirmation periods, and when both the master-side circuit unit and the slave-side circuit unit receive a transmission request, mutual timing adjustment is performed. 11. The serial data communication method according to claim 10, wherein: 12. Arbitration by the arbitration means of the slave side circuit unit is such that the wait state is maintained when there is no transmission request after reset and the signal level of the data input transmission line is constant at a low level. When the signal level is at a high level and the transition from the wait state to the reception confirmation period, the reception clock signal is transmitted to the master side circuit unit, and the transition from the reception confirmation period to the reception mode is performed. When the reception of serial data is started and the predetermined data reception is completed, if there is no transmission request, the state immediately transitions to the wait state, and if there is the transmission request, a reception completion signal is output and the state transits to the transmission preparation period. In this state, if the signal level is high, the state is changed to the wait state,
If the signal level is low, the mode is shifted to the transmission mode, the reception clock signal is started to be received from the master side circuit unit, and at the same time, the serial data transmission is started to the master side circuit unit. When the transmission is completed, the transmission completion signal is generated, the state is shifted to the wait state, and the apparatus waits.When there is no transmission request, and when the data input signal is at a constant low level, the state immediately transitions to the transmission preparation period, 8. When a transmission request is issued from both the master side circuit section and the slave side circuit section, the slave side circuit section is forcibly transmitted immediately after the reception operation of the master side circuit section.
The serial data communication method described. 13. The slave circuit section is provided with a plurality of transmission preparation periods and a plurality of reception confirmation periods, respectively, so that when there is a transmission request from both the master circuit section and the slave circuit section, mutual timing adjustment is performed. The serial data communication method according to claim 11, wherein 14. The slave-side circuit section arbitrarily delays a change timing of the reception clock signal sent from the slave-side circuit section at the time of data transmission of the master-side circuit section in accordance with the state of the master-side circuit section. Claim 1
13. The serial data communication method according to claim 11, wherein