JP2000138616A - Matched filter and lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide 3 matched filter and a LSI therefor where the power consumption is reduced and a spread coefficient can be varied with a simple and small-scale configuration. SOLUTION: In the matched filter, each sample-and-hold circuit of each basic correlator block 10 holds the result of multiplication between a PN code and a CDMA-modulated analog signal that is outputted from a differential amplifier 60 and multipliers 2 in timings shifted by one chip each, an addition control circuit 12 opens a switch on summing signal lines placed directly after the sample-and-hold circuit corresponding to a designated spread coefficient, and an adder 4 accumulates the results of multiplication that are received via the summing signal lines in the timing of summing and are held by the sample- and-hold circuits not disconnected by the switch to provide an output of a correlation signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matched filter and an LSI used on the receiver side of a spread spectrum communication system in mobile communication, wireless LAN and the like.
In particular, the present invention relates to a matched filter and an LSI corresponding to a long code CDMA system and capable of following a change in a spreading factor.

[0002]

2. Description of the Related Art In general, spread spectrum (SpreadSpct)
rum: SS) In a communication system, narrow-band modulation (primary modulation) and spread modulation (secondary modulation) are performed on transmission data on the transmission side.
Is performed, the data is transmitted, and the receiving side performs despreading on the received data to return to the primary modulation signal, and then reproduces the baseband signal using a normal detection circuit. It has become.

[0003] Conventionally, a despreading circuit for a received signal that has been spread spectrum performs synchronization acquisition,
A sliding correlator made up of a logic circuit has been used to take a correlation with a synchronous phase detected by synchronous acquisition.

The sliding correlator shifts a code sequence (local code sequence) generated on the receiving side by one bit using a 1-bit correlator, and obtains a correlation with the received code sequence every time. If a correlation is obtained for only the number of bits having a length, a synchronization phase at which the correlation reaches a peak is obtained, and synchronization acquisition can be achieved.

Here, a sliding correlator, which is one of the conventional despreading circuits, will be described with reference to FIG. FIG. 11 is a configuration block diagram of a part of a conventional sliding correlator. The correlation output acquisition part of the conventional sliding correlator is composed of an AD converter 1, a multiplier 2 ', a PN code register 3', and an adder 4 '.

A / D converter (analog / digital converter)
1 is a code division multiplex (CodeDivisionMultipleAccess: C)
DMA) converts an analog signal transmitted after being modulated and received by an antenna (not shown) into a digital signal with high precision.

[0007] The PN code register 3 'has a CD
The same spreading code used for MA modulation, PN (Ps
eudoRandomNoise) code.

The multiplier 2 'multiplies the digital reception data input from the AD converter 1 by the PN code input from the PN code register 3' and outputs the result as a multiplication result.

The adder 4 'outputs an integrated value obtained by cumulatively adding the multiplication result input from the multiplier 2' for one symbol period as a correlation output. Here, in order to accumulate the multiplication results, the output from the adder 4 'is fed back and delayed by one bit by a delay unit or the like (not shown) and input to the adder 4'. , Is added to the output from the multiplier 2 'by the adder 4' to perform cumulative addition.

The operation of the conventional sliding correlator is such that the analog signal of the received data received by the antenna is converted into a digital signal by the AD converter 1, and the PN code output from the PN code register 3 'and the digital signal are converted. , A multiplier 2 ', and an adder 4' accumulates the result of the multiplication to obtain an addition result for one symbol, and outputs the result as a correlation signal. The multiplication and the cumulative addition are repeated while changing the phase by shifting the timing of the multiplication in the multiplier 2 'by 1 bit, and the synchronous phase at which the correlation output reaches a peak is detected.

The configuration using a sliding correlator as this despreading circuit is relatively simple, has a small number of gates and consumes little power, but has a high-precision analog / digital converter (A) for converting a received analog signal into a digital signal.
This requires the D converter 1), which causes an increase in overall power consumption. In addition, the time required for cumulative addition for one symbol × 1 before a correlation output is obtained.
There is a problem that it takes time for the number of chips (spreading factor) in a symbol.

Therefore, as a method for solving the problem relating to time, a matched filter (Matched Filter: M) is used.
F, a matched filter). The matched filter achieves synchronous acquisition within one symbol time by simultaneously obtaining correlations when the phases are shifted.

That is, a general matched filter is:
For example, the above-described sliding correlators are provided by the number of chips, and multiplication and accumulation are performed at timings shifted by one chip at a time, thereby simultaneously obtaining correlations when the phases are shifted. In case 1
The number of gates is required to be as many as the number of chips in a symbol, which increases the gate size and power consumption.
It is difficult to use it for equipment whose power consumption should be suppressed.

As a countermeasure, a matched filter that directly demodulates an analog signal without using an analog / digital filter has been proposed in Japanese Unexamined Patent Publication No. Hei 9-46231 “matched filter circuit”.

Here, a matched filter which is another example of the conventional despreading circuit will be described with reference to FIG. FIG. 12 is a block diagram showing a configuration example of a conventional matched filter. The conventional matched filter receives a PN code register 3 that outputs a PN code, which is a spreading code, and an analog signal that has been sequentially CDMA-modulated, and receives a plurality of sample / hold circuits (S / H) that hold the analog signal. ) 5 'and the PN from the PN code register 3 with respect to the potential held by each sample and hold circuit 5'.
It comprises a multiplier 2 "for multiplying a code, and an adder 4" for simultaneously adding outputs from the multiplier 2 ".

Incidentally, in the proposal of Japanese Patent Application Laid-Open No. 9-46231,
For the purpose of reducing power consumption, a so-called neuro operational amplifier is used in a sample and hold circuit. Regarding the neuro operational amplifier, in addition to the proposal in Japanese Patent Application Laid-Open No. 6-45839, "Operational Amplifier", the '97 ISSC
C DigestofTechnicalPaperTP6.5Page100 also describes.

[0017]

However, in the conventional digital sliding correlator, there is a problem that the power consumption of the AD converter 1 is large and it takes a long time to obtain a correlation output.

The power consumption of the conventional analog matched filter proposed in Japanese Patent Application Laid-Open No. 9-46231 is about one tenth of that of the digital system, but it uses a neuro operational amplifier. In addition, there is a problem that an offset voltage is generated due to residual charges in the inverter itself, the capacitance, and the like constituting the inverter, an offset error between a large number of amplifiers is large, and output accuracy is deteriorated.

In order to eliminate such residual charges, it is necessary to periodically perform a so-called refresh for short-circuiting the capacitance portion. At the time of this refresh, the operation must be stopped. It is necessary to form extra elements to be executed, and it is necessary to provide a control circuit for controlling the refresh time.
The circuit becomes complicated, and there are problems in performance and manufacturing.

In order to solve these problems, the CDMA-modulated analog input signal is multiplied by the PN code and held, and the holding result for one symbol is added to obtain a correlation output. By obtaining the correlation output for one symbol while shifting the multiplication timing and detecting the correlation peak, a simple and small-scale configuration using only a single amplifier, a plurality of switches, and a capacitance having a simple configuration is possible. , A sliding correlator and a matched filter that can further reduce power consumption are conceivable,
In the sliding correlator and the matched filter, when the long code CDMA is supported, sufficient consideration is not given to the change in the spreading factor.

The present invention has been made in view of the above-mentioned circumstances, and provides a matched filter and an LSI having a simple and small configuration, which can further reduce power consumption and can cope with a change in spreading factor. It is an object.

[0022]

According to a first aspect of the present invention, there is provided a matched filter which receives an input of a CDMA-modulated analog signal and designates the analog signal as the analog signal. Multiplying means for respectively multiplying by the number of PN codes corresponding to the selected spreading factor and outputting the result as a multiplication result, and sample-and-hold circuits corresponding to the maximum spreading factor among a plurality of specifiable spreading factors. , Each of the sample-and-hold circuits receives a capture signal representing the timing of capturing the multiplication result, captures and holds the corresponding multiplication result among the multiplication results output by the multiplication means, and indicates the addition timing. A basic correlator block for receiving the addition instruction signal and outputting the held signal is provided in a number corresponding to the maximum spreading factor. A matrix sample-hold circuit in which the sample-hold circuits forming the correlator block are arranged in the row direction, the basic correlator blocks are arranged in the column direction, and a basic correlator block is sequentially arranged from the matrix sample-hold circuit for each chip timing. A switch control circuit for addition, which outputs an addition instruction signal to a sample-and-hold circuit forming the selected basic correlator block, and a chip timing,
A sample-and-hold circuit in the m-th row and the n-th column which constitutes the matrix sample-and-hold circuit, wherein a remainder obtained by dividing an elapsed chip time by the designated spreading factor is m + n-
A sample and hold switch control circuit for outputting a capture signal for capturing and holding a multiplication result output by the multiplier corresponding to the row for a sample and hold circuit corresponding to 1; And an adder for receiving, from the hold circuit, the signals held from the number of sample / hold circuits corresponding to the designated spreading factor, adding the signals, and outputting the sum as a correlation output. The feature is that the diffusion rate can be changed.

According to a second aspect of the present invention, there is provided a matched filter comprising:
A plurality of multiplying means for receiving the input of the A-modulated analog signal, multiplying the analog signal by a number of PN codes corresponding to a designated spreading factor, and outputting the result as a multiplication result; The number of sample-and-hold circuits is set as a set, and the basic correlator blocks arranged in the column direction by the number corresponding to the maximum spreading rate among a plurality of spreading rates that can specify the set correspond to the maximum spreading rate. A matrix sample-and-hold circuit arranged in the number of rows in a row direction, wherein each of the sample-and-hold circuits receives an input of a capture signal indicating a timing of capturing a multiplication result, and outputs the multiplication result output by the multiplication means. Of these, the corresponding multiplication result is captured and held, and upon receiving an addition instruction signal indicating the timing of addition, the held signal is output. A matrix sample-and-hold circuit, which is a sample-and-hold circuit, and a basic correlator block sequentially selected from the matrix sample-and-hold circuit for each chip timing, and an addition instruction signal is sent to the sample-and-hold circuit forming the selected basic correlator block. Out of a set of a sample-and-hold circuit constituting the matrix sample-and-hold circuit, for each oversampling timing obtained by dividing the chip timing by the number of oversamplings. A plurality of columns having the same remainder when the sum of the number of columns of the basic correlator block to which the set belongs and the number of rows where the set is arranged in the basic correlator block is divided by the designated spreading factor is the same. Said oversampler belonging to a set A sample and hold switch control circuit for simultaneously outputting a capture signal for capturing and holding a multiplication result output by the multiplication means corresponding to each sample and hold circuit for a sample and hold circuit corresponding to the timing of the sampling; Receiving, from the sample-and-hold circuits constituting the basic correlator block, the signals held by the number of sample-and-hold circuits corresponding to the designated spreading factor, adding the signals, and outputting the correlation output; And an adder that outputs the data as an output signal. Thus, oversampling can be realized, and the spreading factor can be changed.

According to a third aspect of the present invention, there is provided a matched filter, comprising:
Multiplying means for receiving an input of the A-modulated analog signal, multiplying the analog signal by a PN code corresponding to a designated spreading factor, and outputting the result as a multiplication result; Comprises a number of sample-and-hold circuits corresponding to the maximum spreading factor, and among the sample-and-hold circuits, an x-th sample-and-hold circuit receives an input of a capture signal representing a timing of capturing a multiplication result, Of the multiplication results output by the multiplication means, the multiplication result with the PN code of the number of chips corresponding to the remainder obtained by dividing x by the designated spreading factor is captured and held, and the input of the addition instruction signal indicating the timing of addition is input. The number of basic correlator blocks for receiving and holding the output signals is provided by the number corresponding to the maximum spreading factor, and constitutes the basic correlator block. A matrix sample-hold circuit in which the sample-hold circuits are arranged in the row direction and the basic correlator blocks in the column direction; and a chip sample-hold-based basic correlator block forming the matrix sample-hold circuit. An addition switch control circuit that outputs an addition instruction signal to the sample and hold circuit of the basic correlator block; and a sample and hold circuit of the m-th row and the n-th column that forms a matrix sample-and-hold circuit for each chip timing. The remainder of dividing the chip time by the specified spread rate,
a sample and hold switch control circuit that outputs a capture signal for capturing and holding a multiplication result output from a multiplier corresponding to the row for a sample and hold circuit corresponding to m + n−1; and forming the basic correlator block. An adder for receiving, from the sample and hold circuits, the signals held by the number of sample and hold circuits corresponding to the designated spreading factor, adding the signals, and outputting the sum as a correlation output; And the signal-to-noise ratio (S / N) of the correlation output can be improved.

According to a fourth aspect of the present invention, there is provided a matched filter, comprising:
Multiplying means for receiving an input of the A-modulated analog signal, multiplying the analog signal by a PN code corresponding to a designated spreading factor, and outputting the result as a multiplication result; The number of sample-and-hold circuits corresponding to the number of oversamplings is set as a set, and the set is provided with the number corresponding to the maximum spreading factor. Each of the sample-and-hold circuits belonging thereto receives an input of a capture signal indicating the timing of capturing the result of the multiplication, and among the multiplication results output by the multiplication means, the number of chips corresponding to the remainder obtained by dividing x by the specified spreading factor. The multiplication result with the PN code is taken and held, and upon receiving the addition instruction signal indicating the timing of addition, the held signal is output. A matrix sample-hold circuit comprising a number of basic correlator blocks corresponding to the maximum spreading factor, a set of sample-hold circuits forming the basic correlator block arranged in a row direction, and the basic correlator blocks arranged in a column direction. An addition switch control circuit for outputting an addition instruction signal to the sample and hold circuit of the basic correlator block for the basic correlator block forming the matrix sample and hold circuit for each chip timing, and oversampling the chip timing For each oversampling timing obtained by dividing the frequency by several minutes, a set of sample and hold circuits constituting the matrix sample and hold circuit, wherein the number of rows where the set is arranged and the set are Basic correlator to which it belongs The sample and hold circuit corresponding to the oversampling timing belongs to a set of a plurality of sample and hold circuits having the same remainder after dividing the sum of the number of lock columns by the designated spreading factor. A sample and hold switch control circuit that simultaneously captures and holds a multiplication result output by the multiplication means corresponding to each of a plurality of sample and hold circuits, and a sample and hold circuit that forms the basic correlator block; And an adder that receives an input of the held signal from the number of sample and hold circuits corresponding to the designated spreading factor, accumulates the signal, and outputs the accumulated signal as a correlation output. , Can handle oversampling, and take sufficient time for addition, Can be held without receiving

According to a fifth aspect of the present invention, there is provided a matched filter according to the first or second aspect, wherein the first row of a basic correlator block forming a matrix sample and hold circuit is provided. Includes two sample and hold circuits, a first sample and hold circuit portion and the second sample and hold circuit portion, and receives the addition instruction signal and receives the first sample and hold circuit portion. Of the sample-and-hold circuit portion and the second sample-and-hold circuit portion are switched and selected, and the multiplication result output from the multiplier corresponding to the selected sample-and-hold circuit portion is held. Time-division operation sample-and-hold circuit that outputs the multiplication result held by the sample-and-hold circuit part that is not performing And characterized in that there, while keeping a sufficient time for the addition can be maintained without leaking the multiplication result.

[0027] The invention according to claim 6 for solving the problems of the above-mentioned conventional example is described in claim 1 or claim 2 or claim 5.
In the matched filter described above, the sample-and-hold circuits forming the basic correlator blocks share one addition signal line, and when the sample-and-hold circuit receives an addition instruction signal as a signal for instructing addition, the sample-and-hold circuit shares the signal. A sample-and-hold circuit for outputting an addition result held in an addition signal line, wherein a switch is provided immediately after the sample-and-hold circuit corresponding to a plurality of configurable spreading factors of the addition signal line, and a switch is provided. The present invention is characterized in that it has an addition control circuit for opening the switch immediately after the sample and hold circuit corresponding to the spread rate, and the spread rate can be changed with a simple and small-scale configuration.

According to a seventh aspect of the present invention, there is provided a matched filter according to the third or fourth aspect, wherein the first row of a basic correlator block forming a matrix sample and hold circuit is provided. And a sample-and-hold circuit immediately after the sample-and-hold circuit corresponding to a plurality of specifiable spreading factors are a first sample-and-hold circuit part and a second sample-and-hold circuit.
And two sample-and-hold circuits, and when receiving an addition instruction signal, receives one of the first sample-and-hold circuit and the second sample-and-hold circuit Time-divisional operation sample that switches and selects and holds the multiplication result output by the multiplier corresponding to the selected sample-hold circuit part and outputs the multiplication result held by the unselected sample-hold circuit part -It is characterized by being a hold circuit, and has an effect that it can hold a multiplication result without giving a sufficient time for addition.

The invention according to claim 8 for solving the problem of the above-mentioned conventional example is described in claim 1 or claim 2 or claim 3.
Alternatively, in the matched filter according to claim 4, claim 5, claim 6, or claim 7, the multiplying means is CDMA.
A differential amplifier that receives the input of the converted analog signal, outputs the signal as it is as a positive-phase signal, converts the signal to a negative phase around a preset DC voltage value, and outputs the negative-phase signal, A multiplication unit having a multiplier that selects and outputs one of a positive-phase signal and a negative-phase signal output from the differential amplifier according to a corresponding PN code, and is small and simple. With such a configuration, there is an effect that a multiplication unit can be realized, and power consumption can be reduced.

According to a ninth aspect of the present invention for solving the above-mentioned problems of the conventional example, there is provided a first or second or third aspect of the present invention.
Alternatively, in the matched filter according to claim 4, claim 5, claim 6, or claim 7, the multiplying means is CDMA.
AD that converts the modulated analog signal into a 1-bit digital signal and outputs the signal as a voltage signal representing the bit
The multiplication means has a converter and a multiplier which is a switch for selectively taking in the voltage signal in accordance with the PN code. The multiplication means can be realized with a small and simple configuration. Yes, power consumption can be reduced.

The invention described in claim 10 for solving the problems of the above-mentioned conventional example is provided in claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7.
In the matched filter as described above, the multiplying means is a CDM
Multiplication means having a staircase wave circuit for converting an A-modulated analog signal into a staircase signal which changes according to the magnitude thereof, and a multiplier which is a switch for selectively taking in the voltage signal according to a PN code This has the effect of realizing a multiplication means with a small and simple configuration, and can reduce power consumption.

An eleventh aspect of the present invention for solving the above-mentioned problems of the conventional example is claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7.
In the matched filter as described above, the multiplying means is a CDM.
An inverter circuit for inverting the A-modulated analog signal and outputting the inverted signal as a reverse-phase signal;
A multiplier which has a switch which selectively takes in the MA-modulated analog signal as it is as a positive-phase signal or as a negative-phase signal output from the inverter circuit. With such a configuration, there is an effect that a multiplication unit can be realized, and power consumption can be reduced.

The invention according to claim 12 for solving the problem of the above-mentioned conventional example is provided in claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7.
Or claim 8 or claim 9 or claim 10 or claim 1
The matched filter according to 1, wherein the plurality of specifiable spreading factors are 2 to the power of a positive integer,
A matched filter suitable for general CDMA communication can be provided. In particular, in the matched filter according to the second aspect, a multiplication result of the number of symbols which is an integral multiple of 2 of a designated spreading factor can always be held. Therefore, the utilization efficiency of the sample and hold circuit can be improved.

According to a thirteenth aspect of the present invention, there is provided an LSI having the matched filter according to the first to twelfth aspects, wherein a matrix sample-and-hold circuit is provided. By arranging the constituent sample-hold circuits in a grid pattern, the layout pattern of the DRAM can be diverted, and the capacitance holding the multiplication result in each sample-hold circuit is not equal. Since the absolute size is not limited, it can be easily manufactured, and the parasitic capacitance in the sample-and-hold circuit has a high degree of freedom.
Can be easily implemented.

[0035]

Embodiments of the present invention will be described with reference to the drawings. Hereinafter, the present invention will be described by dividing it into first and second embodiments. In the matched filter according to the first embodiment of the present invention, the sample-and-hold circuits are arranged in rows and columns corresponding to the largest spreading factor and columns corresponding to the largest spreading factor in a matrix direction.
A switch is provided immediately after the row corresponding to the specifiable spreading factor for the signal line that transmits the signal held by each sample and hold circuit at the time of addition, and is separated from the sample and hold circuit of the subsequent row. There is a simple, small-scale configuration that can change the spreading factor while further reducing power consumption.

First, a schematic configuration of the matched filter according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic configuration block diagram of a first matched filter of the present invention, and FIGS. 2 to 6 are schematic configuration block diagrams of a part of the first matched filter of the present invention.

The first matched filter according to the present invention is shown in FIG.
As shown in the figure, a differential amplifier 60, a plurality of multipliers 2-1 to 2-n provided corresponding to the maximum spreading factor, a PN code register 3, an adder 4, a clock generator 11 An addition control circuit 12, a matrix sample and hold circuit 50, a sample and hold switch control circuit 51,
Upon receiving an instruction to change the spreading factor from the clock generator 11, a signal designating the changed spreading factor is output to the PN code register 3, the addition control circuit 12, and the sample and hold switch control circuit 51. And a spreading rate control circuit 15 which performs the control.

The differential amplifier 60 realizes an amplifier (positive-phase / negative-phase generating amplifier) for generating a positive-phase signal and a negative-phase signal. The differential amplifier 60 takes in a received CDMA-modulated analog signal and inputs it. It generates and outputs a normal phase signal and a negative phase signal related to an analog signal. Specifically, the differential amplifier 60 receives an input of the received CDMA modulated analog input signal and a voltage signal (DC level voltage: DC voltage) corresponding to the DC level of the received analog input signal, and The output analog signal is output as a normal phase signal as it is, and the normal phase signal is turned back on the basis of the DC voltage level and output as a negative phase signal.

That is, for example, when the DC voltage level is 1.5
V, if the potential of the input analog signal (potential of the positive-phase signal) is 2.5 V (potential higher by 1 V than 1.5 V), the opposite phase signal is 0.5 V (more than 1.5 V). 1V
(Low potential), and when the potential of the analog signal is 0.5 V, 2.5 V is output as a reverse phase signal.

Here, the level of the DC voltage may be the center potential level of the analog signal (approximately the center voltage between the maximum value and the minimum value of the analog signal). Since the differential amplifier 60 is not intended for amplification, the gain is 1
Since it is not necessary to set the value to exactly 1, there is an advantage that the manufacturing is easy and the control is easy.

A plurality of multipliers 2 are provided corresponding to the maximum spreading factor. As shown in FIG. 2, the multiplier 2 receives a signal from a differential amplifier 60 in accordance with a PN code input from a PN code register 3 described later. It is a switch for selecting either a positive-phase signal or a negative-phase signal from the input signals. That is, the switches of the multipliers 2-1 to 2-n corresponding to the respective chips are normally in an open state, and each time a PN code is input from the PN code register 3, the switches are changed according to the value of the PN code. A circuit for selecting either the normal-phase signal or the negative-phase signal input from the amplifier 60 and outputting the selected signal to the sample / hold circuit 5 (shown in FIG. 4) in the corresponding row of the matrix sample / hold circuit 50 described later Is

That is, for example, if the PN code is "1", the switch of each multiplier 2 selects and outputs the positive-phase signal input from the differential amplifier 60, and the PN code is "0".
In this case, the switches of the multipliers 2 are configured to select and output the reverse-phase signal input from the differential amplifier 60. Thus, the multiplier 2 realizes multiplication of the analog input signal and the PN code. Here,
Since the multipliers 2 are provided by the number corresponding to the maximum spreading factor, if the PN code is the same, once the switch of the multiplier 2 is set in accordance with the PN code, the differential amplifier is fixed. 60 may be connected to the positive or negative phase side. In this way, since the control of the switch of the multiplier 2 is not required while the PN code does not change, the power consumption can be reduced.

As described above, the differential amplifier 60 and the multiplier 2 multiply the input CDMA-modulated analog signal by the corresponding PN code (hereinafter referred to as “multiplication means” in the claims and in the claims). ), But as will be described later, such multiplication means can be embodied in other ways.

The PN code register 3 stores the CDM on the transmitting side.
A PN code used as a spread code of A modulation is generated and stored. The PN code corresponding to each chip is stored in accordance with a clock signal indicating a chip timing, which is input from a clock generation circuit 11 described later. Is output to the corresponding multiplier 2.

The PN code register 3 receives a signal designating the spreading factor from the spreading factor control circuit 15 and
In accordance with the signal, a plurality of types of PN codes are generated and output. Specifically, when the designated spreading factor is 128, the first PN code consisting of 128 codes is output. When the designated spreading factor is 64, the first PN code is output from 64 codes. Becomes the second P
An N code is output.

That is, if the PN code is "100...", The PN code register 3 stores the first code "1".
The PN code of “1” is output to the multiplier 2-1 corresponding to, and the multiplier 2-2 corresponding to the next code “0” is output to the multiplier 2-1.
It outputs a PN code of “0”.

Matrix sample / hold circuit 50
As shown in FIG. 3, the sample-and-hold circuits 5 are arranged in a matrix in a matrix direction by the maximum spreading factor × the maximum spreading factor, as shown in FIG. That is, the matrix sample
As shown in FIG. 3, each column of the hold circuit 50 constitutes a basic correlator block 10 including a plurality of sample / hold circuits 5-1 to 5-n provided corresponding to the maximum spreading factor. .

The basic correlator block 10 is a unit in which the number of sample-and-hold circuits 5 corresponding to the maximum spreading factor are collected, and holds a multiplication result for one symbol starting from a specific phase (chip timing). The output is performed at the timing of addition.
In the figure, each column of the sample-and-hold circuit 5 forming the matrix sample-and-hold circuit 50 is illustrated so as to correspond to one basic correlator block 10.

Each of these sample and hold circuits 5 includes:
As shown in FIG. 4, a plurality of signal lines (hereinafter, referred to as “captured signal lines”) for transmitting a signal representing a signal holding timing (hereinafter, referred to as “captured signal”), and each basic correlator block 10 And a signal line (hereinafter, referred to as an "addition signal line") for transmitting the held signal to the adder 4 and the held signal provided for each basic correlator block 10 to the addition signal line. A signal line (hereinafter, referred to as an “addition instruction signal line”) that transmits a signal indicating the output timing (hereinafter, referred to as an “addition instruction signal”) is connected to each of the signal lines. Here, FIG.
Of the matrix sample and hold circuit 50 of FIG.
FIG. 3 is an enlarged view of a sample-and-hold circuit 5-4 in the fourth row and a sample-and-hold circuit 5-5 in the fifth row of one basic correlator block 10. In practice, the addition is performed on the addition signal line by the operation of the addition switch 57. Therefore, the illustrated adder 4 may be a simple buffer amplifier.

Here, the number of fetched signal lines is provided corresponding to the number of each sample-and-hold circuit 5 of the basic correlator block 10 in the first column, that is, by the number of spreading factors. 10 samples
They are connected to the hold circuit with a shift by one row.

That is, the capture signal line connected to the sample-and-hold circuit 5-2 in the second row and the first column is connected to the sample-and-hold circuit 5-1 in the next first row and the second column. . The capture signal line connected to the sample and hold circuit 5-1 in the first row and the second column is also connected to the sample and hold circuit 5 in the third row and the last row, and further from the fourth and subsequent columns. Each sample-and-hold circuit 5 of the basic correlator block 10 is connected so as to be shifted by one row.

Therefore, in a sample / sample whose sum when the sum of the number of rows and the number of columns is divided by the designated spreading factor is the same.
The hold circuit 5 receives an input of a capture signal at the same time. To be more specific, if the specified spreading factor is k, the sample-and-hold circuit 5 in the m-th row and the n-th column captures the data at the timing of the chip time mod (m + n-1, k). A signal is input. Here, mod (a, b) represents the remainder when a is divided by b.

The addition signal line and the addition instruction signal line are
Each basic correlator block 10 is connected to the sample-and-hold circuit 5 constituting the basic correlator block 10. Therefore, the addition in the adder 4 is performed for each basic correlator block 10 as described later.

Further, a sample and hold circuit 5 having a number of rows corresponding to a specifiable spreading factor is provided on the addition signal line,
A switch 52 is provided between the next row and the sample / hold circuit 5. Specifically, when the maximum spreading factor is 16 and the specifiable spreading factors are 4, 8, and 16, as shown in FIG. 3 and FIG. The switches 52 are provided between the sample and hold circuits 5 on the fifth and fifth rows and between the sample and hold circuits 5 on the eighth and ninth rows.

Basically, each sample-and-hold circuit 5 holds the multiplication result output from the corresponding multiplier 2 when receiving the input of the capture signal from the capture signal line, and outputs the addition instruction signal from the addition instruction signal line. Is received, the held multiplication result is output to the addition signal line.
Specifically, for example, the sample and hold circuit 5-n on the n-th row of each basic correlator block 10 holds the multiplication result output from the corresponding multiplier 2-n.
A more detailed description of the sample and hold circuit 5 will be described later.

Note that the first of the basic correlator blocks 10
It is conceivable that the sample-and-hold circuit 5-1 in the row switches the two sample-and-hold circuits for each addition and operates in a time-division manner, as described later. Hereinafter, the sample / hold circuit 5-1 is referred to as a "time-division operation sample / hold circuit".

This is because the matched filter has to take in the signals one after another, so that the time for addition cannot be secured. As a countermeasure, two sample-and-hold circuits are prepared, and each of them is switched and used to perform addition. This is because the result of the multiplication can be captured even during the operation.

Here, each sample and hold circuit 5 will be described in more detail with reference to FIGS. 5 (a) and 5 (b). As described above, the sample-and-hold circuit 5 includes the sample-and-hold circuit 5 that does not perform the time-division operation.
And a sample-and-hold circuit 5 (time-division sample-and-hold circuit 5) that operates in a time-division manner.

First, as shown in FIG. 5A, the sample-and-hold circuits 5-2 to 5-n which do not perform the time-division operation are connected to the sample-and-hold switch 55 and the information holding capacitance 5 as shown in FIG.
6 and an addition switch 57. The sample and hold switch 55 is normally open (off)
In the state shown in FIG. 2, the signal is turned on in response to the input of a capture signal indicating the timing of capturing data input from the sample-and-hold switch control circuit 51 described later,
The signal input from the corresponding multiplier 2 is transmitted to the information holding capacitance 56.

The information holding capacitance 56 is a capacitor having one end connected to the terminals of the sample / hold switch 55 and the addition switch 57 and the other end grounded.
The signal transmitted when the sample and hold switch 55 is turned on is held, and when the addition switch 57 is turned on, the held signal is output to the addition signal line via the addition switch 57. Is what you do.

The addition switch 57 is normally open (off), and receives an addition instruction signal for performing addition via an addition instruction signal line from an addition switch control circuit 13 described later. Then, the signal input from the information holding capacitance 56 is transmitted to the adder 4.

That is, the sample / hold circuits 5-2 to 5-2
5-n receives the input of the capture signal from the sample-and-hold switch control circuit 55, holds the signal input from the corresponding multiplier 2 at that time, and later outputs the addition instruction signal from the addition switch control circuit 13 Upon receiving an input, the held signal is output to an addition signal line.

On the other hand, the time-division operation sample-and-hold circuit 5-1 includes a first sample-and-hold circuit portion including a sample-and-hold switch 55a, an information-holding capacitance 56a, and an addition switch 57a; A second sample / hold circuit portion including a hold switch 55b, an information holding capacitance 56b, and an addition switch 57b; and a selection switch 58. Here, the sample and hold switches 55a and 55b, the information holding capacitances 56a and 56b, and the addition switches 57a and 57b are respectively the same as those of the sample and hold circuits 5-2 to 5-n described above. Therefore, the description is omitted.

The selection switch 58 selects one of the sample-and-hold circuit portions, transmits a take-in signal to the sample-and-hold switch 55 of the selected sample-and-hold circuit portion, and transmits the signal to the sample-and-hold switch 55 that is not selected. The capture signal is not transmitted to the sample-and-hold switch 55 of the sample-and-hold circuit portion, and the addition instruction signal is similarly transmitted to the addition switch 57 of the non-selected sample-and-hold circuit portion. The addition instruction signal is not transmitted to the addition switch 57 of the sample and hold circuit part. The selection switch 58 alternately switches the selected sample-and-hold circuit portion every time the addition instruction signal is input.

That is, in the time-division operation sample-and-hold circuit 5-1, initially, the selection switch 58 selects the first sample-and-hold circuit portion, and the first sample-and-hold circuit 5-1.
The multiplication result signal is held in the information holding capacitance 56a of the hold circuit portion, and when the addition instruction signal is input, the selection switch 58 selects and selects the second sample / hold circuit portion. Not the first
Addition switch 57a in the sample and hold circuit section
To the sample-and-hold switch 55b, and the information is held in the information-holding capacitance 56b of the second sample-and-hold circuit portion. That's what you get.

This time division operation sample / hold circuit 5
As will be described later, the function of -1 does not impair the result of the multiplication input at the timing of the addition. The operation of the time-division operation sample-and-hold circuit 5 is hereinafter referred to as “time-division operation”.

Here, the sample-and-hold switch 55, the addition switch 57, and the selection switch 58 of each sample-and-hold circuit 5 are described as general switches in the drawing. Uses a MOS transistor. For the specific configuration and operation of a switch using a MOS transistor, see "Electronic Circuits for Transistors and ICs I, Analog", Donald L. Schilling, et al. Publishing Co., 1991 14
Since there is a detailed description from the first page, the description here is omitted.

Sample / hold switch control circuit 51
Receives a signal specifying the spreading factor from the spreading factor control circuit 15, and when the specified spreading factor is k, the sample-and-hold circuit 5- in the n-th column of the m-th basic correlator block 10 In n, a capture signal is output at a timing (chip timing) of a chip time of mod (m + n-1, k).

More specifically, as shown in FIG. 6, the sample / hold switch control circuit 51 includes a sample / hold data fetch signal generation means 61 and a plurality of selection means 6.
2 and the capture signal lines T′1 to T′1 to Tx1 which are connected to the sample and hold circuits 5 in each row of the basic correlator block 10 in the first column (first column) of the matrix sample and hold circuit 50. It is conceivable that a capture signal is output via T'16 (see FIG. 3). In FIG. 6, for ease of explanation, the spreading factor is 16, and the specifiable spreading factors are 4, 8,
The case where the number is 16 is described as an example.

The data fetch signal generation means 61 responds to a clock signal input from the clock generator 11
It sequentially outputs a capture signal to the corresponding capture signal lines T1 to T16. Incidentally, the data capture signal generating means 61 sequentially outputs capture signals to the capture signal lines T1 to T4 when the spread factor is 4, for example, according to the designated spread factor. In some cases, a capture signal is sequentially output to the capture signal lines T1 to T8.

Here, the capture signal lines T1 to T4 are shown as being connected to the capture signal lines T'1 to T'4 going to the matrix sample and hold circuit 50 as they are. This is because there is no plan to operate at the spreading factor of one chip or one chip. That is, if 2
If it is necessary to operate at the spreading factor of the chip, T3
Also, T4 and T4 need not be directly connected to T'3 and T'4, but must be connected through a device having a function equivalent to the selection means 62 described later.

The selecting means 62 operates when the spreading factor is 4 chips and when the spreading factor is 8 chips, and more specifically, the selecting means 6 which operates when the spreading factor is 4 chips.
2-1 is provided with three switches 65-1 to 65-3 corresponding to the number obtained by subtracting 1 from the spreading factor.
At one end are a capture signal line T1 and a capture signal line T5.
Is connected to the other end, and a fetch signal line T'5 toward the matrix sample and hold circuit 50 is connected to the other end. When the spreading factor is 4, the switch 65-1 connects the capture signal line T1 to T'5. When the spread factor is 8 or 16, the switch 65-1 connects the capture signal line T1.
5 and T'5 are connected.

In other words, the i-th switch 65-i connects either the capture signal line Ti or Ti + 4 to the capture signal line T′i + toward the matrix sample and hold circuit 50 in accordance with the spreading factor. Connect to 4.

Similarly, the selecting means 62-2 operating when the spreading factor is 8 chips is provided with seven switches 66-1 to 66-7 corresponding to the number obtained by subtracting 1 from the spreading factor. The switch 66-i connects one of the capture signal line Ti and Ti + 8 to the capture signal line T'i + 8 toward the matrix sample and hold circuit 50 according to the spreading factor.

That is, when the spreading factor is 16 chips, the sample-and-hold switch control circuit 51 outputs the first row, the first column, the 16th row, the second column, and the like via the take-in signal lines T1 and T'1, for example. .., 15, 3,..., And transmits a capture signal to each sample and hold circuit 5 in the second row, 16 th column. T1 and T'1
Through the first row, first column, fourth row, second column, third row, third column,
The fetch signal is transmitted to each sample-and-hold circuit 5 in the fourth row.

As shown in FIG. 7, the addition control circuit 12
It has an addition switch control circuit 13 and a variable chip addition control circuit 14, and is input from a spreading factor control circuit 15.
The switch 52 on the addition signal line is controlled based on the signal supporting the spreading factor, and the sampled and held circuit 5 holding the multiplication result by the multiplier 2 is connected to the addition signal line. The sample-and-hold circuit 5, which outputs the signal and does not hold the result of the multiplication by the multiplier 2, does not output the signal to the addition signal line. FIG. 7 is a circuit diagram of a first matched filter addition control circuit of the present invention.

The addition switch control circuit 13 receives the input of the clock signal indicating the chip timing from the clock generator 11 and initially waits until the specified spreading factor is reached. The first correlator block 10 sequentially outputs an addition instruction signal via an addition instruction signal line.

When the spreading factor is 4, the variable chip addition control circuit 14 simultaneously opens (offs) the switches 52-1 immediately after the fourth row of each basic correlator block 10, and the spreading factor is 8 Or, in the case of 16, the switch 52
-1 are turned on all at once.

When the spreading factor is 8, the variable chip addition control circuit 14 determines whether the basic correlator block 10
The switches 52-2 immediately after the line are simultaneously opened (ON)
When the spreading factor is 16, the switches 52-2 are simultaneously turned off.

Therefore, when the spreading factor is 4, the switch 5 immediately after the fourth row of each basic correlator block 10
2-1 are simultaneously turned off, and the signals output from the sample and hold circuits 5 in the fifth to sixteenth rows of each basic correlator block 10 are not transmitted to the adder 4.

The adder 4 adds, for each basic correlator block 10, the signal output from the matrix sample-and-hold circuit 50, which has received an input via the addition signal line, and outputs each as a correlation output.

The clock generator 11 includes a PN code register 3, an addition switch control circuit 13 described later,
A clock signal indicating the timing of the chip is output to the sample / hold switch control circuit 51.
Further, when changing the spreading factor, the clock generator 11 outputs an instruction to change the spreading factor to the spreading factor control circuit 15.

Next, the operation of the first matched filter of the present invention will be described. In the following description, a case where the maximum spreading factor is 16 and the specifiable spreading factor is 4, 8, or 16 will be described as an example for simplicity. It is assumed that the selection switch 58 of the time-division operation sample-and-hold circuit 5-1 of each basic correlator block initially selects the first sample-and-hold circuit.

First, when the spreading factor is 16, the selection means 62-1 of the sample and hold switch control circuit 51
Switches 65-1 to 65-4 respectively set T5 to T8 and T'5 to
T'8 and switches 66-1 to 6-6 of the selection means 62-2.
6-8 connect T9 to T16 to T'9 to T'16, respectively. Further, the variable chip addition control circuit 14 of the addition control circuit 12 turns on the switches 52-1 and 52-2 on the addition signal line of each basic correlator block 10.

Then, the data fetch signal generation means 61 of the sample / hold switch control circuit 51 sequentially outputs fetch signals to the fetch signal lines T1 to T16 in accordance with the clock signal input from the clock generation circuit 11. Then, by the operation of the selection means 62, the contents of T1 to T16 are output to the matrix sample and hold circuit 50 as they are via T'1 to T'16. Therefore, at first, one row and one row are connected via T1 and T'1.
The capture signal is output to each sample-and-hold circuit 5 in the column, 16th row, 2nd column,..., 2nd row, 16th column.

On the other hand, at this time, the differential amplifier 60 outputs a positive-phase signal and a negative-phase signal based on the CDMA-modulated analog signal, and the multipliers 2-1 to 2-16 each output a PN code register. In accordance with the PN code input from 3, either the normal phase signal or the negative phase signal is selected and output to each sample / hold 5 in the corresponding row of the matrix sample / hold circuit 50 as a multiplication result.

As a result, the first PN code and the CDMA-modulated analog signal are multiplied in the first sample-hold circuit portion of the time-division operation sample-hold circuit 5-1 in the first row and first column. The signal is held, and the corresponding PN code and the CDMA-modulated analog signal are supplied to each sample-and-hold circuit 5 in the 16th row, the second column, the 15th row, the third column,. And the signal obtained by multiplying by is held.

Further, at the next timing, the second row, the first column, the first row, the second column, and the like are input via the capture signal lines T2 and T'2.
16th row, 3rd column,..., 3rd row, 16th column sample / hold circuit 5 (in the first row, 2nd column, time-division operation sample / hold circuit 5-1, the first sample / hold circuit portion ) Is output, and the result obtained by multiplying the CDMA-modulated analog signal input at the next timing by each corresponding PN code is obtained by the multipliers 2-1 to 2-16. 2nd row, 1st column, 1 row, 2
Column, 16th row, 3rd column,..., 3rd row, 16th column
The hold circuit 5 includes multipliers 2-1 to 2-1 corresponding to each row.
6 will hold the result of the multiplication output.

Thereafter, the same operation is performed, and after a lapse of 16 chip times, the sample-and-hold circuits 5 in the first to 16th rows of the basic correlator block 10 in the first column are used for 1 to 16 chip times. The result obtained by multiplying the CDMA-modulated analog signal at the timing by the corresponding 1st to 16th PN codes is held.

Here, the addition switch control circuit 13
In response to the input of a clock signal at a timing of 17 chip times from the clock generation circuit 11, an addition instruction signal is output to the sample-and-hold circuits 5 in the 1st to 16th rows of the basic correlator block 10 in the first column. At this time, the selection switch 58 of the time-division operation sample-and-hold circuit 5-1 in the first row and the first column selects the second sample-and-hold circuit, and the first sample-and-hold circuit holds. The output signal is output to the addition signal line, and the captured signal input at the same time (at a timing of 17 chip times) is input to the second sample based on the clock signal representing the same chip timing as the addition instruction signal. By outputting the result to the hold circuit portion, the result of the multiplication output from the multiplier 2-1 is similarly held at the timing of 17 chip times in the second sample / hold circuit portion.

On the other hand, the signals held by the sample and hold circuits 5-2 to 5-16 in the second and subsequent rows of the first column are simultaneously transmitted to the corresponding addition signal lines because the switch 52 is turned on. Therefore, the adder 4 adds the multiplication results for 16 chip times held in each sample / hold circuit 5 of the basic correlator block 10 in the first column, and outputs the result as a correlation output.

Then, at the timing of the 17-chip time, 1 to 15 of the basic correlator block 10 in the second row are used.
The sample-and-hold circuit 5 in the row makes the P-code corresponding to the CDMA-modulated analog signal in 2 to 16 chips
The result of multiplication with the N code is held, and the result of the multiplication of the CDMA code analog signal and the 16th PN code by the sample-and-hold circuit 5 in the 16th row at the subsequent 17-chip time is held. Become like

Thereafter, each time a clock signal is input from the clock generation circuit 11, the addition switch control circuit 13 sequentially transmits the addition instruction signal to the sample and hold circuits 5 in the first to sixteenth rows of each basic correlator block 10. Output,
The signals held by the sample-and-hold circuit 5 are simultaneously output to the corresponding addition signal lines, and the adder 4 receives the input of the signal added for each of the basic correlator blocks 10 and outputs the correlation at each timing. Output as output. That is, each basic correlator block 10
Since the addition instruction is performed at each chip timing, correlation outputs shifted one chip at a time are sequentially obtained.

Next, the case where the spreading factor is 8 will be described. In this case, the switches 65-1 to 65-4 of the selection means 62-1 of the sample and hold switch control circuit 51 are described.
Connect T5 to T8 to T'5 to T'8, respectively,
2-2 switches 66-1 to 66-8 respectively set T1 to T8 and T '
9 to T'16, and the PN code register 3 is connected to one row to the matrix sample and hold circuit 50.
The PN code corresponding to each of the first to eighth chips is output to the multipliers 2-1 to 2-8 corresponding to the eighth row. At this time, the operation of the basic correlator blocks 10 in the ninth column and thereafter is stopped.

Then, the variable chip addition control circuit 14 of the addition control circuit 12 turns on the switch 52-1 on the addition signal line of each basic correlator block 10 and immediately after the sample-and-hold circuit 5 in the fourth row, thereby turning on the eight rows. The switch 52-2 immediately after the eye sample and hold circuit 5 is turned off.

Then, the data fetch signal generation means 61 of the sample / hold switch control circuit 51 sequentially outputs fetch signals to the fetch signal lines T1 to T16 in accordance with the clock signal input from the clock generation circuit 11.

Then, by the operation of the selecting means 62, the contents of T1 to T8 are output to the matrix sample and hold circuit 50 as they are via T'1 to T'8, and the same T1 to T8 is output.
To T8 are output via T'9 to T'16.

Therefore, initially, T1, T'1 and T'9
, A capture signal is output to each sample-and-hold circuit 5 in the first row, the first column, the eighth row, the second column,..., The second row, the eighth column. At this time, the differential amplifier 60 outputs a positive-phase signal and a negative-phase signal based on the CDMA-modulated analog signal, and the multipliers 2-1 to 2-8 output PN signals input from the PN code register 3 respectively. According to the code, either the positive-phase signal or the negative-phase signal is selected and output as a multiplication result to each sample / hold 5 in the corresponding row of the matrix sample / hold circuit 50.

As a result, the first PN code and the CDMA-modulated analog signal are multiplied in the first sample-hold circuit portion of the time-division operation sample-hold circuit 5-1 in the first row and first column. The signal is held, and the sample-and-hold circuit 5 in the eighth row, the second column, the seventh row, the third column,.
The signal obtained by multiplying the modulated analog signal is held.

Further, at the timing of the next two chips, via the fetch signal line T2 and T'2 and T'10,
A fetch signal is output to the sample-and-hold circuit 5 in the second row, the first column, the first row, the second column, the eighth row, the third column,.
At the same time, the multipliers 2-1 to 2-8 obtain the result of multiplying the CDMA-modulated analog signal input at the next timing by each corresponding PN code.
Multipliers output by the multipliers 2-1 to 2-8 corresponding to the respective rows of the sample-and-hold circuits 5 in the first row, the first row, the second column, the eighth row, the third column,... Will hold the result.

Thereafter, the same operation is performed, and after eight chip time has elapsed, the basic correlator block 1 in the first row
The sample and hold circuits 5 in the first to eighth rows of 0
The result obtained by multiplying the CDMA modulated analog signal at the timing of 8 chip times by the corresponding first to eighth PN codes is held.

Then, the addition switch control circuit 13
When a clock signal indicating a timing of 9 chip times is input from the clock generation circuit 11, an addition instruction signal is sequentially output to the sample and hold circuits 5-1 to 5-16 of the first to 16th rows of each basic correlator block 10. I do.

Then, each of the sample and hold circuits 5-1 to 5-1
The signals held by 5-16 are simultaneously output to the addition signal line, but since the switch 52-2 is off,
The adder 4 includes a sample and hold circuit 5 for the first to eighth rows.
Only the multiplication results held by -1 to 5-8 are transmitted, and the adder 4 accumulates the transmitted multiplication results and outputs the result as a correlation output at each timing for each basic correlator block 10. Become like

At this time, the time division operation sample of the first row
In the hold circuit 5-1, the signal held by the first sample / hold circuit portion is output to the addition signal line, and at the same time (at the timing of 9 chips), the selection switch 58 is turned on by the second sample / hold circuit. The hold circuit portion is selected, and the signal of the multiplication result output from the multiplier 2-1 at the timing of the nine chip time is held by the second sample / hold circuit portion.

After the lapse of 9 chips, 2
In the basic correlator block 10 in the column, the sample-and-hold circuit 5 in the first to seventh rows multiplies the CDMA-modulated analog signal at the timing of 2 to 8 chip times by the corresponding first to seventh PN codes. Hold and
The sample-and-hold circuit 5 in the eighth row holds the result of multiplying the CDMA-modulated analog signal and the eighth PN code at the timing of the succeeding nine-chip time.

Thereafter, each time the addition control circuit 12 receives a clock signal from the clock generation circuit 11, a portion corresponding to the spreading factor of each basic correlator block 10, ie, the sample and hold circuit of the first to eighth rows, 5-1 to 5-8
Is transmitted to the adder 4 and the adder 4
Is added to the transmitted multiplication result, and is output as a correlation output at each timing for each basic correlator block 10. That is, by instructing each basic correlator block 10 to perform addition at each chip timing, correlation outputs shifted by one chip can be sequentially obtained.

When the designated spreading factor is 4, the switch 52-1 is turned off and operates similarly. When the spreading factor is 8, the signals output from the sample-and-hold circuits 5 on the ninth and subsequent rows are grounded, and when the spreading factor is 4, the switches 52- 2 may be turned on, and the signals output from the sample and hold circuits 5 in the fifth and subsequent rows may be grounded. This has the effect of stabilizing the operation without generating stray capacitance of the circuit.

According to such a first matched filter of the present invention, the switch 5 provided on the addition instruction signal line
2 and the operation of the addition control circuit 12, there is an effect that it is possible to cope with a change in the spreading factor with a simple and small-sized configuration while further suppressing power consumption.

Next, a matched filter according to a second embodiment of the present invention will be described with reference to the drawings. The matched filter according to the second embodiment of the present invention, when the spreading factor is smaller than the number of columns of the basic correlator block 10, the sample and hold of a row subsequent to the row corresponding to the spreading factor. Focusing on the fact that the circuit 5 is not working, the sample-and-hold circuit 5 also stores the multiplication result in duplicate, and performs cumulative addition at the same time during addition.
Thereby, the signal-to-noise ratio (S / N) of the correlation output can be improved.

Next, a second matched filter of the present invention will be described with reference to FIG. FIG. 8 is a schematic block diagram of a second matched filter according to the present invention.
As shown in FIG. 8, the second matched filter of the present invention includes a differential amplifier 60, a plurality of multipliers 2 provided corresponding to the number of chips having the maximum spreading factor, a PN code register 3, An adder 4, a clock generator 11, an addition switch control circuit 13, a spreading factor control circuit 15, and a matrix sample and hold circuit 50 'having a number of basic correlator blocks 10 corresponding to the maximum spreading factor; , And a sample and hold switch control circuit 51 '.

Here, the differential amplifier 60, the multiplier 2, the adder 4, the clock generator 11, and the addition switch control circuit 1
3 and the spreading factor control circuit 15 are the same as those of the first matched filter of the present invention described above. Note that PN
Here, the code register 3 has, for example, a spreading factor of 16
In the case of, the 1st to 16th PN codes are
When the spreading factor is 8, the PN code of the 1st to 8th is set to the multipliers 2-1 to 2-8 of the 1st to 8th and 9th to the 16th multipliers 2-1 to 2-16. The 16th to 16th multipliers 2-9 to 2-16 are set respectively.

Matrix sample and hold circuit 50 '
Is similar to that of the first matched filter of the present invention,
The sample-and-hold circuits 5 are arranged in a grid pattern in the matrix direction. In addition to the sample-and-hold circuits 5-1 in the first row of each basic correlator block 10, the sample and hold circuits 5 The difference is that the sample-and-hold circuit 5 in the row next to the corresponding row is a time-division operation sample-and-hold circuit.

That is, if the maximum spreading factor is 16 and the specifiable spreading factors are 4, 8, and 16, the spreading factor is 4 or 8, and the multiples of 4, 8, and 12 lines are used. The line immediately after the eye, that is, one of the basic correlator blocks 10
The sample-hold circuit 5-1 in the row, the sample-hold circuit 5-5 in the fifth row, the sample-hold circuit 5-9 in the ninth row, and the sample-hold circuit 5-13 in the thirteenth row
Are time-division operation sample-and-hold circuits.

The time-division sample-and-hold circuit includes a sample-and-hold circuit 5-1 in the first row and a sample-and-hold circuit 5 in the row next to the row corresponding to the spreading factor.
Except for the above, the operation is the same as that of the ordinary sample and hold circuit 5 without performing the time division operation. That is,
When the spreading factor is 8, the sample-and-hold circuits 5-1 in the first row and the sample-and-hold circuits 5-9 in the ninth row operate in a time-division manner, and the sample-and-hold circuits 5-5 in the fifth row
And the sample-and-hold circuit 5-13 on the thirteenth row do not perform time-division operation.

Sample / hold switch control circuit 5
1 'is the sample-and-hold circuit 5 in the nth row of the basic correlator block 10 in the mth column when the spreading factor is k.
With respect to -n, a capture signal is output at a timing of a chip time of mod (m + n-1, k).

More specifically, as shown in FIG. 9, the sample / hold switch control circuit 51 'mainly comprises a sample / hold data fetch signal generation means 61 and a plurality of selection means 62'. The fetched signals are transferred via fetch signal lines T'1 to T'16 connected to the sample and hold circuits 5 of each row of the basic correlator block 10 in the first column (first column) of the matrix sample and hold circuit 50. It is conceivable that it is output. FIG. 9 is a schematic block diagram of a sample / hold switch control circuit 51 'of the second matched filter of the present invention. In FIG. 9, for the sake of simplicity, the case where the maximum spreading factor is 16 and the specifiable spreading factors are 4, 8, and 16 is described as an example.

The data take-in signal generation means 61
The sample of the first matched filter of the present invention shown in FIG.
This is similar to that of the hold switch control circuit 51, and sequentially outputs a capture signal to the corresponding capture signal lines T1 to T16 according to the clock signal input from the clock generator 11. The data fetching signal generating means 61 determines that the spreading factor is 4 according to the spreading factor.
When, the capture signal is sequentially output to the capture signal lines T1 to T4, and when the spreading factor is 8, the capture signal is sequentially output to the capture signal lines T1 to T8.

Here, the capture signal lines T1 to T4 are shown as being connected to the capture signal lines T'1 to T'4 directed to the matrix sample and hold circuit 50 'as they are. This is because there is no plan to operate the spreading factor as two chips or one chip.

The selecting means 62 'operates when the spreading factor is 4 chips and when the spreading factor is 8 chips. More specifically, the selecting means 62'- operates when the spreading factor is 4 chips. 1 is four switches 65-1 corresponding to the number of chips
To 65-4. For example, a capture signal line T1 and a capture signal line T5 are connected to one end of the switch 65-1,
The other end is connected to a take-in signal line T'5 toward the matrix sample and hold circuit 50 '. When the spreading factor is 4, the switch 65-1 connects the capture signal lines T1 and T'5. When the spread factor is 8 or 16, the switch 65-1 connects the capture signal lines T5 and T'5. Is to be connected.

That is, the ith switch 65-i connects the fetch signal line Ti or Ti + 4 to the fetch signal line T'i + 4 toward the matrix sample and hold circuit 50 'according to the spreading factor. Things.

Similarly, the selection means 62'-2 which operates when the spreading factor is 8 chips includes eight switches 66'-1 to 66'-8 corresponding to the number of chips, and the i-th switch 66 ''-I is x = mod when the spreading factor is k.
As (i, k), the fetch signal line Tx is connected to the fetch signal line T'i + 8 toward the matrix sample and hold circuit 50 '.

That is, when the spreading factor is 16 chips, the sample / hold switch control circuit 51 '
For example, one row and one line via the capture signal lines T1 and T'1
The fetched signal is transmitted to each sample-and-hold circuit 5 in the second row, the 16th column, the 16th row, the second column, the 15th row, the third column,..., And when the spreading factor is 4 chips,
By the operation of the selection means 62, the capture signal line T1 and
Each sample-and-hold circuit 5 in the first row, the first column, the fourth row, the second column, the third row, the third column, the second row, the fourth column, the fifth row, the first column, and the eight rows, two columns via T'1 , The 7th row, the 3rd column, the 6th row, the 4th column, each sample hold circuit 5, the 9th row, the 1st column, the 12th row, the 2nd column,
Each sample-and-hold circuit 5 in the 11th row, the 3rd column, the 10th row, the 4th column, the 13th row, the 1st column, the 16th row, the 2nd column, the 15th row, the 3rd column,
A capture signal is transmitted to each sample-and-hold circuit 5 in the 14th row and the 4th column.

Next, the operation of the second matched filter of the present invention will be described. In the following description, a case where the maximum spreading factor is 16 and the spreading factor is one of 4, 8, and 16 will be described as an example for the sake of simplicity. It is assumed that the selection switches 58 of the time-division operation sample-and-hold circuits 5-1, 5-5, and 9-9 of each basic correlator block 10 initially select the first sample-and-hold circuit. First, if the spreading factor is 16,
The switches 65-1 to 65-4 of the selection means 62'-1 of the sample and hold switch control circuit 51 'respectively connect T5 to T8,
Switch 6 of the selection means 62'-2 connected to T'5 to T'8.
6'-1 to 66'-8 connect T9 to T16, respectively, to T'9 to T'16.

Sample / hold switch control circuit 5
The 1 'data fetch signal generation means 61 sequentially outputs fetch signals to the fetch signal lines T1 to T16 in accordance with the clock signal input from the clock generation circuit 11. Then, by the operation of the selecting means 62 ', the contents of T1 to T16 are output to the matrix sample and hold circuit 50' via T'1 to T'16 as they are. Therefore, at first, one row and one row are connected via T1 and T'1.
The capture signal is output to each sample-and-hold circuit 5 in the column, 16th row, 2nd column,..., 2nd row, 16th column.

On the other hand, at this time, the differential amplifier 60 outputs a positive-phase signal and a negative-phase signal based on the CDMA-modulated analog signal, and the multipliers 2-1 to 2-16 each output a PN code register. According to the PN code input from 3, either the normal-phase signal or the negative-phase signal is selected and output to each sample / hold 5 in the corresponding row of the matrix sample / hold circuit 50 'as a multiplication result.

As a result, the first PN code and the CDMA-modulated analog signal are multiplied by the first sample-and-hold circuit portion of the time-division operation sample-and-hold circuit 5-1 in the first row and the first column. The signal is held, and the corresponding PN code and the CDMA-modulated analog signal are stored in each sample-and-hold circuit 5 in the 16th row, the second column, the 15th row, the third column,. Is held.

Further, at the next timing, the second row, the first column, the first row, the second column, and the like are input via the capture signal lines T2 and T'2.
16th row, 3rd column,..., 3rd row, 16th column sample / hold circuit 5 (first time sample / hold circuit portion in time-division operation sample / hold circuit 5-1 in 1st row, 2nd column) At the same time, a result obtained by multiplying the CDMA-modulated analog signal input at the next timing by each corresponding PN code is output to the multiplier 2.
-1 to 2-16, and the sample-and-hold circuits 5 in the second row and first column, the first row and second column, the 16th row and the third column,..., The third row and the 16th column perform multiplication corresponding to each row. The results of the multiplication output from the units 2-1 to 2-16 are held.

Thereafter, the same operation is performed, and after the lapse of 16 chip times, the sample-and-hold circuits 5 in the first to 16th rows of the basic correlator block 10 in the first column are used for 1 to 16 chip times. The result obtained by multiplying the CDMA-modulated analog signal at the timing by the corresponding 1st to 16th PN codes is held.

The addition switch control circuit 13
In response to the input of a clock signal at a timing of 17 chip times from the clock generation circuit 11, an addition instruction signal is output to the sample-and-hold circuits 5 in the 1st to 16th rows of the basic correlator block 10 in the first column.

At this time, the selection switch 58 of the time-division operation sample-and-hold circuit 5-1 in the first row and the first column selects the second sample-and-hold circuit portion, and the first sample-and-hold circuit portion Output the signal held by the adder signal line, and based on the clock signal representing the same chip timing as the add instruction signal, the capture signal input at the same time (at a timing of 17 chip times) is output. By outputting the result to the sample-and-hold circuit portion 2 in the same manner, the result of the multiplication output from the multiplier 2-1 is held in the second sample-and-hold circuit portion at the timing of 17 chips.

On the other hand, the signals held by the sample and hold circuits 5-2 to 5-n in the second and subsequent rows of the first column are simultaneously output to the corresponding addition signal lines. The multiplication results for 16 chip times held in each sample / hold circuit 5 of the basic correlator block 10 in the first column are added and output as a correlation output.

Then, at the timing of the 17-chip time, 1 to 15 of the basic correlator block 10 in the second row are used.
The sample-and-hold circuit 5 in the row makes the P-code corresponding to the CDMA-modulated analog signal in 2 to 16 chips
The result of multiplication with the N code is held, and the result of the multiplication of the CDMA code analog signal and the 16th PN code by the sample-and-hold circuit 5 in the 16th row at the subsequent 17-chip time is held. And so on.

Thereafter, each time a clock signal is input from the clock generation circuit 11, the addition switch control circuit 13 sequentially transmits the addition instruction signal to the sample-and-hold circuits 5 in the first to sixteenth rows of each basic correlator block 10. Output,
The signals held by the sample-and-hold circuit 5 are simultaneously output to the corresponding addition signal lines, and the adder 4 receives the input of the signal added for each of the basic correlator blocks 10 and outputs the correlation at each timing. Output as output. That is, each basic correlator block 10
Since the addition instruction is performed at each chip timing, correlation outputs shifted one chip at a time are sequentially obtained.

Next, the case where the spreading factor is 8 will be described. In this case, the switches 65-1 to 65 of the selection means 62'-1 of the sample and hold switch control circuit 51 'are used.
-4 connects T5 to T8 to T'5 to T'8, respectively, and switches 66'-1 to 66'-8 of the selection means 62'-2 connect to T1 to T8, respectively.
Are connected to T'9 to T'16, and only the sample and hold circuits 5 in the first and ninth rows of the matrix sample and hold circuit 50 'perform the time division operation.

At this time, the PN code register 3 is provided to each of the first to eighth chips for the multipliers 2-1 to 2-8 corresponding to the first to eighth rows of the matrix sample and hold circuit 50 '. The corresponding PN code is output, and the PN code corresponding to each of the first to eighth chips is also output to the multipliers 2-9 to 2-16 corresponding to the ninth to sixteenth rows. further,
At this time, the basic correlator blocks 10 in the ninth and subsequent columns
Has stopped working.

Sample / hold switch control circuit 5
The 1 'data fetch signal generation means 61 sequentially outputs fetch signals to the fetch signal lines T1 to T16 in accordance with the clock signal input from the clock generation circuit 11.

Then, by the operation of the selection means 62 ', the matrix sample-and-hold circuit 50' has T1 to T8.
Are output as they are via T'1 to T'8, and the same contents of T1 to T8 are output via T'9 to T'16.

Therefore, initially, T1, T'1 and T'9
, The 1st row, the 1st column, the 8th row, the 2nd column,..., The 2nd row, the 8th column, and the 9th row, the 1st column, the 16th row, the 2nd column,. The captured signal is output to each sample-and-hold circuit 5 of the eye. At this time,
The differential amplifier 60 outputs a positive-phase signal and a negative-phase signal based on the CDMA-modulated analog signal.
-16 is the PN input from the PN code register 3.
According to the code, either the positive-phase signal or the negative-phase signal is selected, and the matrix sample-and-hold circuit 50 'is selected.
Is output as a multiplication result to each sample and hold circuit 5 in the row corresponding to.

As a result, the first sample-hold circuit portion of the time-sharing operation sample-hold circuit 5-1 in the first row and the first column and the first sample-hold circuit portion of the time-division operation sample-hold circuit 5-9 in the ninth row and the first column are used. The sample-and-hold circuit portion 1 holds a signal obtained by multiplying the first PN code and the CDMA-modulated analog signal. The 8th row, 2nd column, 7th row, 3rd column,. The sample-and-hold circuit 5 at the second row and the eighth column holds a signal obtained by multiplying the corresponding PN code by the CDMA-modulated analog signal.

Further, at the timing of the next two chips, via the fetch signal line T2 and T'2 and T'10,
A fetch signal is output to the sample-and-hold circuit 5 in the second row, the first column, the first row, the second column, the eighth row, the third column,..., The third row, the eighth column, and the CDM input thereto at the next timing.
The results of multiplying the A-modulated analog signal by the corresponding PN codes are obtained by the multipliers 2-1 to 2-8. The above-mentioned second row, first column, first row, second column, and eight rows, third column ..,..., The third row and the eighth column each sample-hold circuit 5 holds the result of the multiplication output from the multipliers 2-1 to 2-8 corresponding to each row.

Thereafter, the same operation is performed, and after eight chips have elapsed, the basic correlator block 1 in the first row
The sample-and-hold circuits 5 in the first to eighth rows and the sample-and-hold circuits 5 in the ninth to sixteenth rows of the “0” correspond to the CDMA-modulated analog signal at the timing of 1 to 8 chip times, and The result of multiplication with the eighth to eighth PN codes is held.

Then, the addition switch control circuit 13
When a clock signal indicating a timing of 9 chip times is input from the clock generation circuit 11, an addition instruction signal is sequentially output to the sample and hold circuits 5 in the first to 16th rows of each basic correlator block 10, and the sample and hold is performed. The signals held by the circuit 5 are simultaneously output to the corresponding addition signal lines, and the adder 4
The input of the signal added at each timing is received and output as a correlation output at each timing.

At this time, in the time-division operation sample-and-hold circuits 5-1 and 5-9 on the first and ninth rows, the signal held by the first sample-and-hold circuit is output to the addition signal line. At the same time, the selection switch 58 selects the second sample and hold circuit portion (at the timing of 9 chip times), and the multiplication result output from the multiplier 2-1 at the timing of the 9 chip time. Is held by the second sample and hold circuit portion.

After the lapse of 9 chips, 2
In the basic correlator block 10 in the column, the sample-and-hold circuits 5 in the first to seventh rows and the sample-and-hold circuits 5 in the tenth to sixteenth rows correspond to CDMA-modulated analog signals at timings of 2 to 8 chip times. 1 to
The result of multiplication with the seventh PN code is held, and the sample-and-hold circuit 5 in the eighth row and the sample-and-hold circuit 5 in the sixteenth row are used to hold the CDMA-modulated analog signal 8 Th PN
The result of multiplying by the code is retained.

Thereafter, each time a clock signal is input from the clock generation circuit 11, the addition switch control circuit 13 sequentially outputs an addition instruction signal to the sample and hold circuit 5 of each basic correlator block 10, and
The signals held by the hold circuit 5 are simultaneously output to the corresponding addition signal lines, and the adder 4 receives the signal added for each basic correlator block 10 and outputs the signal as a correlation output at each timing. I will be. That is, by instructing each basic correlator block 10 to perform addition at each chip timing, a value equivalent to twice the correlation output shifted by one chip can be sequentially obtained.

Similarly, when the spreading factor is 4, the sample and hold circuits 5-1 to 5-4 in the first to fourth rows and the sample and hold circuits 5-5 to 5-5 in the fifth to eighth rows are similarly processed. Sample hold circuits 5-9 and 5-12 to 5-12 and sample hold circuits 5-13 to 13-16:
16 hold the multiplication results obtained by multiplying the first to fourth PN codes by the CDMA-modulated analog signals. One chip is provided for each basic correlator block 10 upon receiving the input of the addition instruction signal. A value equivalent to four times the correlation output shifted by one by one can be sequentially obtained.

According to such a second matched filter of the present invention, the number of time-division operation sample-and-hold circuits increases, but when the spreading factor is low, the multiplication result for obtaining a correlation output becomes plural. Therefore, there is an effect that the signal-to-noise ratio (S / N) of the correlation output can be improved.

In the first and second matched filters of the present invention, the matrix sample-and-hold circuit 5
Since the sample-and-hold circuits 5 arranged in a grid pattern are used as 0, these matched filters are set to L
When forming the SI, the layout pattern of the DRAM can be diverted as the pattern of the information holding capacitance 56 of each sample and hold circuit 5, and there is an effect that the LSI can be easily formed.

Furthermore, the information holding electrostatic capacitance 56 may be easily manufactured because it is sufficient that the capacitance value is equal and the absolute size is not limited. That is, the information holding capacitance 56 of the sample / hold circuit 5 is preferably larger than the parasitic capacitance of the MOS transistor of the sample / hold switch 55 and the MOS transistor of the addition switch 57 and the parasitic capacitance due to wiring. However, it is only necessary that the values including the parasitic capacitance from the output side of the sample-and-hold switch 55 to the input side of the addition switch 57 match, and the parasitic capacitance of the other portions may be different. There is an effect that the degree of freedom of wiring is large, the layout can be easily performed, and the LSI can be easily formed.

Further, instead of the differential amplifier 60 of the first and second matched filters of the present invention, an inverter circuit for inverting a CDMA-modulated analog signal and outputting the inverted signal as an inverted-phase signal may be used. If the threshold value is exceeded, a voltage signal of, for example, about 2.5 V is output as a signal of "1". If not, a voltage signal of, for example, about 0.5 V is output as a signal of "-1". An output 1-bit AD converter may be used.

When a 1-bit AD converter is used, when the input PN code is “1”, the multiplier 2 outputs the signal output from the AD converter as it is, and outputs the PN code. Is "0", a signal output from the AD converter may not be taken in.

Further, instead of the differential amplifier 60, a circuit (staircase wave circuit) for converting an input CDMA-modulated analog signal into a staircase signal may be used.
In such a circuit, two thresholds, high and low, are set. If the magnitude of the input signal exceeds a first threshold (threshold with a high value), for example, 2. 5V is output, and if it is between the first threshold value and the second threshold value (low threshold value), for example, 1.5V is output,
Is smaller than the threshold value, for example, 0.5 V is output.

Also in this case, the multiplier 2 receives the input P
When the N code is "1", the signal output from the AD converter is output as it is, and when the PN code is "0", the signal output from the AD converter is not taken in. It is possible.

Further, the first and second matched filters of the present invention complete the operation as a matched filter,
When the phase relationship becomes clear, the unnecessary part is rested by using the single basic correlator block 10,
Demodulation can be performed while reducing power consumption. At this time, in the second matched filter, similarly to the first matched filter, a switch is provided on the addition signal line to selectively multiply from the number of sample-and-hold circuits 5 corresponding to the designated spreading factor. Get the result and accumulate,
A correlation output can be considered.

If a small number of (for example, three) basic correlator blocks 10 are demodulated one chip time at a time around the phase where synchronization is established, the demodulation operation can be performed with the preceding and succeeding phases. When the correlation signal becomes large, the phase shift can be detected, so that it is possible to perform demodulation with high accuracy while monitoring the phase, and because the unnecessary basic correlator block 10 is off, power consumption is reduced. Can be reduced.

It is to be noted that the correspondence to a plurality of paths (so-called delayed waves) is controlled by controlling the number of basic correlator blocks 10 to be used (generally, about three times the number of paths) or not for each basic correlator block. Therefore, power consumption can be significantly reduced as compared with the conventional matched filter.

When the oversampling process is performed, for example, as shown in FIG.
Comprises several sample-and-hold circuits 5 corresponding to the number corresponding to the number of oversampling times the maximum spreading factor,
That is, when the maximum spreading factor is n and the number of oversamplings is p, the basic correlator block 10 in which the sample-and-hold circuits 5 of n rows × p columns are arranged can be considered. FIG. 10 is a configuration block diagram illustrating a schematic configuration of the basic correlator block 10 in the matched filter that performs oversampling according to the present invention.

In this case, each time the sample-and-hold switch control circuit 51 divides the chip timing by the oversampling number, the sampling timing corresponds to the oversampling number in the n-th row of the basic correlator block 10 in the m-th column. And the number of sample-and-hold circuits 5-n corresponding to the set,
This can be realized by sequentially outputting a capture signal to -n.

That is, in this case, each of the sample-and-hold circuits 5-n belonging to the group is set to one of the chip timings.
The result of multiplication is stored at a timing shifted by / p.

Further, the processing for each of the I phase and the Q phase can be achieved by operating a plurality of the matched filters in parallel.

[0161]

According to the first aspect of the present invention, the CDMA-modulated analog signal output from the multiplying means and the PN signal are output.
A plurality of basic correlator blocks each having the number of sample-and-hold circuits corresponding to the maximum spreading factor hold the result of multiplication with the code at a shifted timing for each chip timing, and are designated at the timing of the addition. Since the number of sample-and-hold circuits corresponding to the spreading factor selectively outputs the held multiplication result, and the adder is a matched filter that adds the output multiplication result and outputs the result as a correlation output, There is an effect that can respond to changes in

According to the second aspect of the present invention, the result of multiplication of the CDMA-modulated analog signal and the PN code output by the multiplying means is grouped by the number of over-sampling circuits in the sample and hold circuit. Each set of a plurality of basic correlator blocks having the number corresponding to the spreading factor holds the number corresponding to the oversampling number at a shifted timing for each chip timing, and is designated at the addition timing. The number of sample-and-hold circuits corresponding to the spreading factor is selectively output the held multiplication result, and the adder is a matched filter that adds the output multiplication result and outputs the result as a correlation output. Thus, there is an effect that it is possible to respond to a change in the spreading factor while realizing oversampling.

According to the third aspect of the present invention, the multiplying means outputs the result of the multiplication of the CDMA-modulated analog signal and the PN code, and when a spreading factor smaller than the maximum spreading factor is designated. In addition, a plurality of basic correlator blocks each having a number of sample-and-hold circuits corresponding to the maximum spreading factor hold the multiplication result output from the multiplier for a plurality of symbols at a timing shifted by one chip time, respectively. At the timing, the held multiplication results are output all at once,
Since the adder employs a matched filter that adds the output signals and outputs the result as a correlation output, when the spreading factor is low, a plurality of multiplication results are obtained to obtain the correlation output. There is an effect that the noise ratio (S / N) can be improved.

According to the fourth aspect of the present invention, the number of sample-and-hold circuits corresponding to the number of oversamples is set, and the multiplying means outputs the result of multiplication of the CDMA-modulated analog signal by the PN code. When a spreading factor smaller than the maximum spreading factor is specified, a plurality of basic correlator blocks each having a set of sample and hold circuits corresponding to the maximum spreading factor are shifted by one chip time. At the timing, the multiplication result output from the multiplier is held for a plurality of symbols, and at the addition timing, the held multiplication result is output all at once, and the adder adds the output signals and outputs as a correlation output. Since the filter is a matched filter, when the spreading factor is low, there are multiple multiplication results to obtain the correlation output. There is an effect that it is possible to improve the signal-to-noise ratio of the output (S / N).

According to the fifth aspect of the present invention, each sample-hold circuit in the first row of the basic correlator block forming the matrix sample-hold circuit is a sample-hold circuit performing a time-division operation. Since the matched filter according to claim 2 is used, there is an effect that the spreading factor achieved by the invention according to claim 1 or 2 can be changed, and the multiplication result can be obtained while sufficiently taking time for addition. It has the effect that it can be maintained without changing.

According to the sixth aspect of the present invention, the sample signal corresponding to the specifiable spreading factor is provided on the addition signal line for outputting the signal held by each sample and hold circuit.
A switch is provided immediately after the hold circuit, and when the spreading factor is specified, the sample / sample corresponding to the specified spreading factor is set.
2. The switch immediately after the hold circuit is opened, the adder receives the multiplication result selectively held from the sample and hold circuit corresponding to the designated spreading factor, receives the multiplication result, accumulates the result, and outputs the result as a correlation signal. Alternatively, since the matched filter according to claim 2 or 5 is used, there is an effect that the spreading factor can be changed with a simple and small-scale configuration.

According to the seventh aspect of the present invention, the sample data corresponding to the first row of the basic correlator block forming the matrix sample and hold circuit and the specifiable spreading factor can be obtained.
Since each sample-and-hold circuit in the next row of the hold circuit is a sample-and-hold circuit that performs a time-division operation, the matched filter according to the third or fourth aspect is provided. This has the effect of improving the signal-to-noise ratio (S / N) of the correlation output to be played, and has the effect of retaining the multiplication result without giving a sufficient time for addition.

If the multiplying means is constituted as in the inventions of claims 8 to 11, claims 1, 2 or 3 or 4 or 5 or 6 or 7 will be described. In the matched filter described above, there is an effect that a multiplication unit can be realized with a small and simple configuration, and an effect that power consumption can be reduced.

According to the twelfth aspect of the invention, the plurality of specifiable spreading factors are 2 to the power of a positive integer, and the spreading factor is a positive integer power of 2. Since the matched filter according to claim 6 or claim 7 or claim 8 or claim 9 or claim 10 or claim 11 is used, there is an effect that a matched filter suitable for general CDMA communication can be provided. In the matched filter according to the third or fourth aspect, the multiplication result of the number of symbols that is an integral multiple of 2 of the designated spreading factor can be always held, so that the use efficiency of the sample and hold circuit is improved. There is an effect that can be.

According to the thirteenth aspect, the first aspect is provided.
In the matched filter according to the twelfth aspect, the sample-and-hold circuits constituting the matrix sample-and-hold circuit are arranged in a grid pattern, thereby achieving
There is an effect that the layout pattern of the RAM can be diverted, and the capacitance holding the multiplication result in each sample-and-hold circuit only needs to have the same capacitance value. Since the degree of freedom of the parasitic capacitance in the sample and hold circuit is high, the degree of freedom of wiring is large, the layout can be easily performed, and the LSI can be easily formed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of a first matched filter of the present invention.

FIG. 2 is a schematic block diagram of a part of a first matched filter of the present invention.

FIG. 3 is a schematic block diagram of a part of a first matched filter of the present invention.

4 is a matrix sample-and-hold circuit 50 of FIG.
5 is an enlarged view of a sample-and-hold circuit 5-4 on the fourth row and a sample-and-hold circuit 5-5 on the fifth row of one basic correlator block 10. FIG.

FIG. 5 is a schematic block diagram of a part of a first matched filter of the present invention.

FIG. 6 is a schematic configuration block diagram of a part of the first matched filter of the present invention.

FIG. 7 is a circuit diagram of a first matched filter addition control circuit of the present invention.

FIG. 8 is a schematic configuration block diagram of a second matched filter of the present invention.

FIG. 9 shows a sample of a second matched filter of the present invention;
It is a schematic block diagram of a hold switch control circuit 51 '.

FIG. 10 is a configuration block diagram illustrating a schematic configuration of a basic correlator block 10 in a matched filter that performs oversampling according to the present invention.

FIG. 11 is a configuration block diagram of a part of a conventional sliding correlator.

FIG. 12 is a block diagram illustrating a configuration example of a conventional matched filter.

[Explanation of symbols]

1 AD converter, 2, 2 ', 2 "... multiplier, 3,
3 '... PN code register, 4,4' ... Adder,
5, 5 ': sample / hold circuit, 10: basic correlator block, 11: clock generator, 12: addition control circuit, 13: addition switch control circuit, 14
... variable chip addition control circuit, 15 ... spreading factor control circuit,
50, 50 '... matrix sample and hold circuit,
51, 51 ': sample / hold switch control circuit, 52: switch, 55: sample / hold switch, 56: information holding capacitance, 57: addition switch, 58: selection switch, 60: differential amplifier, 61 ... data fetch signal generating means 62,6
2 '... selection means, 65 ... switches, 66,66' ...
switch

Claims (13)

[Claims] 1. A plurality of multiplying means for receiving an input of a CDMA-modulated analog signal, multiplying the analog signal by a number of PN codes corresponding to a designated spreading factor, and outputting the result as a multiplication result; Among a plurality of specifiable spreading rates, a basic correlator block in which the number of sample and hold circuits corresponding to the maximum spreading rate are arranged in the column direction is arranged in the row direction by the number corresponding to the maximum spreading rate. A matrix sample-and-hold circuit, wherein each of the sample-and-hold circuits receives a capture signal representing a timing of capturing a multiplication result, and captures a corresponding one of the multiplication results output by the multiplication means. A sample and hold circuit, which is a sample-and-hold circuit that receives an addition instruction signal indicating the timing of addition and holds the signal and outputs the held signal. And Rikusu sample and hold circuit for each chip timing, sequentially selects the basic correlator blocks from the matrix sample and hold circuit,
The sample that constitutes the selected basic correlator block
An addition switch control circuit that outputs an addition instruction signal to the hold circuit; and a sample / hold circuit that constitutes the matrix sample / hold circuit for each chip timing.
For a plurality of sample and hold circuits that have the same remainder after dividing the sum of the number of rows and the number of columns where the sample and hold circuit is arranged by the designated spreading factor,
A sample-and-hold switch control circuit that simultaneously captures and holds a multiplication result output by the multiplication means corresponding to each of the plurality of sample-and-hold circuits, and a sample-and-hold circuit that forms the basic correlator block Among the circuits, an adder for receiving the signals held from the number of sample and hold circuits corresponding to the designated spreading factor, adding the signals, and outputting the sum as a correlation output. And the matched filter. 2. A plurality of multiplying means for receiving a CDMA-modulated analog signal, multiplying the analog signal by a number of PN codes corresponding to a designated spreading factor, and outputting the result as a multiplication result; The number of sample-and-hold circuits corresponding to the number of oversamplings is set as a set, and a basic correlator block in which the set is arranged in the column direction by a number corresponding to the maximum spreading rate among a plurality of spreading rates that can be specified, A matrix sample and hold circuit arranged in the row direction by the number corresponding to the diffusion rate, wherein each of the sample and hold circuits is
Upon receiving an input of a capture signal indicating the timing of capturing the multiplication result, among the multiplication results output by the multiplication means,
A matrix sample-and-hold circuit, which is a sample-and-hold circuit that receives and holds a corresponding multiplication result, receives an addition instruction signal indicating the timing of addition, and outputs the held signal; and Select the basic correlator block sequentially from the matrix sample and hold circuit,
The sample that constitutes the selected basic correlator block
An addition switch control circuit that outputs an addition instruction signal to a hold circuit; and a sample / hold circuit that constitutes the matrix sample / hold circuit at each oversampling timing obtained by dividing the chip timing by the number of oversampling. Of the set, the remainder of dividing the sum of the number of columns of the basic correlator block to which the set belongs and the number of rows where the set is arranged in the basic correlator block by the designated spreading factor A capture signal that captures and holds a multiplication result output by the multiplication means corresponding to each sample and hold circuit, for a sample and hold circuit corresponding to the oversampling timing and belonging to a plurality of sets having the same Sample and hold switch control circuit that outputs all Of the sample-and-hold circuits constituting the basic correlator block, receiving the signals held from the number of sample-and-hold circuits corresponding to the designated spreading factor, adding the signals, and outputting the result as a correlation output A matched filter, comprising: 3. Multiplying means for receiving an input of a CDMA-modulated analog signal, multiplying the analog signal by a PN code corresponding to a designated spreading factor, and outputting the result as a multiplication result, Of sample and hold circuits corresponding to the maximum spreading factor,
Among the hold circuits, the x-th sample / hold circuit receives an input of a capture signal indicating the timing of capturing the multiplication result, and divides x of the multiplication result output by the multiplication means by a designated spreading factor. The multiplication result with the PN code of the number of chips corresponding to the remainder is captured and held, and upon receiving an input of an addition instruction signal indicating the timing of addition, the basic correlator block outputting the held signal corresponds to the maximum spreading factor. A matrix sample-and-hold circuit in which the sample-and-hold circuits forming the basic correlator block are arranged in the row direction and the basic correlator blocks are arranged in the column direction, and the matrix sample-and-hold circuit is provided for each chip timing. For the basic correlator block forming a circuit,
An addition switch control circuit for outputting an addition instruction signal to a sample-hold circuit of the basic correlator block; and a sample-hold circuit constituting the matrix sample-hold circuit for each chip timing, wherein the sample-hold circuit For a plurality of sample-and-hold circuits in which the remainder of dividing the sum of the number of rows and the number of columns where they are arranged by the designated spreading factor is the same, for each of the plurality of sample-and-hold circuits A sample-and-hold switch control circuit for simultaneously outputting a capture signal for capturing and holding a multiplication result output by the corresponding multiplication means; and a sample-and-hold circuit forming the basic correlator block, corresponding to a specified spreading factor. The number of sample-and-hold circuits ,
And an adder for accumulating the signals and outputting as a correlation output. 4. Multiplying means for receiving an input of a CDMA-modulated analog signal, multiplying the analog signal by a PN code corresponding to a specified spreading factor, and outputting the result as a multiplication result. Out of the spreading factors, the number of sample-and-hold circuits corresponding to the number of oversamplings is set as a set, and the set is provided in a number corresponding to the maximum spreading factor. Each of the sample-and-hold circuits belonging to the set of hold circuits receives an input of a capture signal indicating the timing of capturing the multiplication result, and, of the multiplication results output by the multiplication means, divides x by a designated spreading factor, and The multiplication result with the PN code of the corresponding chip number is captured and held, and upon receiving an input of an addition instruction signal indicating the timing of addition, The number of basic correlator blocks corresponding to the maximum spreading factor is provided to output the held signals, a set of sample and hold circuits forming the basic correlator block are arranged in the row direction, and the basic correlator blocks are arranged in the column direction. Matrix sample and hold circuit, and for each chip timing, the basic correlator block forming the matrix sample and hold circuit,
An addition switch control circuit for outputting an addition instruction signal to the sample and hold circuit of the basic correlator block; and the matrix sample and hold circuit for each oversampling timing obtained by dividing the chip timing by the number of oversamplings. And the sum of the number of rows where the set is arranged and the number of columns of the basic correlator block to which the set belongs is divided by the designated spreading factor. A multiplication result output by the multiplication means corresponding to each of the plurality of sample-hold circuits to a sample-hold circuit belonging to the same set of a plurality of sample-hold circuits and corresponding to the oversampling timing To capture and hold the A pull-hold switch control circuit, among the sample-hold circuits forming the basic correlator block, receiving the input of the signal held from the number of sample-hold circuits corresponding to the designated spreading factor,
And an adder for accumulating the signals and outputting as a correlation output. 5. A sample-and-hold circuit in a first row of a basic correlator block forming a matrix sample-and-hold circuit, comprising: a first sample-and-hold circuit portion;
And two sample-and-hold circuits for the second sample-and-hold circuit portion.
One of the hold circuit portion and the second sample / hold circuit portion is switched and selected, and the multiplication result output from the multiplier corresponding to the selected sample / hold circuit portion is held and not selected. 3. The matched filter according to claim 1, wherein the matched filter is a time-division operation sample-and-hold circuit that outputs a multiplication result held by the sample-and-hold circuit portion. 6. A sample-and-hold circuit forming each basic correlator block shares one addition signal line. When the sample-and-hold circuit receives an addition instruction signal as a signal for instructing addition, the sample-and-hold circuit receives the addition instruction signal. A sample-and-hold circuit for outputting an addition result held in a signal line, wherein a switch is provided immediately after the sample-and-hold circuit corresponding to a plurality of configurable spreading factors of the addition signal line, and a switch is provided. 6. The matched filter according to claim 1, further comprising an addition control circuit for opening the switch immediately after the sample-and-hold circuit corresponding to the spreading factor. 7. A sample / hold circuit in a first row of a basic correlator block forming a matrix sample / hold circuit, and a sample / hold circuit immediately after the sample / hold circuit corresponding to a plurality of specifiable spreading factors. Comprises two sample-and-hold circuits, a first sample-and-hold circuit portion and a second sample-and-hold circuit portion.
And the second sample-and-hold circuit portion is switched and selected, and the multiplication result output from the multiplier corresponding to the selected sample-and-hold circuit portion is held and selected. 5. The matched filter according to claim 3, wherein the matched filter is a time-division operation sample-and-hold circuit for outputting a multiplication result held by a sample-and-hold circuit portion not provided. 8. The multiplying means receives the CDMA-converted analog signal, outputs the signal as it is as a normal-phase signal, and converts the signal into a negative phase around a preset DC voltage value. The multiplication means includes a differential amplifier that outputs a phase signal and a multiplier that selects and outputs one of a positive-phase signal and a negative-phase signal output by the differential amplifier according to a corresponding PN code. The matched filter according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. 9. A multiplying means for converting an analog signal subjected to CDMA modulation into a 1-bit digital signal and outputting the signal as a voltage signal representing the bit, and selectively converting the voltage signal according to a PN code. 8. A matched filter according to claim 1, wherein the multiplier is a multiplier having a multiplier which is a switch to be incorporated into the matched filter. . 10. A multiplying means for converting a CDMA-modulated analog signal into a step-like signal that changes according to the magnitude thereof, and a switch for selectively taking in the voltage signal according to a PN code. 8. A matched filter according to claim 1, wherein the multiplier is a multiplier having the following multiplier: 11. A multiplication means for inverting a CDMA-modulated analog signal and outputting the inverted signal as a negative-phase signal, wherein the CDMA-modulated analog signal is directly used as a positive-phase signal according to a PN code, or 6. A multiplying means comprising a multiplier which is a switch which selectively takes in as an inverted-phase signal output from the inverter circuit. The matched filter according to claim 6. 12. A method according to claim 1, wherein said plurality of specifiable spreading factors are 2 raised to a power of a positive integer. The matched filter according to claim 7, claim 8, claim 9, claim 10, or claim 11. 13. An LSI comprising the matched filter according to claim 1. Description: