JP2000133800A - Method of estimating semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of precisely estimating parasitic resistor components by isolating the parasitic resistor components from each other using a device simulator. SOLUTION: A method of estimating parasitic resistor components comprises the steps of (1) performing structural analysis of an insulating gate transistor based on means of inverse modeling, (2) determining the sheet resistance of the channel region and the extended region of the source-drain region on the basis of the current-voltage characteristics in a linear state on a device simulator, and (3) integrating the sheet resistance from one end of the source-drain region to the other end, to isolate the parasitic resistors of the channel region and extended region and estimate them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a method for measuring the parasitic resistance of a miniaturized MOSFET (metal-oxide-semiconductor field effect transistor) for each component. The present invention relates to a method for evaluating a semiconductor device and a method for manufacturing a semiconductor device, which are characterized by a method of performing evaluation by dividing into two.

[0002]

2. Description of the Related Art Conventional miniaturization of MOSFETs and the like is not known to end, and the degree of integration of LSIs has been increasing year by year. The size of transistors constituting semiconductor memory devices and logic ICs is on the order of sub-0.1 μm. ,
That is, it is moving to 0.1 μm or less.

As described above, as MOSFETs become finer, the resistance felt by carriers in the source / drain regions cannot be ignored compared to the channel resistance. To improve the performance of the semiconductor device, The precise control of parasitic resistance and impurity profile has become increasingly important.

In the conventional measurement of parasitic resistance, the source-drain voltage V _ds , which is negligibly short channel effect, for example, the on-resistance R _ON of a MOSFET in a linear state in which a voltage of 50 mV is applied, is measured by a unit length. When the channel resistance of R is R _ch , the effective channel length is L _ch , and the parasitic resistance is R _p , it can be expressed by using R _ON = R _ch × L _ch + R _p .

[0005] Here, with reference to FIG.
The method of measuring the raw resistance will be described. See FIG. 5 (a). FIG.
C. Form multiple MOSFETs with various gate lengths
And V_gsIs applied between the gate and the source, that is,
Gate voltage, V_thIs the threshold voltage of each MOSFET.
In this case, (V_gs
-V_th) Is constant so that the gate voltage V_gsAnd set
Its gate voltage V_gsBetween source and drain
Voltage V of mV_dsCurrent I when applying_dsMeasure
Then V_ds/ I_dsON resistance R represented by_ONTo each gate length
The plot is plotted against (V)_gs
-V_th) Is fixed at two different values: (V_gs-V
_th)₁And (V_gs-V_th) _TwoAnd plot the two cases
ing.

In this case, generally, the threshold voltage V _th varies with each gate length due to the short channel effect, and the voltage (V _gs −V _th ) effectively applied to the channel region changes. If the capacity of the gate oxide film was _{C ox, C ox × (V} gs -V th) = ρ carrier density [rho _ch in the channel represented by _ch fluctuates,
For each gate length, the channel resistance R per unit length
_{Since the channel} fluctuates, the carrier density ρ _{ch in the channel} is made constant by making the voltage (V _gs −V _th ) effectively applied to the channel region constant, whereby the channel resistance per unit length is increased. It is corrected for variations of the R _ch.

Then, two constant voltages (V _gs -V _th ) ₁
And the (V _gs -V _{th) 2,} if the source and drain regions becomes effective channel length L _ch is 0 overlap exactly, on-resistance, _{respectively, R ON1 = R p1 R ON2} = R p2 However, since the MOSFETs having the same channel length have the same element structure, the parasitic resistances R _p1 and R _p2 are the same, and therefore they intersect at one point.

That is, two constant voltages (V_gs-V_th)₁Passing
(V_gs-V_th)_TwoON resistance R at_ONMeasurement results
In the plot, the intersection of the two
Anti-R _pAnd the overlap length, this value
From the parasitic resistance R_pWas evaluated.

[0009]

However, the parasitic resistance of the MOSFET constituting the actual logic device includes a silicide sheet resistance, a silicide-bulk contact resistance, and an LDD (Lightly Doped Dr).
ain) region, that is, the sheet resistance of the extension region and the resistance of the diffusion region of the extension. However, the conventional parasitic resistance measurement method cannot separate each of these parasitic resistance components. There is a problem that there is.

Here, each parasitic resistance component will be described with reference to FIG. FIG. 5B is a cross-sectional view of a main part showing a configuration of an extension region, that is, a drain region side of an n-channel MOSFET provided with an LDD region.
Forms an element isolation oxide film (not shown) by selectively oxidizing the p-type silicon substrate 11 and thermally oxidizes the surface of an element formation region surrounded by the element isolation oxide film to form the gate oxide film 12. After formation, n such as P (phosphorus)
A polycrystalline silicon gate electrode 13 doped with a type impurity is provided, and an n-type impurity such as As is ion-implanted shallowly using the polycrystalline silicon gate electrode 13 as a mask to form an n-type LDD region 14.

[0011] Next, using anisotropic etching,
After the sidewall 15 made of the O ₂ film is formed, the n ⁺ -type drain region 16 and the n ⁺ -type source region (FIG. After forming a silicide electrode 17 of CoSi or the like in the n ⁺ -type drain region 16 and the n ⁺ -type source region, an interlayer insulating film 19 is deposited on the entire surface.
The metal contact electrode 20 is formed through the contact hole provided in. The channel region directly below the gate oxide film 12 is channel-doped with B (boron) as necessary.

In this case, as the parasitic resistance R _p , first,
The sheet resistance of the silicide electrode 17 itself becomes a problem, and a thin Schottky barrier is formed at the interface between the silicide electrode 17 and the n ⁺ -type drain region 16, that is, at the silicide-bulk contact region 18. The current flows through the key barrier to effectively act as an ohmic contact, but the resistance associated with the current flowing through the Schottky barrier, that is, the silicide-bulk contact resistance becomes a problem.

Next, the sheet resistance of the LDD region 14 itself,
That is, the extension sheet resistance _Rsh becomes a problem,
Further, in the LDD region 14 extending directly below the polysilicon gate electrode 13, the resistance of the region where the pseudo channel is formed by depletion, that is, the extension diffusion resistance _Rac becomes a problem.

However, when it is impossible to separate the parasitic resistance components as described above, or when it is necessary to reduce the parasitic resistance during the development of the device, a policy on which component should be reduced and how should be reduced. And it was difficult to design a device to obtain desired characteristics.

Furthermore, in the conventional method, especially in an n-channel MOSFET, the impurity profile of the channel region fluctuates with the shortening of the gate length due to the abnormal diffusion of B injected into the channel. There is also a problem that is difficult.

Further, in the conventional evaluation method, the silicide-bulk contact resistance is not estimated, or even if the evaluation is performed, a silicide-bulk contact resistance is set on the silicon surface to obtain a silicide-bulk contact resistance. Since the effect of the bulk contact resistance has been estimated, this situation will be briefly described with reference to FIG.

Referring to FIG. 6, the n ⁺ type drain region 16 and n
^An estimated contact resistance component 21 is set on the surface of a ⁺ type source region (not shown). When the silicide electrode 17 is deepened, the silicide electrode 17, the n ⁺ type drain region 16 and the n ⁺ type source There is a problem in that it is not possible to use such as estimating an increase in parasitic resistance due to a decrease in the distance from the bottom of the region.

Accordingly, an object of the present invention is to provide a method for accurately evaluating each parasitic resistance component separately from each other using a device simulator.

[0019]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1. (1) In the semiconductor device evaluation method, the present invention performs a structural analysis of an insulated gate transistor by inverse modeling, and based on the result, based on a current-voltage characteristic in a linear state on a device simulator. To determine the sheet resistance of the channel region and the extension region of the source / drain region, and integrate the sheet resistance from one of the source / drain regions to the other to separately evaluate the parasitic resistance of the channel region and the extension region. It is characterized by.

As described above, inverse modeling (Inv
In other words, by performing an inverse analysis of the impurity profile of the real device from the electrical characteristics of the real device only by device simulation without using process simulation, the extended region of the source / drain region, that is, the LDD region, etc. The active impurity profile in the extension region can be determined with high accuracy, the sheet resistance distribution is determined based on the impurity profile, and the profile is integrated in the source-drain direction to separate the parasitic resistance component. Therefore, each parasitic resistance component can be accurately evaluated.

Further, by feeding back the evaluation result to a device design or device manufacturing process of an insulated gate semiconductor device, a device having desired characteristics can be manufactured with good reproducibility.

(2) Further, according to the present invention, there is provided a method for evaluating a semiconductor device, comprising the steps of: forming a silicide electrode on a source / drain region of an insulated gate transistor;
The parasitic resistance of the bulk contact region is characterized by using a device simulator and fixing the mobility of the silicide-bulk contact region to a fixed value.

As described above, by fixing the mobility of the silicide-bulk contact region to a constant value, the parasitic resistance of the silicide-bulk contact region can be accurately evaluated by using a device simulator. The accuracy of the analysis of the operation characteristics of the device or the prediction of the operation performance can be improved.

(3) According to the present invention, in the method of manufacturing a semiconductor device, the dose of the impurity into the extended region of the source / drain region and the annealing conditions are optimized based on the evaluation result of the above (1). And controlling the parasitic resistance of the extension region.

As described above, the dose amount of the impurity to the extended region of the source / drain region and the annealing conditions are optimized based on the evaluation result of each parasitic resistance component of each region in the above (1), whereby the extended region is obtained. A parasitic element such as a parasitic resistance or a parasitic capacitance of the region can be controlled according to a design value, so that desired operation performance can be obtained.

(4) According to the present invention, in the method of manufacturing a semiconductor device, the impurity concentration and depth of the source / drain region and the depth of the silicide electrode are optimized based on the evaluation result of the above (2). And control the parasitic resistance of the silicide-bulk contact region.

As described above, based on the evaluation result of the parasitic resistance of the silicide-bulk contact region (2), that is, the silicide-bulk contact resistance, the impurity concentration and depth of the source / drain region and the silicide electrode By optimizing the depth of the contact, the silicide-bulk contact resistance can be controlled as designed, thereby achieving the expected operating performance.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a method for evaluating a parasitic resistance of a MOSFET by inverse modeling according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. Before that, an inverse modeling method will be described. A brief description will be given. This inverse modeling is a method of performing an inverse analysis of an impurity profile based on the electrical characteristics of an existing device only by a device simulation without using a process simulation, and combining a plurality of Gaussian functions inside a device simulator to obtain an impurity peak. Parameters such as the concentration N _p , the peak position in the depth direction of the impurity, ie, the projection range R _p , or the decay, ie, the standard deviation ΔR _p in the depth direction of the impurity, are measured by the least square method to obtain the CV. The impurity profile is obtained in accordance with data such as characteristics.

In particular, in the case of the present invention, an extended region of the source / drain region which is difficult to obtain, that is, LD
A device simulator (Galine 3) was used to determine the impurity profile of the D region.

First, prior to the description of the inverse modeling procedure, a device for obtaining measured data is necessary.
The manufacturing conditions of the FET will be described. First, the phosphorus concentration was 4.0.
As 16 is applied to the surface of an n-type silicon substrate of × 10 ¹⁵ cm ^-3.
Channel doping is performed by ion implantation at an acceleration energy of 0 keV and a dose of 1.0 × 10 ¹³ cm ⁻² .

Next, after a gate oxide film having a thickness of 4.0 nm is formed by thermal oxidation, boron is deposited at 1 × 10 ²⁰ cm ^-3.
A doped polysilicon gate electrode is provided, and BF ₂ is added for 5.0 k using the polysilicon gate electrode as a mask.
Ion implantation is performed at a dose of 1.0 × 10 ¹⁴ cm ⁻² at an acceleration energy of eV to form a p ⁻ -type LDD region.

Next, using anisotropic etching, the Si
After a sidewall made of an O ₂ film is formed, boron is again applied at 5.0 keV using the sidewall as a mask.
Ion implantation at a dose of 2.0 × 10 ¹⁵ cm ⁻² at an acceleration energy of p ⁺ -type drain region and p ^+
After forming a ⁺ -type source region and then forming a silicide electrode made of CoSi _{2 on} the p ⁺ -type drain region and the p ⁺ -type source region, an interlayer insulating film is deposited on the entire surface, and a contact provided on the interlayer insulating film is formed. A metal contact electrode made of W and barrier metal TiN is formed through the hole.

Next, the p-channel type M thus formed
Using OSFET, gate and measure long channels of CV characteristics between the source and drain, i.e., I _d (drain current) in the device channel length of the degree the influence of the short channel effect hardly -V _g (gate voltage ) Characteristic back bias V
Measurement of _b dependency C _gd (capacitance between gate and drain) −V _g (gate voltage) Back bias V of characteristic Measurement of _b dependency _Applied voltage V _ds between source and drain is V _ds = −0.1
Performing I _d (drain current) -V _g (gate voltage) measurement of the gate length L dependence of characteristics of the case of the V.

Inverse modeling is performed based on such actual measurement data. First, the active impurity profile in the polycrystalline silicon gate electrode is adjusted from the above-described inversion layer capacitance of the CV characteristic using a device simulator. . This utilizes the fact that the difference between the gate oxide film thickness and the inversion capacitance of the CV characteristic is caused by the impurity profile in the gate electrode.

Next, V _{b of the} above I _d -V _g characteristics
From the dependence, matching of the channel profile in the channel region is performed using a device simulator. As a function set in the device simulator in order to obtain an impurity profile in this case, for example, the position in the depth direction of the channel region is used. When the a z, n _p exp - set to ^{_{[(z-R p) n /}} ΔR p n ], so as to more approximate to the measured data using the least squares method, the peak concentration of the impurity n _p, projected range The parameters R _p , standard deviation ΔR _{p in} the depth direction, and n are determined.

FIG. 2 (a) is a diagram showing the results of matching channel profiles. In each back bias _Vb , good agreement between the measured value shown by the solid line and the simulation result shown by the circle is shown. was gotten. In this case, the value of each parameter is as follows: peak concentration of impurities N _p = 8.003 × 10 ¹⁷ cm ⁻³ projection range R _p = 0.1142 μm standard deviation in depth direction ΔR _p = 0.083 μm n = 2.90.

Next, the V _b dependence of C _gd -V _g characteristics of the performs narrowing combined impurity profiles of the LDD region using a device simulator. This utilizes the fact that the expansion of the depletion layer accompanying the drain region changes due to the back bias _Vb . In this case, the function set in the device simulator to obtain the impurity profile of the LDD region is as follows. for example, the lateral diffusion of the Gaussian function and impurities, i.e., sets a combination of error function for evaluating the standard deviation [Delta] R _pt lateral (erfc).

FIG. 2B is a graph showing the results of adjusting the impurity profile of the LDD region. For each back bias _Vb , the measured values shown by the solid line and the simulation results shown by the circle are good. Good agreement was obtained.

3 (c) and 3 (d). FIG. 3 (c) is an overall impurity profile obtained by combining the above-described channel profile evaluation result and the LDD region impurity profile evaluation result. FIG.
(D) shows an I obtained by using a device simulator based on the entire impurity profile of FIG. 3 (a).
and the gate length L dependence of _d -V _g characteristics, a graph showing matching of the gate length L dependence of measured data of I _d -V _g characteristics,
Since good agreement is obtained for each gate length L, it can be understood that the inverse analysis of the impurity profile by the inverse modeling is very accurate.

Next, a sheet resistance distribution is obtained by using a device simulator based on the entire impurity profile of FIG. 3 (a) in which the accuracy is ensured in the comparison of the actually measured data. In this case, in the device simulator, each region in the silicon substrate is finely divided into meshes, and a resistance value based on the linear IV characteristic based on the impurity concentration in each fine mesh region is calculated. The sheet resistance distribution is obtained by integrating in the vertical direction.

FIG. 4E shows the sheet resistance distribution obtained in this manner.
FIG. 4C is a diagram showing the impurity profile shown in FIG. 3C together with the gate length L of the polycrystalline gate electrode being L = 0.2 μm and the gate bias V _g being −
The simulation result at the time of 1.0V, -1.5V, and -2.0V is shown.

As can be seen from the figure, a polycrystalline silicon gate electrode having a length of 0.2 μm is approximately 0.06 μm on the left and right sides.
m (= 60 nm), the LDD region enters immediately below the polycrystalline silicon gate electrode, and the effective channel length is about 0.08 μm.
m can be understood, and considering the bending point and the like of the sheet resistance distribution, the ranges indicated by arrows in the figure are the diffusion resistance R _{ac in the} extension region and the sheet resistance R _{sh in the} extension region.

Next, by integrating this sheet resistance distribution from the source region to the drain region in the device simulator, the resistance distribution at each position is obtained, and each parasitic resistance component is separated.

FIG. 4 (f) is a diagram showing the integration result of the sheet resistance together with the impurity profile shown in FIG. 3 (c).
The ON resistance R _ON of the channel type MOSFET is estimated to be 2700Ω, and is evaluated by superimposing the range of the diffusion resistance R _{ac and} the range of the sheet resistance R _sh based on the bending point of the sheet resistance distribution shown in FIG. Then, the sheet resistance R _sh is about 1
Since the range is from 00Ω to about 300Ω, R _sh sh2
00 Ω and the diffusion resistance R _ac is in the range of about 300 Ω to about 800 Ω, so that R _ac ≒ 500 Ω. Further, the resistance between 0 and 100Ω can be evaluated as the resistance of the source / drain region injected after the formation of the sidewall.

In addition, for the ON resistance R _ON = 2700Ω, the value of the drain region of the resistance in FIG. 4F is 250Ω, and the difference of 200Ω can be evaluated as the silicide-bulk contact resistance. This is silicide-
This is because the bulk contact resistance cannot be expressed in the form of sheet resistance.

Therefore, the source / drain regions are
If provided symmetrically, R_shAnd R _acExists on the left and right
So that the extension area acts on the entire device
The parasitic resistance due to the sheet resistance is 2 × R_sh≒ 400Ω
And the parasitic resistance caused by the diffusion resistance in the extension region.
Resistance is 2 × R_ac≒ 1000Ω and silicide
-Parasitic resistance due to bulk contact resistance is
Can be evaluated as 200Ω.

Based on the evaluation results, the effect of each parasitic resistance component on the operating characteristics and operating performance of the device is evaluated, and the results are fed back to the manufacturing conditions in the device design and device manufacturing process, whereby the device having the expected characteristics is obtained. Can be manufactured with good reproducibility.

For example, in a small MOSFET, L
Since the impurity profile in the DD region has a great effect on the operation characteristics and operation performance of the device, the ions used to form the LDD region based on the results of the separation of the parasitic resistance component based on the result of such inverse modeling are described. The implantation conditions and the subsequent annealing conditions for activating the impurities can be optimized.

Next, a method of evaluating silicide-bulk contact resistance, which has not been substantially estimated in the past, will be described. When a device simulator (Galine 3) is used, analysis can be performed by setting the mobility (mobility) as a fixed region, so that the mobility in the silicide-bulk contact region is fixed to μ _sb and n is the carrier. The density and Q are equal to the elementary charge (= 1.6 × 10
^-19 coulomb) and the electric field in the silicide-bulk contact region is E, and the silicide-bulk contact resistance, that is, the silicide-bulk contact is obtained by using a current equation represented by I = n · Q · _μsb · E. The parasitic resistance of the region can be expressed on a device simulator.

Referring to the thus obtained silicide-bulk contact resistance and evaluating the integral curve of the resistance in FIG. 4F, if the sheet resistance R _{sh in the} extension region is evaluated.
And the diffusion resistance R _ac can be evaluated more accurately.

Also, by using this method for evaluating the silicide-bulk contact resistance, the parasitic resistance is increased due to the fact that the silicide electrode is deepened and the distance between the silicide electrode and the bottom of the source / drain region is reduced. It is possible to accurately estimate an increase in parasitic resistance due to a reduction in the gate electrode and element separation distance.

By feeding back the method of evaluating the silicide-bulk contact resistance to the determination of device design or device manufacturing conditions, for example, the depth of the silicide electrode, the depth of the source / drain regions and the impurity concentration can be optimized. As a result, the influence of the parasitic resistance can be controlled, so that a device having desired characteristics can be manufactured with good reproducibility.

The embodiment of the present invention has been described above. However, the embodiment is only for explaining one method of the present invention, and is not limited to the configuration and conditions described in the embodiment. Can be changed. For example, in the above inverse modeling, a p-channel MOSFET
However, it goes without saying that the present invention is similarly applied to an n-channel MOSFET.

In the above embodiment, inverse modeling is performed for a MOSFET formed on a silicon wafer. However, a MOSFET formed on an insulating substrate and formed with a silicon thin film, that is, an SOI-type MOSFET is formed.
The present invention is also applied to a MOS. In that case, the present invention is not limited to a normal MOSFET, and is also applied to a simulation of a so-called TFT and another type of insulated gate semiconductor device.

In the simulation of the above embodiment, the resistance distribution in the linear state is estimated. However, this method is also applied to the analysis of the saturated state, and is obtained by the inverse analysis in the inverse modeling. By using the obtained impurity profile and separately setting the relationship between the impurity concentration and the resistance value in the saturated state, it is possible to analyze the saturated state.

Further, the function form used in the inverse modeling is not limited to a simple Gaussian function, and if further accuracy is required, any appropriate function can be used.

[0057]

According to the present invention, since the parasitic resistance components are separated based on the impurity profile of the real device obtained by inverse modeling, the contribution of each parasitic resistance component can be accurately evaluated. become,
Further, by feeding back the evaluation result to the design and manufacturing process of a next-generation semiconductor device that requires more precise impurity distribution control, a semiconductor device having desired characteristics can be manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 shows IV characteristics and C in an embodiment of the present invention.
FIG. 9 is an explanatory diagram of a result of adjusting the −V characteristics.

FIG. 3 is an explanatory diagram of an impurity profile and an inverse modeling result obtained in the embodiment of the present invention.

FIG. 4 is an explanatory diagram of separation of a sheet resistance distribution and a parasitic resistance in the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional parasitic resistance evaluation method.

FIG. 6 is an explanatory diagram of a conventional method for evaluating contact resistance.

DESCRIPTION OF SYMBOLS 11 p-type silicon substrate 12 gate oxide film 13 polycrystalline silicon gate electrode 14 LDD region 15 side wall 16 n ⁺ type drain region 17 silicide electrode 18 silicide-bulk contact region 19 interlayer insulating film 20 metal contact electrode 21 Estimated contact resistance component

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB20 CC01 DD84 GG09 HH16 HH20 4M106 AA07 AB01 AB03 AB04 BA14 BA20 CA01 CA10 CA11 CA12 CB02 CB30 DJ20 5F040 DA22 DC01 EF02 EF03 EH02 FB02 FC11 FC19 FC21

Claims (4)

[Claims] An insulated gate transistor is subjected to a structural analysis by inverse modeling, and a sheet resistance of an extended region of a channel region and a source / drain region is determined on the basis of a result of the analysis on a device simulator based on a current-voltage characteristic in a linear state. And evaluating the parasitic resistance of the channel region and the extension region separately by integrating the sheet resistance from one of the source / drain regions to the other. 2. The method according to claim 1, further comprising: a silicide electrode provided in a source / drain region of the insulated gate transistor.
A method for evaluating a semiconductor device, comprising: evaluating a parasitic resistance of a bulk contact region by using a device simulator while fixing the mobility of the silicide-bulk contact region to a constant value. 3. The parasitic resistance of the extension region is controlled by optimizing the dose amount of impurities to the extension region of the source / drain region and the annealing condition based on the evaluation result of claim 1. A method for manufacturing a semiconductor device. 4. The method according to claim 2, wherein the impurity concentration and depth of the source / drain region and the depth of the silicide electrode are optimized to control the parasitic resistance of the silicide-bulk contact region. A method for manufacturing a semiconductor device, comprising: