JP2000132456A - Cache memory device for parallel computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of the whole system by reducing the overhead of a memory access process by changing methods for consistency management according to data. SOLUTION: Cache memories 3-1 to 3-n are provided in cache memory devices 2 attached to respective processors 1 of the parallel computer and different consistency management systems are assigned to the respective cache memories 3-1 to 3-n. For example, an MEI protocol is assigned to one cache memory and data which is not referred to at all and expelled from the cache memory is accessed by using the cache memory of the MEI protocol. Further, it may be possible to specify protocols by the cache lines of the cache memories 3 by providing bits P specifying protocols for the cache lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device for speeding up memory access, and more particularly, to a cache memory device attached to a processor of a parallel computer connected by an interconnection line.

[0002]

2. Description of the Related Art A cache in a shared memory type parallel computer has a problem of coherency management of a cache as compared with a cache of a single processor system. Here, a system in which a processor and a cache are connected by a shared bus as shown in FIG. 36 will be described as an example.
FIG. 36 is a diagram illustrating a configuration example of a parallel computer, in which processors 101 to 10n share a shared bus 201 through a cache.
Connected to. A memory 203 is also connected to the shared bus 201, and the memory 203 is used in common by all the processors 101 to 10n. Parallel computers include:
There is not only such a shared bus / shared memory type but also a shared memory type of a distributed system, but here, for simplicity, only this type will be described.

In FIG. 36, it is assumed that a cache 101a associated with a processor 101 already has a copy of a memory, and another processor 102 attempts to access the same data. For a single processor,
The cache associated with the processor 102 may simply store a copy of the data on the memory in the cache, but a problem arises if a similar method is used in the parallel computer shown in FIG. Now, after the data is stored in the cache 102a attached to the processor 102, the processor 1
Suppose that 01 has updated the data. If the cache is a write-back cache, the updated data is not written back to the memory but is stored in the cache 101a.
Accordingly, processor 102 and processor 102
Cannot know that the data has been updated. Therefore, the processor 102
Therefore, even if a read request for the data is issued, the cache 102a attached to the processor 102 continues to return the old data before update, which is held by itself, forever.

In such a state, the processor 10
1 and the cache 101 associated with the processor 101
An inconsistency may occur between the value referenced by a and the value referenced by the processor 102 and its associated cache 102a, resulting in an operation different from what the programmer expects. In order to prevent such a situation, a mechanism for matching data between a plurality of caches is required. In order to match the data, the data on the cache or the data on the memory must have a state and cooperate with another cache according to the state. There are various types of ways of giving this state and ways of cooperation.

In general, a method is used in which a state is provided in a cache and information is exchanged with another cache according to the state. The description will be made by taking the MOESI protocol as an example. As an example, FIG.
Consider a parallel computer like Since it is a shared bus system, when a cache associated with a certain processor performs memory access, the operation can be confirmed by another processor (a snoop cache system).
The cache can have a state for each line, and the state is M (Modified), O (Owned), E
(Exclusive), S (Shared), and I (Invalid).

The processor 101 issues an access request,
If the data does not exist in the cache 101a, the cache 101a associated with the processor 101
Reads the data from the main memory 202 and stores it. Then, a state of E (Exclusive) is given to the line. Next, when the processor 102 attempts to read the same data, the cache associated with the processor 102 performs the same operation as described above. At this time, since the cache 101a attached to the processor 101 knows that the data is held by itself, it changes its own data state to S (Shared: data sharing) and Signals that you own it. The cache 102a attached to the processor 102 changes the state of the read data to S (Shar
ed) and save.

In this state, if the processor 101 attempts to write the data, the processor 1
First, the cache 101a attached to 01 checks the state of data. Then, since the state is S (Shared), it is possible to know that another cache has the same data. Therefore, in order to maintain consistency, the cache 101a attached to the processor 101 requests another cache to invalidate the data or notifies the data to be updated before updating the data. in this way,
Coherency can be maintained by interacting with other processors depending on the state of the cache line.

[0008]

However, in the prior art, the same consistency management method is applied to all data, and there is a possibility that the processing may be delayed depending on the data. For example, suppose that there is data that one processor A frequently writes, and another processor reads it one at a time. When a processor other than the processor A refers to the cache, the cache associated with the processor A has a copy. Therefore, the cache associated with the processor A changes the data to the S state (shared). Have to be done. However, in this case, since the other processors no longer refer to the data, the consistency management processing is useless. When such useless processes overlap, the execution of the program becomes unnecessarily slow.

The present invention has been made in view of the above circumstances, and has as its object to change the method of consistency management according to data so that appropriate consistency management can be performed. Is to reduce the overhead of the memory access process and improve the performance of the entire system.

[0010]

According to the present invention, the following methods (1) and (2) are used in order to use a different consistency management method for each data. A method of performing consistency management between a plurality of caches is referred to as a cache protocol (hereinafter, abbreviated as a protocol as necessary).

(1) A plurality of cache memories are prepared in a cache memory device associated with each processor of a parallel computer, and a different consistency management method is assigned to each cache memory (the same consistency management method is assigned. May be more than one). That is, FIG.
As shown in (a), a plurality of cache memories 3-3 are stored in a cache memory device 2 associated with each processor 1.
1 to 3-n and the cache control devices 4-1 to 4-1n are provided, and each of the cache memories 3-1 to 3-n performs a separate consistency management operation.

(2) Only one cache memory is prepared without dividing the cache memory so that it is possible to distinguish which consistency management method (protocol) is used for each data. Therefore, in the present invention, it is possible to distinguish which consistency management method is used for each cache line. That is, as shown in FIG. 1B, in the cache memory device 2 associated with each processor 1,
One cache memory 3 and a cache control device 4 are provided, and a bit P for designating a protocol is provided for each cache line of the cache memory 3 so that a protocol can be designated for each cache line. In this method, the cache control device 4 operates by determining what consistency management method is used for each line. By performing the above (1) and (2), the consistency management method (protocol) can be used properly.

If it is known in advance by a program running on the processor which data should use which consistency management method, in the above (1) and (2), which cache memory should be used by the processor,
Alternatively, it is possible to specify which protocol is assigned to the cache line. However, since a consistency management method suitable for data is not always clear by a program, a method for automatically determining the consistency management method is required. Therefore, a reference counter is added to each cache line. The reference counter indicates how much the cache line has been referred to by the processor, and can be used as a reference for selecting an appropriate consistency management method by referring to this value.

In order to further select the appropriate consistency management method automatically by the hardware, a system which assumes a specific protocol is proposed. In particular,
Using a combination of a protocol that does not allow data sharing with another cache memory (for example, MOESI, MESI protocol) and a protocol that allows data sharing with another cache memory (for example, MEI protocol), either of them is automatically performed. Determine whether to use the consistency management method.

For this reason, the following three methods can be used. (1) Mainly use the "protocol that does not allow data sharing with other cache memories", and use the "protocol that allows data sharing with other cache memories" only for data that is difficult to refer to. (2) Mainly use the "protocol that allows data sharing with other cache memories", and use only the frequently referenced data "protocol that does not allow data sharing with other cache memories". (3) The criteria for determining which protocol to use is adaptively changed.

For example, in the present invention, MOESI or M
Combine the two of the ESI protocol and the MEI protocol. Then, a method of dividing into cache memories using respective protocols as in the above (1) and a method of adding a bit indicating which protocol is used for each cache line as in the above (2) are consistently used. Perform sex management. In either method, the above-described reference counter is added for each cache line.
Using this reference counter, MOES
There are two main methods for selectively using the I / MESI protocol and the MEI protocol. One is to use the MOESI / MESI protocol mainly and use the MEI protocol only when a specific condition is satisfied. The other is to use the MEI protocol mainly and use the MEI protocol mainly and only when a specific condition is satisfied. MOE
This is a method using the SI / MESI protocol.

In order to realize the above, it is only necessary to determine data for which the S state need not be created. For this purpose, first, a table in which addresses can be registered is prepared. Next, the reference counter is examined to find data that is evicted from the cache memory without being referenced at all. The address of the found data is registered in the previous table, and the MEI protocol that does not create the S state will be used from the next time. In this method, the cache memory of (1) is
The same method can be applied to both the method of preparing one and the method (2) of allowing a protocol to be selected for each cache line. In order to realize the above, the reverse of the above method may be performed. That is, a table in which addresses can be registered is prepared, and the reference counter is checked. At some point, data that is referenced from the cache memory after a certain number of references (this is set to a fixed number c) is found and registered in a table. MOESI / MES using S state from next time
I protocol is used. Again, as in the previous method,
A method of preparing two cache memories of the above (1),
The method (2) can be applied to both of the methods of allowing a protocol to be selected for each cache line.

This method can be further extended.
In other words, the reference value c for determining whether or not a certain number of references have been made is fixed, but is dynamically changed. By dynamically changing the reference value c, differences due to cache size and program characteristics can be absorbed. As a specific method for dynamically changing, in the present invention, in the above (1), the MOE
In the case where a collision occurs in a cache using the SI / MESI protocol, the above-mentioned reference value c is incremented by 1, and when a collision occurs in a cache using the MEI protocol, a method of subtracting -1 from the above-mentioned reference value is used. This applies only to the method using two cache memories.

[0019]

Embodiments of the present invention will be described below. (1) First Embodiment FIG. 2 is a diagram showing a configuration of a first embodiment of the present invention.
In the system shown in FIG. 1, a plurality of processors 11 are connected to a shared bus 12 via a cache memory device 20,
The memory 13 constitutes a shared memory system connected to the shared bus 12. In the cache memory device 20, two cache memories 21, 22 and two cache control devices 21a, 22a (hereinafter, referred to as control devices) are arranged. Each cache memory 2
The combination of the control devices 21 and 22 and the control devices 21a and 22a works in the same manner as a normal cache. That is, when viewed from the memory 13 side, it looks as if a plurality of independent cache memory devices are connected.

Each of the cache memories 21 and 22
Is constituted by, for example, a cache line as shown in FIG. Note that there are a full associative method, a set associative method, and a direct map method in the cache configuration method. FIG. 3 shows the direct map method, and [V] is valid / invalid (1: vali
d: valid / 0: invalid (invalid), [Status]
Is a bit indicating the state of the cache, for example, MO
In the case of the cache of the ESI protocol, S (1: sh
ared / 0: non-shared) and D (1: dirty / 0: clean) bits, each bit state including the above [V] and MO
The correspondence of the ESI states is as shown in FIG. 4A (where [X] represents an arbitrary value).

In the case of the cache of the MEI protocol, the cache consists of D (1: dirt / 0: clean) bits,
FIG. 4B shows the correspondence between each bit state including the above [V] and the state of the MEI. Control devices 21a, 22
“a” controls the movement of the cache, and performs resolution of a reference request from a processor, reading of a memory, confirmation of a cache state, storage of data in the cache, and the like.

In FIG. 2, cache memories 21 and
2 are assigned different consistency management schemes. For example, MOES is stored in one cache memory 21.
I protocol and the other cache memory 22
To the MEI protocol. The cache memory 22 is allocated to data that does not need to be referred to at all and is not required to create an S state, such as data that is evicted from the cache memories 21 and 22, and the S state is assigned to data that may be frequently referred to. The data that needs to be
The cache memory 21 is allocated. If a program running on the processor 11 knows in advance which data should use which consistency management method, the processor 11 specifies which cache memory to use.

As an example of specifying which cache memory is to be used, there is a case where read-ahead control is performed. When performing prefetching, there is a low probability that the prefetched data will be used. Therefore, when performing prefetching, the processor notifies the cache that the prefetching is performed, and executes S
(Shared) Do not create a state. Thereby, it is possible to avoid a consistency management process that may be wasted.

FIG. 5 is a diagram showing a configuration example in which this embodiment is applied to prefetch control. In FIG. 5, reference numeral 11 denotes a processor, and reference numeral 14 denotes a prefetch control unit. The prefetch control unit 14 outputs a prefetch data notification when the processor 11 prefetches data. 21 is a cache memory of the MOESI protocol, 22 is a cache memory of the MEI protocol, 21a and 22a are cache control devices, 15 is a cache selection control unit, 16 is a selector, and the cache selection control unit 15 is output by the prefetch control unit 14. Based on the pre-read data notification, the selector 16 is switched to select which of the caches 21 and 22 to use. For example, when the prefetch data is notified,
Since the read-ahead data has low reliability, the cache selection control unit 15 switches the selector 16 to the MEI protocol cache memory 22 side, and issues a read request to the shared bus 12 via the cache memory 22.

FIG. 6 is a flowchart showing the operation at the time of memory reading, and the operation of the embodiment of FIG. 5 will be described with reference to FIG. When the processor accesses the memory, the cache is first searched to determine whether or not the cache has been hit (steps S1 and S2). If the cache hits, the process proceeds to step S10, and the data read from the cache is returned to the processor. If no hit is found in the cache, the process proceeds to step S3, and it is checked whether the cache is a prefetch. In the case of pre-reading, the process proceeds to step S11, where a read request is issued to the shared bus via the cache memory 22 of the MEI protocol.
Data is stored in the cache memory 22 as 1 (valid) and D = 0 (clean).

If it is not prefetching, step S
4, go to MOESI protocol cache memory 2
1 and issues a read request to the shared bus. In step S5, it is checked whether or not another cache memory has data. If the other cache memory does not have data, V = 1 (valid), S = 0 (non-shared),
Assuming that D = 0 (clean), the data is stored in the cache memory 21, and the procedure goes to step S11. If the other cache memory has the data, the process goes to step S6 to check whether the data is dirty. If the data is dirty, go to step S7, where V = 1 (valid
), S = 1 (shared) and D = 1 (dirty), the data is stored in the cache memory 21, and step S10
go to.

If the data is not dirty,
Go to step S8, where V = 1 (valid), S = 1 (shar
ed), D = 0 (clean) and the cache memory 21
And the process goes to step S10. As described above, according to the present embodiment, two cache memory devices having different protocols are provided, and data that is evicted from the cache memory without being referred to at all is assigned to a cache of a protocol having no S state. Therefore, useless consistency processing is not performed, and the processing speed can be improved.

(2) Embodiment 2 FIG. 7 is a diagram showing a configuration of a second embodiment of the present invention. In FIG. 7, a plurality of processors 11 are connected to the shared bus 12 via the cache memory device 20 as described above,
The memory 13 constitutes a shared memory system in which the shared memory 12 is connected to the shared bus 12, and the cache memory 21 and the cache control device 2
1a are arranged one by one. This cache memory is constituted by cache lines as shown in FIG. 8, and is different from the cache line of FIG. 3 in that a bit for designating a protocol is added to each cache line. The number of bits varies depending on the number of protocols to be handled.

That is, in the present embodiment, a protocol can be designated for each cache line. Therefore, in this embodiment, only one cache memory and one control device are provided for one processor. In this embodiment, all the cache operations include an operation of "checking a protocol specification bit and determining which protocol to use" before a normal cache operation. After that,
The cache operation is performed according to the selected protocol.

For example, the MEI protocol is assigned to data that is evicted from the cache memory 21 without being referred to at all by the protocol designation bit, and the MOESI protocol is assigned to the data that may be frequently referred to by the protocol designation bit. . If a program running on the processor 11 knows in advance which data should use which consistency management method, the processor 11 specifies which protocol to use as described above.

Hereinafter, a specific example of the present embodiment will be described by taking the above-described prefetch control as an example. FIG. 9 shows a specific configuration example in which this embodiment is applied to prefetch control. In FIG.
Reference numeral 11 denotes a processor, and reference numeral 14 denotes a prefetch control unit. The prefetch control unit 14 outputs a prefetch data notification when the processor 11 prefetches data. Reference numeral 21 denotes a cache memory, reference numeral 21a denotes a cache control device, and reference numeral 17 denotes a protocol selection control unit. The protocol selection control unit 17 selects a protocol of a cache line based on a prefetch data notification output from the prefetch control unit 14. For example, when the prefetch data is notified, the protocol selection control unit 17 sets the protocol to MEI and issues a read request to the shared bus as described above.

FIG. 10 is a flowchart showing the operation at the time of memory reading, and the operation of this embodiment will be described with reference to FIG. When the processor accesses the memory, the cache is first searched to determine whether or not the cache has been hit (steps S1 and S2). If the cache hits, the process proceeds to step S10, and the data read from the cache is returned to the processor. If no hit is found in the cache, the process proceeds to step S3, and it is checked whether the cache is a prefetch. In the case of pre-reading, the procedure goes to step S11, and a read request is issued to the shared bus with the protocol set to MEI. At step S12, V = 1 (valid), D
= 0 (clean) and P = 0 (MOESI: 1 / MEI: 0) and store data in the cache memory 21 (S bit is P
Is effective only when = 1, and is ignored when P = 0).

If it is not prefetching, step S
4 and issues a read request to the shared bus with the protocol being MOESI. In step S5, it is checked whether or not the other cache memory has data. If the other cache memory has no data, V = 1 (va
lid), S = 0 (non-shared), D = 0 (clean), P
= 1 (MOESI), the data is stored in the cache memory 21, and the process goes to step S10. If the other cache memory has the data, the process goes to step S6 to check whether the data is dirty. If the data is dirty, go to step S7, where V = 1 (valid
), S = 1 (shared), D = 1 (dirty), P = 1 (M
OESI), the data is stored in the cache memory 21, and the process goes to step S10. If the data is not dirty, the process goes to step S8 and V = 1 (valid
), S = 1 (shared), D = 0 (clean), P = 1 (M
OESI), the data is stored in the cache memory 21, and the process goes to step S14.

As described above, according to this embodiment, a protocol can be designated for each cache line, and a protocol having no S state is designated for data that is evicted from the cache memory without being referred to at all. Therefore, as in the first embodiment, unnecessary consistency processing is not performed, and the processing speed can be improved. Further, since only one cache memory and one cache control device are required for each processor, the configuration can be simplified as compared with the first embodiment.

(3) Embodiment 3 In this embodiment, a reference counter is added to the cache memory device described in Embodiments 1 and 2. The configuration of the present embodiment is the same as that of FIGS. 2 and 7 described above.
Is connected to the shared bus 12 through
The memory 13 is connected to the shared bus 12 and constitutes an Inari memory system. Each cache memory device 20 is provided with a plurality of cache memories or one cache memory. In the present embodiment, as shown in FIGS.
A reference counter indicating the number of times data stored in the line is referred to is added to each line. 11 and 12 correspond to FIGS. 3 and 8 except that a reference counter is added.
It is the same as FIG.

The value of this reference counter is cleared to 0 when data is stored in the cache, and is incremented by one each time reading / writing is performed by the processor. The value of the reference counter can be read by the processor 11. Therefore,
Based on the value of the reference counter, the processor 11 can know the data that is evicted from the cache memories 21 and 22 without being referred to at all and the (address of) the data that may be frequently referred to. A consistent consistency management method.

For example, as shown in the first embodiment, the cache memory 22 is allocated to data that is evicted from the cache memories 21 and 22 without being referred to at all, and data that may be frequently referred to is assigned. , It is possible to allocate the cache memory 21 and, as in the second embodiment, to specify which protocol the processor 11 uses. As mentioned above, providing a reference counter helps the program determine the appropriate protocol for the data.

(4) Fourth Embodiment FIG. 13 shows a combination of a cache memory using the MOESI protocol and a cache memory using the MEI protocol as a coherence management method, and adding a reference counter to a cache line of each cache memory. Further, an embodiment in which an address table for storing addresses is added is shown. The configuration of the present embodiment is the same as that of FIG. 2 described above, and constitutes a shared memory system in which a plurality of processors 11 are connected to a shared bus 12 via a cache memory device 20 and a memory 13 is connected to the shared bus 12. are doing. The cache memory device 20 includes two cache memories 21 and 22 and two cache controllers 21a and 21 with different protocols.
2a is arranged.

FIGS. 14 and 15 show cache lines in this embodiment. FIG. 14 shows a cache line of the MOESI protocol, and FIG. 15 shows a cache line of the MEI protocol. As shown in FIG. 14, the cache line of the MOESI protocol
S (shared) as a bit corresponding to [state] shown in FIG.
/ Non-shared), D (dirty / clean) bits and V
A (valid / invalid) bit and a reference counter are added, and the cache run of the MEI protocol has D (dirty / invalid) as a bit corresponding to the [state] shown in FIG. 12 as shown in FIG. clean), V (valid / invalid) bits, and a reference counter.

The cache memory device of this embodiment has an address table 23 for storing addresses. FIG. 16 shows the contents of each entry of the address table 23. As shown in FIG.
3 is composed of V (valid / invalid) and address fields. And the cache memory 2
When data is expelled from 1 and 22, the reference counter is referred to, and if the value is 0, the address of the data is registered in the address table 23. Later, when a request for the same address occurs, the address is registered in the address table 23,
It is accessed using a cache that uses the I protocol. In this way, data that is not often referenced is stored in the ME.
By storing in the cache using the I protocol, the S state can be reduced and the overhead of consistency management can be reduced.

FIG. 17 is a diagram showing a specific configuration example of this embodiment. In FIG. 17, 11 is a processor, 21 is M
OESI protocol cache memory, 22 is MEI
The cache memory of the protocol, 21a and 22a are cache control devices. Note that the cache memory 21,
“R” of 22 indicates a reference counter. 1
Reference numeral 5 denotes a cache selection control unit. The cache selection control unit 15 is provided with the above-described address table 23 and address registration means 24.
Calculates the address of data that is evicted from the cache memories 21 and 22 without being referred to at all based on the value of the reference counter, and registers the address in the address table 23. Then, the cache selection control unit 15 refers to the address table 23 when a memory request is issued, and if the address is registered in the address table 23, the selector 16 uses the selector 16 to set the cache memory 2 of the MEI protocol.
2 and the cache memory 22 of the MEI protocol is selected.
Send a read request to the shared bus via

FIGS. 18 and 19 are flow charts showing the operation at the time of memory reading in this embodiment. FIG. 20 determines whether to use the cache memory using the MOESI protocol or the cache memory using the MEI protocol. 5 is a flowchart, and the operation of the present embodiment will be described with reference to FIG. When the processor accesses the memory, the cache is first searched to determine whether or not the cache has been hit (steps S1 and S2). If the cache hits, the reference counter is incremented by one in step S15. Then, the data read from the cache is returned to the processor. If no hit is found in the cache, the process proceeds to step S3, and the cache selection control unit checks whether the address is registered in the address table.

If the address is registered in the address table, the process goes to step S16, where a read request is issued to the shared bus via the MEI protocol cache memory 22, and in step S17, V = 1 (valid),
The data is stored in the cache memory 22 as D = 0 (clean), and in step S18, the reference counter is cleared to 0 and the flow proceeds to step S14. If the address is not registered in the address table, the process proceeds to step S4, and a read request is issued to the shared bus via the cache memory 21 of the MOESI protocol. That is, as shown in FIG. 19, the cache selection control unit uses the MEI protocol according to whether the address is registered in the address table,
Select whether to use the SI protocol.

In step S5, it is checked whether another cache memory has data. If the other cache memory has no data, V = 1 (valid
), S = 0 (non-shared) and D = 0 (clean), the data is stored in the cache memory 21, and the process goes to step S10. If the other cache memory has the data, the process goes to step S6 to check whether the data is dirty. If the data is dirty, go to step S7, where V = 1 (valid), S = 1 (share
d), D = 1 (dirty), and the cache memory 21
And the process goes to step S10.

If the data is not dirty,
Go to step S8, where V = 1 (valid), S = 1 (shar
ed), D = 0 (clean) and the cache memory 21
And the process goes to step S10. Step S
In step 10, the reference counter is cleared to 0, and in step 11, it is checked whether data has been evicted from the cache. If data has not been evicted from the cache, the process proceeds to step S14.
If data has been flushed, it is checked in step S12 whether the reference counter of the flushed data is zero. Reference counter is 0
If not, go to step S14. If the reference counter is 0, go to step S13.
The address of the data to be evicted is registered in the address table, the process goes to step S14, and the read data is returned to the processor.

(5) Fifth Embodiment FIG. 21 is a diagram showing a configuration of a fifth embodiment of the present invention. In the present embodiment, the fourth embodiment is applied to the second embodiment. The protocol is specified for each cache line. In the present embodiment, a plurality of processors 11 are connected to a shared bus 12 via a cache memory device 20 as shown in FIG.
Takes the form of a shared memory system connected to the shared bus 12, and a cache memory 21 and a cache control device 21 a are respectively arranged in a cache memory device 20.

In this embodiment, the cache memory 21
Are constituted by cache lines as shown in FIG. As shown in FIG. 22, the cache line has S (shared / non-shared) and D (dirty / clean) bits and V (valid / invalid) as bits corresponding to the [state] shown in FIG. ) And a P (MOESI / MEI) bit indicating the type of protocol are provided, and a reference counter is added.
The same operation as in the third embodiment is performed. The S bit is P =
It is valid only when 1 and ignored when P = 0.

The cache memory device of this embodiment is provided with an address table 23 for storing addresses, as shown in FIG. The contents of each entry of the address table 23 are configured as shown in FIG. 16 similarly to the fourth embodiment, and are composed of V (valid / invalid) and address fields. As described above, when data is evicted from the cache memory, the reference counter is referred to. If the value is 0, the address of the data is registered in the address table 23.
Later, when a request for the same address occurs, if the address is registered in the address table 23, the MEI
Accessed using a protocol, the protocol selection bit P of the cache line is set to the MEI protocol. In this way, by setting data to be evicted without being referred to using the MEI protocol, the S state can be reduced, and the overhead of consistency management can be reduced.

FIG. 23 shows a specific configuration example of this embodiment. In FIG. 23, 11 is a processor, 21 is a cache memory, 21a is a cache control device, 17 is a protocol selection control unit, and the protocol selection control unit 17 is provided with the above-mentioned address table 23 and address registration means 24. The address registration unit 24 obtains the address of the data that is evicted from the cache memory 21 without being referred to at all based on the value of the reference counter, and registers the address in the address table 23. Then, when a memory request is generated, the address table 23 is referred to, and if the address is registered in the address table 23, the ME is added to the cache line of the cache memory 21.
Set the I protocol.

FIGS. 24 and 25 are flow charts showing the operation at the time of memory reading, and the operation of this embodiment will be described with reference to FIG. The MOESI protocol and ME
The process of determining which of the I protocols to use is the same as in FIG. The operation of this embodiment is the same as that described in the flowcharts of FIGS. 18 and 19, and the operation of this embodiment will be described below. The processing in steps S1 to S3 is the same as that in FIG. 18 described above. The cache is searched and it is checked whether or not the cache has been hit. If the cache has been hit, the reference counter is incremented by one in step S15. Then, the data read from the cache is returned to the processor. If no hit is found in the cache, it is checked whether the address is registered in the address table (steps S1 to S3).

If the address is registered in the address table, a read request is issued to the shared bus with the protocol being MEI, and V = 1 (valid) and D = 0 (cl
ean), the data is stored in the cache memory 21 as P = 0 (MEI), the reference counter is cleared to 0, and the procedure goes to step S14 (steps S16 to S18). If the address is not registered in the address table, the process goes to step S4 and the protocol is set to MOE.
A read request is issued to the shared bus as SI. In step S5, it is checked whether the other cache memory has data. If the other cache memory has no data, V = 1 (valid), S = 0 (non-share)
d), D = 0 (clean), P = 1 (MOESI), store the data in the cache memory 21, and go to step S10. If another cache memory has data, it is checked in steps S6 and S7 whether the data is dirty. If the data is dirty, V = 1
(Valid), S = 1 (shared), D = 1 (dirty), P
= 1 (MOESI), and store the data.
go to.

If the data is not dirty,
In step S8, V = 1 (valid), S = 1 (shar
ed), data is stored as D = 0 (clean), and P = 1 (MOESI), and the process goes to step S10. The processing after step S10 is the same as that in FIG. 19 described above. The reference counter is cleared to 0, it is checked whether data has been evicted from the cache, and if data has not been evicted from the cache, the data is read out to the processor. Returns the data. Also, if data eviction occurs,
It is determined whether the data reference counter is 0. If the reference counter is not 0, the process proceeds to step S14.
And if the reference counter is 0,
The address of the data to be evicted is registered in the address table, and the read data is returned to the processor.

(6) Sixth Embodiment This embodiment has the same configuration as the fourth embodiment. The overall configuration is the same as that of FIG.
4 and the cache line shown in FIG. In this embodiment, the address table 23 is prepared similarly to the fourth embodiment. Although the contents of the entry are the same as those in FIG. 16, in the present embodiment, when the value of the reference counter is larger than a predetermined constant value c, the address of the data is registered in the address table. That is, when data is evicted from the cache memory, the reference counter is referred to, and if the value is equal to or greater than a certain value c, the address of the data is stored in the address table 23
Register with. Then, when a request for the same address occurs later, if the address is registered in the address table 23, it is accessed using a cache using the MOESI protocol. In this way, by storing frequently referenced data in a cache using the MOESI protocol, the S state can be used appropriately.

FIG. 26 is a diagram showing a specific configuration example of the present embodiment, which has the same configuration as that of FIG. 17, but the cache selection control unit 15 in the present embodiment employs a means 25 for holding a constant threshold value c. The address registration means 24 of the cache selection control unit 15 compares the constant value c with the value of the reference counter R, and when the value of the reference counter R is larger than the constant value c, stores the address of the data in the address table. register. Then, the cache selection control unit 15 refers to the address table 23 when a memory request is issued, and if the address is registered in the address table 23, the selector 16 selects the cache memory 22 of the MOESI protocol by the selector 16.

FIGS. 27 and 28 are flow charts showing the operation at the time of memory reading in this embodiment. Also,
FIG. 29 is a flowchart of a process for determining whether to use the MOESI protocol or the MEI protocol. FIG.
7. In FIG. 28, the processes up to steps S1 to S3 are the same as those in FIG. 24. The cache is searched, it is checked whether or not the cache is hit. If the cache is hit, the reference counter is incremented by +1 in step S18. I do. Then, the data read from the cache is returned to the processor. If no hit is found in the cache, it is checked whether the address is registered in the address table (steps S1 to S3).

If the address is registered in the address table, a read request is issued to the shared bus via the MEI cache, and V = 1 (valid) and D = 0 (clea).
The data is stored in the cache memory 21 as n), the reference counter is cleared to 0, and the procedure goes to step S14 (steps S11 to S13). Then, step S1
In step 4, it is checked whether data has been evicted from the cache. If data has not been evicted from the cache, the process proceeds to step S17, and the read data is returned to the processor. If data eviction has occurred, it is checked in step S15 whether the data reference counter is equal to or greater than c.
If the reference counter is equal to or larger than c, the address of the data to be evicted is registered in the address table in step S16, and the process goes to step S17 to return the read data to the processor.

If the address is not registered in the address table, the process goes to step S4, where the MO
A read request is issued to the shared bus via the ESI cache. In step S5, it is checked whether another cache memory has data. If the other cache memory does not have data, V = 1 (valid) and S = 0.
(Non-shared), D = 0 (clean), the data is stored in the cache memory 21, and the procedure goes to step S10.

If the other cache memory has data, it is checked in steps S6 and S7 whether the data is dirty. If the data is dirty,
V = 1 (valid), S = 1 (shared), D = 1 (dirty
), The data is stored, and the procedure goes to step S10.
If the data is not dirty, step S8
V = 1 (valid), S = 1 (shared), D = 0
The data is stored as (clean), and the process goes to step S10. In step S10, the reference counter is cleared to 0, and in step S17, the read data is returned to the processor.

(7) Embodiment 7 This embodiment has a configuration similar to that of the fifth embodiment. FIG. 21 shows the overall configuration, and the contents of the cache memory are composed of the cache lines shown in FIG. In this embodiment, an address table is prepared as in the fifth embodiment.
Although the contents of the entry are the same as those in FIG. 16, in this embodiment, as in the sixth embodiment, when the value of the reference counter is larger than a predetermined constant value c, the address of the data is stored in the address table. register. That is, when data is evicted from the cache memory, the reference counter is referred to, and if the value is equal to or greater than a certain value c, the address of the data is registered in the address table. Later, when a request for the same address occurs, since the address is registered in the address table, it is accessed using the MOESI protocol, and the protocol selection bit of the cache line is set to MO.
Revised to ESI protocol. In this way, by setting frequently referenced data to use the MOESI protocol, the S state can be used appropriately.

FIG. 30 is a diagram showing a specific configuration example of the present embodiment, which has the same configuration as that of FIG. 23, but the protocol selection control unit 17 in the present embodiment employs a means 25 for holding a constant threshold value c. The address registration means 24 of the protocol selection control unit 17 compares the constant value c with the value of the reference counter R, and when the value of the reference counter R is larger than the constant value c, stores the address of the data in the address table 23. Register with. Then, the cache selection control unit 15 refers to the address table 23 when a memory request is issued, and if the address is registered in the address table 23, the selector 16 selects the cache memory 22 of the MOESI protocol by the selector 16.

FIGS. 31 and 32 are flow charts showing the operation at the time of memory reading in this embodiment. Also,
A flowchart for determining whether to use the MOESI protocol or the MEI protocol is as shown in FIG. 29 as in the sixth embodiment. The operation at the time of reading the memory of the present embodiment is the same as that of the sixth embodiment. A read request is issued to the shared bus with the protocol set to MOESI in step S4, and the protocol is set to the shared bus as MEI in step S11. Point that a read request is issued, and steps S12 and S7
In S9 and S12, the only difference is that the value of P is set.
7 and FIG.

(8) Eighth Embodiment This embodiment has a configuration similar to that of the fourth and sixth embodiments, and the overall configuration is as shown in FIG. 13. The contents of each cache memory are as shown in FIG. 14 and FIG. It consists of the indicated cache line. Also in the present embodiment, an address table 23 is prepared as in the fourth and sixth embodiments. Although the contents of the entry are the same as those in FIG. 16, in this embodiment, when the value of the reference counter is larger than a predetermined constant value c, the address of the data is registered in the address table and the value of c is changed. Change dynamically.

That is, when data is evicted from the cache memory, the reference counter is referred to, and when the value is equal to or greater than a certain threshold value c, the address of the data is registered in the address table. Later, when a request for the same address occurs, the address is registered in the address table and is accessed using a cache using the MOESI protocol. In this way, by storing frequently referenced data in a cache using the MOESI protocol, the S state can be used appropriately. Further, in the present embodiment, unlike the sixth embodiment, the threshold value c is dynamically changed as follows.

The value of c is 11 when a collision occurs in the cache memory using the MOESI protocol (when valid data is evicted from the cache memory), and M
It is decremented by 1 when a collision occurs in the cache memory using the EI protocol (when valid data is evicted from the cache memory). By changing the threshold value c in this way, when a cache memory using the MOESI protocol is frequently used, the threshold value is increased and the MOES
If the cache memory using the MEI protocol is not used very much, and if the cache memory using the MEI protocol is used frequently, the threshold is lowered to reduce the MEI.
The cache memory using the protocol can be less used. As a result, both cache memories can be used effectively regardless of the environment such as the amount of cache memory.

FIG. 33 is a diagram showing a specific configuration example of the present embodiment. The configuration is similar to that of FIG. 26, but the cache selection control unit 15 in the present embodiment holds a dynamically changing threshold value c. Means 25 and address registration means 24,
Threshold value increasing / decreasing means 27 for increasing / decreasing the threshold value c when valid data is evicted from the cache memories 21 and 22
It has. Then, the address registration means 24
The threshold value c is compared with the value of the reference counter R, and when the value of the reference counter R is larger than the fixed value c, the address of the data is registered in the address table. Further, the threshold value increasing / decreasing means 27 is, as described above,
When a collision occurs in the cache memory using the protocol, the threshold value c is set to 11, and when a collision occurs in the cache memory using the MEI protocol, the threshold value c is set to −1.

As described above, when a memory request occurs, the cache selection control unit 15
And if the address is registered in the address table 23, the selector 16 selects the cache memory 22 of the MOESI protocol.

FIGS. 34 and 35 are flow charts showing the operation at the time of memory reading in this embodiment. Also,
Cache memory and ME using MOESI protocol
A flowchart for determining which one of the cache memories using the I protocol is used is the same as FIG.
It is. The operation of this embodiment will be described with reference to FIGS. 34 and 35, the processes in steps S1 to S3 are the same as those in FIG. 31 described above. The cache is searched, it is checked whether or not the cache has been hit. If the cache has been hit, the reference counter is reset in step S18. +1. Then, the process goes to step S20 to return the data read from the cache to the processor. If no hit is found in the cache, it is checked whether the address is registered in the address table (steps S1 to S3). If the address is registered in the address table, a read request is issued to the shared bus via the MEI cache, and V = 1 (valid), D = 0
(Clean), the data is stored in the cache memory 21, the reference counter is cleared to 0, and step S1 is executed.
6 (steps S13 to S15).

Then, at step S16, it is checked whether or not data has been evicted from the cache. If no data has been evicted from the cache,
Go to step S20, and return the read data to the processor. Also, if data eviction occurs,
In step S17, the value of the threshold value c is decremented by one, and in step S18, it is checked whether the reference counter of the data to be expelled is equal to or larger than c. If the reference counter is not equal to or greater than c, the process proceeds to step S20. If the reference counter is equal to or greater than c, the address of the data to be evicted is registered in the address table in step S19, and the process proceeds to step S17 to read out to the processor. Returns the data.

If the address is not registered in the address table, the process goes to step S4, where the MO
A read request is issued to the shared bus via the ESI cache. In step S5, it is checked whether another cache memory has data. If the other cache memory does not have data, V = 1 (valid) and S = 0.
(Non-shared), D = 0 (clean), the data is stored in the cache memory 21, and the procedure goes to step S10.
If the other cache memory has data,
In steps S6 and S7, it is checked whether the data is dirty. If the data is dirty, V = 1 (vali
d), S = 1 (shared), D = 1 (dirty), the data is stored, and the process goes to step S10.

If the data is not dirty,
In step S8, V = 1 (valid), S = 1 (shar
ed), the data is stored as D = 0 (clean), and the procedure goes to step S10. In step S10, the reference counter is cleared to 0, and in step 11, it is checked whether data eviction has occurred. If data eviction has not occurred, the process proceeds to step S20. If data eviction has occurred, the process proceeds to step S12.
Is incremented by 1, and the process goes to step S20 to return the data read to the processor.

[0071]

As described above, in the present invention, in the cache on the parallel computer, the method of consistency management is changed according to data, so that memory access caused by extra consistency management processing is performed. Processing overhead can be reduced. Therefore, the performance of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing an overall configuration of a first (third) embodiment in which two cache memories and a cache control device are provided in a cache memory device;

FIG. 3 is a diagram illustrating a cache line of the cache memory according to the first embodiment.

FIG. 4 is a diagram showing a correspondence between a bit indicating a state and each state of a cache;

FIG. 5 is a diagram illustrating a configuration example in which the first embodiment is applied to prefetch control.

FIG. 6 is a flowchart illustrating an operation at the time of memory reading according to the first embodiment;

FIG. 7 is a diagram showing an overall configuration of a second (third) embodiment in which one cache memory and a cache control device are provided in a cache memory device;

FIG. 8 is a diagram illustrating a cache line of a cache memory according to a second embodiment;

FIG. 9 is a specific configuration example in which the second embodiment is applied to prefetch control.

FIG. 10 is a flowchart showing an operation at the time of memory reading according to the second embodiment.

FIG. 11 is a diagram (part 1) illustrating a cache line according to a third embodiment in which a reference counter is provided for each line;

FIG. 12 is a diagram illustrating a cache line according to a third embodiment in which a reference counter is provided for each line (part 2);

FIG. 13 is a diagram showing an overall configuration of a fourth (sixth and eighth) embodiment of the present invention provided with a reference counter and an address table.

FIG. 14 shows a cache memory (MOES) of the fourth embodiment.
It is a figure which shows the cache line of I).

FIG. 15 is a cache memory (MEI) according to a fourth embodiment;
FIG. 3 is a diagram showing a cache line of FIG.

FIG. 16 is a diagram showing a structure of an address table.

FIG. 17 is a diagram showing a specific configuration example of the fourth embodiment.

FIG. 18 is a flowchart (part 1) illustrating an operation at the time of memory reading according to the fourth embodiment;

FIG. 19 is a flowchart (part 2) illustrating an operation at the time of memory reading according to the fourth embodiment;

FIG. 20 is a flowchart for determining whether to use the MOESI protocol or the MEI protocol in the fourth (fifth) embodiment.

FIG. 21 is a diagram showing an overall configuration of a fifth (seventh) embodiment in which one cache memory and a cache control device are provided in a cache memory device.

FIG. 22 is a diagram illustrating cache lines of a cache memory according to a fifth embodiment.

FIG. 23 is a diagram illustrating a specific configuration example of the fifth embodiment.

FIG. 24 is a flowchart (part 1) illustrating an operation at the time of memory reading according to the fifth embodiment;

FIG. 25 is a flowchart (No. 2) illustrating an operation at the time of memory reading according to the fifth embodiment;

FIG. 26 is a diagram showing a specific configuration example of the sixth embodiment.

FIG. 27 is a flowchart (part 1) illustrating an operation at the time of memory reading according to the sixth embodiment;

FIG. 28 is a flowchart (part 2) illustrating an operation at the time of memory reading according to the sixth embodiment;

FIG. 29 is a flowchart of a process of determining whether to use the MOESI protocol or the MEI protocol according to the sixth (seventh and eighth) embodiments.

FIG. 30 is a diagram showing a specific configuration example of the seventh embodiment.

FIG. 31 is a flowchart (part 1) illustrating an operation at the time of memory reading according to the seventh embodiment;

FIG. 32 is a flowchart (part 2) illustrating an operation at the time of memory reading according to the seventh embodiment;

FIG. 33 is a diagram showing a specific configuration example of the eighth embodiment.

FIG. 34 is a flowchart (part 1) illustrating an operation at the time of memory reading according to the eighth embodiment;

FIG. 35 is a flowchart (part 2) illustrating an operation at the time of memory reading according to the eighth embodiment;

FIG. 36 is a diagram illustrating a configuration example of a parallel computer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processor 2 Cache memory device 3, 3-1 to 3-n cache memory 4, 4-1 to 4-n Cache control device 11 Processor 20 Cache memory device 12 Shared bus 13 Memory 21, 22, Cache memory 21a, 22a Cache control Apparatus 14 Prefetch control unit 15 Cache selection control unit 16 Selector 17 Protocol selection control unit 23 Address table 24 Address registration means 25 Means for holding a constant threshold 26 Means for holding a dynamically changing threshold c 27 Threshold increase / decrease means

Claims (6)

[Claims] 1. A cache memory device provided corresponding to each processor of a shared memory type parallel computer, wherein a plurality of cache memories having different cache protocols are provided in the cache memory device. A cache memory device which performs different coherence management. 2. A cache memory device provided corresponding to each processor of a shared memory type parallel computer, wherein a bit for designating which cache protocol is used is added to each cache line of the cache memory. A cache memory device wherein different consistency management is performed for each line. 3. The method according to claim 1, wherein a reference counter is provided for each cache line to indicate how much the cache line has been referenced by the processor, and a cache protocol is selected based on the value of the reference counter. 2 cache memory device. 4. An address table for registering an address is provided, and based on a value of the reference counter,
Find the address of the data that was evicted from the cache memory without being referenced at all, or the address of the data that was evicted from the cache memory after being referenced a predetermined number of times or more and registered in the address table, and registered in the address table Based on the address provided,
4. The cache memory device according to claim 3, wherein a cache protocol to be used is automatically selected. 5. A cache system comprising: a plurality of cache memories using a first protocol that does not allow data sharing with another cache memory and a second protocol that allows data sharing with another cache memory; For each cache line in the memory, a reference counter indicating how much the cache line has been referred to by the processor, an address table for registering an address, and a conflict in the cache memory using the first protocol. A means for holding a threshold value that is incremented by one when a collision occurs in a cache memory using the second protocol, and when data whose reference counter value is equal to or greater than the threshold value is evicted from the cache memory, Find the address of Register Le based on the registered address in the address table,
2. The cache memory device according to claim 1, wherein a cache protocol of which cache protocol is used is automatically selected. 6. A computer comprising the cache memory device according to claim 1, 2, 3, 4, or 5.