JP2000124740A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the output of wide band frequency while reducing the spurious by using the output signal of a reference signal oscillator as a clock to generate a signal of the designated frequency and also a local oscillation wave of the specific frequency, outputting and multiplying the signal of sum or difference frequency between the output signal of a DDS(direct digital synthesizer) and the local oscillation wave, dividing the output signal of a multiplier and varying the number of divided signals. SOLUTION: A reference oscillator 1 generates a cycle signal having the specific frequency and outputs it to a DDS 2. The DDS 2 outputs a signal of output frequency that is designated by the frequency setting data and on the basis of the timing of a reference clock received from the oscillator 1. A local oscillator 7 outputs a local oscillation wave. The output signal of the DDS 2 and the local oscillation wave of the oscillator 7 are inputted to a frequency converter 8 and converted into a signal of sum or difference frequency of two signals. The frequency of output of the converter 8 is set larger than the that of the output signal of the DDS 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer using a direct digital synthesizer as frequency generating means used in a radar transmitting / receiving apparatus.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a circuit showing the configuration of a conventional frequency synthesizer. In FIG.
2 is a direct digital synthesizer (Direct
Digital Synthesizer: DD
3 is a phase accumulator, 4 is a memory, 5
Denotes a digital-analog converter (hereinafter referred to as a DA converter), 6 denotes a filter, and DDS2 comprises a phase accumulator 3, a memory 4, a DA converter 5, and a filter 6. FIG. 7 is a signal waveform diagram in each section, and FIG. 8 is a diagram showing an example of a relationship between phase data and amplitude data.
Here, the phase accumulator 3 in the DDS 2 is shown in FIG.
The frequency setting data is cumulatively added with reference to the timing of the reference clock from the reference signal oscillator 1 shown in the reference signal output diagram of FIG. 7A to output the digital value shown in the phase accumulator output diagram of FIG. I do. When the cumulatively added phase becomes 2π, the phase accumulator 3 resets the phase to 0, and repeatedly outputs a value of 0 to 2π. The reference clock is configured so that one cycle of the output signal includes two or more clocks. Memory 4
Holds digital data output from the phase accumulator 3 as address data and waveform data (amplitude data) corresponding to a phase as a look-up table, as shown in FIG. As shown in FIG. 8, the phase data represents a phase corresponding to the amplitude data stored in the memory 4, but also represents an address of the memory 4, and the amplitude data is read out. The amplitude data is converted into an analog value by the DA converter 5 and passed through a filter 6 for removing unnecessary waves and extracting only necessary frequency components, and is shown in the DDS output signal diagram of FIG. Outputs a sine wave signal.

In such a circuit, the output frequency fDDS of the DDS2 is expressed by the following equation (1), where fr is the reference signal frequency, A is the number of bits for which the frequency of the DDS2 can be set, and B is the decimal value of the actual frequency setting data. Is represented by As a result, the output frequency of the DDS2 can be set within a range of about の of the frequency of the reference signal oscillator by the frequency setting data.

[0004]

(Equation 1)

[0005]

In the above-mentioned conventional frequency synthesizer, the amplitude data of the sine wave is quantized and stored in a memory. Therefore, there is a disadvantage that spurious is generated due to the distortion of the wave accompanying the quantization.

[0006] Further, when a signal accompanied by such spurious signals is frequency-divided, spurious signals are output as the output signal. Here, assuming that the power ratio of the carrier and the spurious at the output of the DDS is Si, the ratio Soi of the power of the carrier and the spurious after the frequency division is represented by Expression 2.

[0007]

(Equation 2)

Here, N is a frequency division number. Equation 2 shows that spurious can be reduced when frequency division is performed. However, the DDS digital IC has a frequency limit, and the output frequency and the frequency band are reduced to 1 / N due to the frequency division, so that the output frequency is lowered and the frequency band cannot be widened.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency synthesizer that outputs a wide band frequency while reducing spurious due to a DDS quantization error. I do.

[0010]

According to a first aspect of the present invention, there is provided a frequency synthesizer for generating a periodic signal having a specific frequency, and receiving and specifying frequency setting data using an output signal of the reference signal oscillator as a clock. DDS for generating a signal having a specified frequency, a local oscillator for generating a local oscillation wave having a specific frequency, and a frequency converter for outputting a signal having a sum or difference frequency between the output signal of the DDS and the local oscillation wave A frequency divider that multiplies the output signal of the frequency converter, and a variable frequency divider that can divide the frequency of the output signal of the frequency multiplier and change the frequency division number according to frequency setting data. It is characterized by having done.

A frequency synthesizer according to a second aspect of the present invention provides a reference signal oscillator for generating a periodic signal having a specific frequency, and a frequency specified by receiving frequency setting data using an output signal of the reference signal oscillator as a clock. A DDS that generates a signal having the same, a frequency converter that outputs a sum or difference frequency between the output signal of the DDS and the local oscillation wave using the output signal of the reference signal oscillator as a local oscillation wave,
A frequency divider configured to multiply an output signal of the frequency converter, and a variable frequency divider capable of dividing an output signal of the frequency multiplier and changing the frequency of division by frequency setting data. Features.

Further, a frequency synthesizer according to a third aspect of the present invention provides a reference signal oscillator for generating a periodic signal having a specific frequency, a frequency divider for dividing an output signal of the reference signal oscillator, and a frequency divider for the frequency divider. A DDS that generates a signal having a designated frequency by receiving frequency setting data using the output signal as a clock, and a sum or difference between the output signal of the DDS and the local oscillation wave using the output signal of the reference signal oscillator as a local oscillation wave A frequency converter that outputs the frequency of the frequency converter, a frequency multiplier that multiplies the output signal of the frequency converter, and a frequency division circuit that divides the output signal of the frequency multiplier and changes the frequency division number according to the frequency setting data. And a variable frequency divider.

According to a fourth aspect of the present invention, there is provided a frequency synthesizer for generating a reference signal oscillator for generating a periodic signal having a specific frequency, and receiving a frequency setting data using an output signal of the reference signal oscillator as a clock to set a designated frequency. A DDS that generates a signal having the signal, a first multiplier that multiplies the output signal of the reference signal oscillator, and a local oscillation wave using the output signal of the first multiplier as a local oscillation wave. A frequency converter that outputs a sum or difference frequency, a second multiplier that multiplies the output signal of the frequency converter, and a frequency divider that divides the output signal of the second multiplier, and calculates the frequency division number And a variable frequency divider that can be changed by setting data.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram of a frequency synthesizer according to a first embodiment of the present invention. In FIG. 1, 7 is a local oscillator, 8 is a frequency converter, 9
Is a multiplier, and 10 is a variable frequency divider, and the same or corresponding parts as those in the conventional example of FIG. DDS2
Is the same as that of the conventional example. FIG. 2 is a diagram showing the relationship between the frequency of the input signal and the frequency of the output signal of the variable frequency divider.

Next, the operation will be described. First, the reference signal oscillator 1 generates a periodic signal having a specific frequency,
Output to DDS2. The DDS 2 outputs a signal having an output frequency specified by the frequency setting data with reference to the timing of the reference clock from the reference signal oscillator 1. In such a circuit, the output frequency f of the DDS2
The DDS is represented by Equation 1, where fr is the reference signal frequency, A is the frequency settable bit number of the DDS2, and B is the decimal value of the actual frequency setting data. On the other hand, the local oscillator 7 outputs a local oscillation wave. The output signal of the DDS2 and the local oscillation wave are input to the frequency converter 8, and are converted into a signal having a sum or difference frequency of the two signals. Here, the frequency of the output of the frequency converter 8 is set to be higher than the frequency of the output signal of the DDS2. The output signal of the frequency converter 8 is multiplied by a multiplier 9. At this time, the frequency of the local oscillation wave is fLO, and the multiplier of the multiplier is M
Then, the frequency fmlt of the output of the multiplier 8 is expressed by Expression 3.

[0016]

(Equation 3)

The output signal of the multiplier 9 is divided and output by the variable frequency divider 10 and becomes the output of the frequency synthesizer. Here, one of the frequency setting data of the variable frequency divider 10 is
Assuming that the value converted into a 0-base number, that is, the frequency division number, is N, the frequency fout of the output signal is expressed by Expression 4.

[0018]

(Equation 4)

Here, assuming that the power ratio of the carrier and the spurious at the output of the DDS2 is Si, the ratio Soi of the power of the carrier and the spurious after the frequency division is represented by Equation 5, and the spurious can be reduced. .

[0020]

(Equation 5)

Next, the relationship between the frequency of the input signal and the frequency of the output signal of the variable frequency divider 10 will be described. From FIG. 2, the minimum value of the frequency of the input signal of the variable frequency divider 10 is fmltmi.
n, when the maximum value of the frequency division number N of the variable frequency divider 10 is Nmax, the minimum value foutmin of the output signal is expressed by Expression 6.

[0022]

(Equation 6)

If a value larger than Nmax is selected from Equation 6, the lower limit of the output frequency can be reduced. Further, the maximum value of the frequency of the input signal of the variable frequency divider 10 is fmltma.
x, when the minimum value of the frequency division number N of the variable frequency divider 10 is Nmin, the minimum value foutmax of the output signal is expressed by Expression 7.

[0024]

(Equation 7)

If a value smaller than Nmin is selected from Equation 7, the upper limit of the output frequency can be increased. Therefore,
By setting the band of the output signal to a large range of the frequency division number N, a wideband frequency synthesizer can be obtained.
The condition for the output signal to be continuous is expressed by Expression 8.

[0026]

(Equation 8)

In equation 8, fmltmax-fmlt
min is the band of the output signal of the multiplier 9. The band ΔfDDS of the output signal of the DDS 2 is 1 / M of the band of the output signal of the multiplier 9. Therefore, if the minimum value of the output frequency of the frequency converter 8 is fmixmin, ΔfDD
S is represented by Expression 9.

[0028]

(Equation 9)

From equation (9), regardless of the bandwidth of the output signal,
If M is increased, ΔfDDS can be made sufficiently small.

Embodiment 2 FIG. FIG. 3 is a configuration diagram of a frequency synthesizer according to a second embodiment of the present invention. In the figure, reference numerals 1, 2, 8 to 10 are the same as those in the first embodiment of FIG.

Next, the operation will be described. Reference signal oscillator 1, DDS2, frequency converter 8, and multiplier 9
The operation of the variable frequency divider 10 is the same as that of the first embodiment, and the same operation of reducing spurious and the operation of widening the band by the variable frequency divider 10 can be expected. Here, the frequency converter 8 uses the output signal of the reference signal oscillator 1 as a local oscillation wave. Since only one oscillator is used, the cost can be reduced and the coherence of the frequency synthesizer can be realized.

Embodiment 3 FIG. FIG. 4 is a block diagram of a frequency synthesizer according to a third embodiment of the present invention. In the figure, reference numerals 1, 2, 8 to 10 are the same as those of the first embodiment of FIG. 1, and reference numeral 11 denotes a frequency divider.

Next, the operation will be described. Frequency divider 11
Divides the output signal of the reference signal oscillator 1 to generate a reference clock of the DDS2. Reference signal oscillator 1 and DDS2
The operations of the frequency converter 8, the frequency multiplier 9, and the variable frequency divider 10 are the same as those in the first embodiment, and the same spurious reduction operation and the operation of widening the bandwidth by the variable frequency divider 10 can be expected. . Further, since only one oscillator is used, the cost can be reduced, and the coherence of the frequency synthesizer can be realized. Further, since the output signal of the reference signal oscillator 1 is frequency-divided and used as a reference signal, a low spurious component that operates at a low frequency can be used for the DDS 2.

Embodiment 4 FIG. 5 is a configuration diagram of a frequency synthesizer according to a fourth embodiment of the present invention. In the figure, 1, 2, 8, and 10 are the same as those in the first embodiment of FIG. 1, 9a is a first multiplier, 9b is a second multiplier.

Next, the operation will be described. The first multiplier 9a multiplies the output signal of the reference signal oscillator 1 to generate a local oscillation wave of the frequency converter 8. Reference signal oscillator 1
The operation of DDS2, frequency converter 8, and variable frequency divider 10 is the same as that of the first embodiment. The operation of the second multiplier 9b is the same as the operation of the multiplier 9 of the first embodiment, and the same operation of reducing spurious and the operation of widening the band by the variable frequency divider 10 can be expected. Further, since only one oscillator is used, the cost can be reduced, and the coherence of the frequency synthesizer can be realized. In addition, since the output signal of the reference signal oscillator 1 is multiplied and used as a local signal wave, the DDS 2 can use a component having a low spurious performance that operates at a low frequency.
The frequency of the reference signal oscillator 1 can be reduced.

[0036]

According to the first aspect of the invention, it is possible to obtain a frequency synthesizer that outputs a wide band frequency while reducing spurious due to a DDS quantization error.

According to the second aspect of the present invention, it is possible to obtain a frequency synthesizer that outputs a wide band frequency while reducing spurious due to a DDS quantization error. In addition, since only one oscillator is used, the cost can be reduced, and a coherent frequency synthesizer can be realized.

Further, according to the third aspect, it is possible to obtain a frequency synthesizer that outputs a wide band frequency while reducing spurious due to a DDS quantization error. In addition, since only one oscillator is used, the cost can be reduced, and a coherent frequency synthesizer can be realized. In addition, a low spurious component that operates at a low frequency can be used for the DDS.

Further, according to the fourth aspect, it is possible to obtain a frequency synthesizer that outputs a wide band frequency while reducing spurious due to a DDS quantization error. In addition, since only one oscillator is used, the cost can be reduced, and a coherent frequency synthesizer can be realized. In addition, it is possible to use low spurious components operating at a low frequency for the DDS,
The frequency of the reference signal oscillator can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing Embodiment 1 of a frequency synthesizer according to the present invention.

FIG. 2 is a diagram illustrating a relationship between frequencies of an input signal and an output signal of a variable frequency divider.

FIG. 3 is a diagram showing a second embodiment of the frequency synthesizer according to the present invention;

FIG. 4 is a diagram showing a third embodiment of the frequency synthesizer according to the present invention;

FIG. 5 is a diagram showing a fourth embodiment of the frequency synthesizer according to the present invention;

FIG. 6 is a diagram illustrating a conventional frequency synthesizer.

FIG. 7 is a diagram for explaining signal waveforms at various parts of the DDS.

FIG. 8 is a diagram illustrating an example of a relationship between DDS phase data and amplitude data.

[Explanation of symbols]

1 reference signal oscillator, 2 DDS (direct digital synthesizer), 3 phase accumulator, 4 memory, 5 DA converter (digital-analog converter), 6 filter, 7 local oscillator, 8 frequency converter, 9 multiplier, 9a 1st multiplier, 9b 2nd multiplier, 10 variable frequency divider, 11 frequency divider.

Claims (4)

[Claims] A reference signal oscillator for generating a periodic signal having a specific frequency; a direct digital synthesizer for generating a signal having a designated frequency by receiving frequency setting data using an output signal of the reference signal oscillator as a clock; A local oscillator that generates a local oscillation wave having a specific frequency, a frequency converter that outputs a signal having a sum or difference frequency between the output signal of the direct digital synthesizer and the local oscillation wave, and an output of the frequency converter. A frequency synthesizer comprising: a frequency multiplier for multiplying a signal; and a variable frequency divider which divides an output signal of the frequency multiplier and can change the frequency of division by frequency setting data. 2. A reference signal oscillator for generating a periodic signal having a specific frequency, a direct digital synthesizer for generating a signal having a specified frequency in response to frequency setting data using an output signal of the reference signal oscillator as a clock. A frequency converter that outputs the sum or difference frequency between the output signal of the direct digital synthesizer and the local oscillation wave using the output signal of the reference signal oscillator as a local oscillation wave, and a multiplier that multiplies the output signal of the frequency converter. A frequency synthesizer comprising: a frequency divider; and a variable frequency divider that can divide the output signal of the multiplier and change the frequency of division by frequency setting data. 3. A reference signal oscillator for generating a periodic signal having a specific frequency, a frequency divider for dividing an output signal of the reference signal oscillator, and frequency setting data using the output signal of the frequency divider as a clock. A direct digital synthesizer that receives and generates a signal having a designated frequency; and outputs a sum or difference frequency between the output signal of the direct digital synthesizer and the local oscillation wave using the output signal of the reference signal oscillator as a local oscillation wave. A frequency converter;
A frequency divider configured to multiply an output signal of the frequency converter, and a variable frequency divider capable of dividing an output signal of the frequency multiplier and changing the frequency of division by frequency setting data. A featured frequency synthesizer. 4. A reference signal oscillator for generating a periodic signal having a specific frequency, and a direct digital synthesizer for generating a signal having a specified frequency by receiving frequency setting data using an output signal of the reference signal oscillator as a clock. First multiplying the output signal of the reference signal oscillator
A frequency converter that outputs the sum or difference frequency between the output signal of the direct digital synthesizer and the local oscillation wave using the output signal of the first multiplier as a local oscillation wave; A second multiplier for multiplying the output signal, and dividing the output signal of the second multiplier,
A frequency synthesizer comprising a variable frequency divider whose frequency can be changed by frequency setting data.