JP2000124317A - Information-processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time for reconfiguring a circuit into a programmable logic circuit, and at the same time to efficiently utilize the circuit existing on the programmable logic circuit. SOLUTION: An information-processing system stores a plurality of circuit information for configuring a programmable logic circuit 104 into a storage means 200. An acquisition means 105 stores the information of a circuit being configured on the programmable logic circuit 104, and at the same time passes specified circuit information from an application program and the information of the circuit being configured in the programmable logic circuit to an editing means 300, acquires the circuit information of a specified circuit which arrives from the editing means 300, and configures a specified circuit in the programmable logic circuit according to the circuit information. The editing means 300 generates circuit information of a circuit being specified by specified information from the acquisition means 105 in a state which can be utilized without reconfiguring a circuit which is configured in the programmable logic circuit 104 through the use of the circuit information acquired from the storage means 200.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system capable of processing at least a part of processing by an application program by a programmable logic circuit whose circuit configuration can be reconfigured.

[0002]

2. Description of the Related Art In the field of digital circuit devices, in particular, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PGAs) have been developed in order to shorten the development period of products.
2. Description of the Related Art Programmable logic circuits including LDs) are widely used.

[0003] These programmable logic circuits can freely configure internal logic circuits and connections between the logic circuits by reading circuit information describing the logic circuits. For this reason, the use of the programmable logic circuit has an advantage that the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design, is not required. In particular, US Pat. No. 4,700,18
An electrically reconfigurable programmable logic circuit such as the invention of No. 7 has an advantage that a circuit once manufactured can be freely changed as many times as necessary, and the programmable logic circuit is increasingly used. It is becoming.

Japanese Patent Application Laid-Open No. 6-232259 discloses an apparatus for designing such a programmable logic circuit.
Patent Document "FPGA circuit design apparatus and method"
There is an example. This will be described as Conventional Example 1 with reference to FIGS.

FIG. 18 shows a configuration diagram of a CAD system for designing a large-scale FPGA circuit. This device has an F that has placement and wiring information and logic function information in advance.
It has a database 12 in which a plurality of hard macrocells composed of PGA function modules are registered, and a larger-scale FPGA integrated circuit is designed by arranging and wiring using a plurality of hard macrocells registered in the database. Things.

In this device, a designer operates a data input / output device 10 as a man-machine interface to operate a file management program group 11. The file management program group 11 has a logical file management program, a library management program, a placement and routing management program, and the like, and manages the database 12 to be managed by these.

The database 12 includes a logic file in which a large number of logic function information of the FPGA is registered, a cell library in which FPGA cells as function modules are registered,
It consists of a placement and routing file in which placement and routing information inside and outside the GA is registered. In the cell library, a large number of hard macro cells which have arrangement / wiring information and logic function information in advance and execute a specific function as a peripheral circuit or the like are registered in advance. The contents of each file in the database 12 are read and diagnosed by the diagnostic system 13 as appropriate, and the diagnostic data 14 is output.

A large-scale FPGA circuit is realized by sequentially using a drawing input system, a netlist generation system, a layout system, an in-cell arrangement and wiring system, and an output program in accordance with the contents of each file registered in the database. And output a design drawing and a program therefor.

[0009] The 1 designed by this CAD system
FIG. 19 shows a configuration example of a microcomputer system using a chip FPGA. This FPGA chip 20
CPU21, ROM22, RAM23, I / O port 2
4. PIT (P
programmable Interval Time
r) 25, a PIC (Programmable In) that controls interrupt signals from a plurality of devices that occurred simultaneously.
terruptController) 26, CPU
21 and a DMAC (D
directMemory Access Contro
each of the address / data bus 2
8 and the control signal line 29.

The I / O port 24, PIT2
5, hard macro cells corresponding to the PIC 26 and the DMAC 27 are registered in advance in the cell library of the database 12, and these are simply read out as they are and mapped onto the FPGA chip 20. The placement and routing process can be completed.

As described above, according to the conventional example 1, there is provided a library in which a plurality of hard macro cells each including an FPGA function module having arrangement and wiring information and logic function information are registered in advance, and registered in this library. By arranging and wiring using multiple hard macro cells, the existing FPGA circuit can be utilized as a design property,
A design with a reduced development period by reducing the burden of system design can be achieved.

The prior art 1 described above relates to the invention when one FPGA chip is designed. However, the complexity of recent logic circuits increases, and the scale cannot be realized by one programmable logic circuit device. The circuit scale has increased up to.

One way to solve this problem is to implement different logic circuits at different times,
It has been proposed to reconfigure a programmable logic circuit during processing. By using this method, there is an advantage that various processes can be performed at a relatively high speed even when the size of a circuit that can be built in is limited because the device is small like a portable information terminal.

However, when reconfiguring a programmable logic circuit, the circuit information of the entire circuit is read again, so that there is a disadvantage that the reconfiguration takes time. Further, reconfiguring in the middle of the process means that the process is temporarily suspended, the data at that time is saved in a storage device outside the programmable logic circuit, new circuit information is read and reconfigured, and the data before reconfiguration is reconstructed. And extra processing of inputting new data accompanying the reconstruction is necessary, and the processing of taking data in and out becomes redundant.

In order to solve this problem, a programmable logic circuit described in a data book named "CONFIGURABLE LOGIC" by Atmel Corporation of the United States and "THE PROGR by Xilinx Corporation of the United States" have been proposed.
A programmable logic circuit described in a data book named "AMMABLE LOGIC" has a data storage device for storing data, and reads part of circuit information from an external storage device during operation of the circuit to partially store the circuit information. By performing the reconfiguration, the time required for the reconfiguration is minimized.

A problem when such a programmable logic circuit is used in an information processing system is that circuit information for forming a desired logic circuit is extracted from a storage destination, and a plurality of pieces of circuit information are synthesized as necessary. And to reconfigure the desired logic circuit at high speed and efficiently.

The above-described information system for reconfiguring a plurality of pieces of circuit information into programmable logic circuits at different times and performing predetermined processing can be used by connecting to a network. As an example, there is a "reconfigurable network computer" described in Japanese Patent Application Laid-Open No. 10-78932, which will be described as Conventional Example 2 with reference to FIG.

The information processing system according to the second conventional example is composed of a plurality of computers connected to a communication network NET, at least one of which is a computer (application server) SB for distributing an application program, and the remaining ones. The computer is a system configured by a computer (client computer) CL which is a client that downloads and executes the application program. An extended hardware (extended HW) 31 capable of changing and reconfiguring functions at any time by a program is mounted on a part of the plurality of client computers CL.

In the application program AP stored in the server SB, some of its functions are
Extended hardware program code (extended code)
And the code of the main processor (main P) 32 of the client computer CL.

OS of the client computer CL
Has a function of determining whether or not the extension hardware 31 is installed. When the extension hardware 31 is installed, the application program AP has the function as shown in the upper client computer CL in FIG. It has a code selection function 33 for extracting only codes suitable for the hardware configuration from the inside. When the client does not have the extended hardware 31 like the client computer CL on the lower side of FIG. 20, the code of the main processor 32 is selected by the code selection function 33 and the application can be used.

In another configuration, the function realized by the extended hardware 31 is realized as an OS extended function or a dynamic library that can be dynamically added / deleted later on the client computer CL, and the application program AP Registers the type of an extended function or a dynamic library used during processing with the OS. The OS uses the extended function or the dynamic library if it exists on the client, and uses the network N if it does not exist.
The required extended function or dynamic library is transferred from the server SB on the ET and used.

Further, a code for the main processor 32,
The code for the extension hardware 31 is not integrated, but is
Individual code can also be provided on the host computer for each S extension or dynamic library.

Further, in the case of the conventional example 2, if the configuration of the programmable logic circuit constituting the extension hardware differs between the clients, the extension code is replaced by a logic circuit having an appropriate number of gates and input / output terminals. Basic modules in which functions are described by Boolean expressions or the like, and codes expressing their connection relations can also be used. The basic module can be reused as a design property by referring to another circuit.

Furthermore, the function of allocating the basic module to the basic program of the programmable logic circuit, and in the case of a large extension code extending over a plurality of programmable logic circuit chips, the basic module is divided according to the degree of connection. The function of arranging and wiring each programmable logic circuit chip is provided on the server or the client.

Also, a hardware resource management function for reusing the unnecessary hardware resources for another application program so that a plurality of applications using the extended hardware can be executed at the same time; It has a code replacement function that replaces extended codes that cannot fit in by time sharing.

Also, a priority value appropriately set for each application program executed on the client, a processing capacity value of the main processor, a processing capacity value of the extended hardware, a hardware resource amount, and processing required for code replacement. It has an extended hardware management function for selecting a plurality of application programs that cannot fit in the hardware resources based on the capability value.

When a plurality of applications use the same extension code at the same time with the extension hardware, the function is shared by switching only the internal state by time division.

As described above, in the case of the conventional example 2, when the application program distributed from the server is executed on the client side on the computer connected via the network, the function is changed by the program on the client side as needed. Then, with reconfigurable expansion hardware, the application program stored in the server contains the main processor code and expansion code of the client, and the code selection function that determines the presence or absence of the expansion hardware and the type, The application program can be processed at high speed by changing the configuration of the computer on the client side and making the configuration suitable for processing.

Further, when a new service requiring special hardware on the client side is to be started on the network, conventionally, the user on the client side has to introduce new hardware for that purpose. In addition, the service provider will provide the new service only to some users who have the new hardware, but by implementing the above-mentioned conventional example 2, the new hardware is introduced. Without having to start a new service.

[0030]

However, in the second conventional example, even if the extension code required for a new application is common to a part of the extension code already configured in the extension hardware, the entire extension is required. The code has to be transferred from the server and reconstructed, and the processing time is increased by the time it takes to transfer and reconstruct,
There is a problem that the processing speed is reduced. Further, since the same circuit is redundantly reconfigured on the extension hardware, there is a problem that the utilization efficiency of the extension hardware is low.

In view of the above, the present invention reduces the processing speed by generating circuit information of a programmable logic circuit so that a circuit configured on the programmable logic circuit can be used as much as possible. It is an object of the present invention to solve the problem and to improve the use efficiency of a circuit configured on a programmable logic circuit.

[0032]

According to a first aspect of the present invention, there is provided an information processing system for processing at least a part of an application program by a programmable logic circuit. Processing means for executing a process using a circuit configured in the programmable logic circuit in accordance with an instruction from the application program, and storing a plurality of circuit information for configuring the circuit in the programmable logic circuit Storage means for performing the operation, editing means having a function of generating circuit information of one circuit specified by the specification information using a plurality of circuit information stored in the storage means, and a circuit configured in the programmable logic circuit To identify the application program The specified information is passed to the editing means as the specified information, and the circuit information of the circuit specified by the specified information arriving from the editing means is obtained. Configure the circuit specified above,
Obtaining means for storing information of a circuit configured in the programmable logic circuit, wherein the editing means obtains the circuit information of the circuit specified by the specification information from the obtaining means. The circuit information is generated in a state in which a circuit portion configured in the programmable logic circuit is used without being reconfigured with reference to information of a circuit configured in the programmable logic circuit. .

The information processing system according to a second aspect of the present invention is the information processing system according to the first aspect, wherein the circuit information stored in the acquisition means included in the programmable logic circuit includes a circuit identifier and a circuit identifier of the circuit. And the layout information on the programmable logic circuit, the editing means refers to the identifier of the circuit and the layout information, whereby the circuit information of the circuit specified by the specification information,
In a case where a circuit configured in the programmable logic circuit can be generated in a usable state, the circuit information is generated in a state where the circuit part configured in the programmable logic circuit is used without being reconfigured. It is characterized by.

In the information processing system according to a third aspect of the present invention, in the first aspect, each of the plurality of circuit information stored in the storage means has an identifier of its own circuit information, and When a part or the whole is configured by other circuit information, an identifier of the other circuit information is provided as a reference identifier as circuit data for configuring a circuit in the programmable logic circuit. Generating the circuit information of the circuit specified by the specification information from the acquisition unit by obtaining the circuit information of the specified circuit and other circuit information indicated by the reference identifier from the storage unit Thing,
The editing unit refers to the obtaining unit by using the reference identifier for the existence of the circuit specified by the reference identifier obtained from the storage unit, thereby configuring the circuit indicated by the reference identifier in the programmable logic circuit. And from the acquisition means, obtains the layout information of the circuit configured in the programmable logic circuit, and configures the programmable logic circuit using the circuit information obtained from the storage means. The circuit information is generated in a state where the circuit portion used is used without being reconfigured.

According to a fourth aspect of the present invention, in the information processing apparatus according to the third aspect, the editing means corresponds to the designation information from the acquisition means, and stores the circuit information of a circuit designated by the designation information. Is referred to the storage means by the identifier, and the storage means, in response to the inquiry from the editing means, if the circuit information indicated by the identifier at the time of the inquiry includes a reference identifier, the storage means Returning to the editing means, the editing means inquires of the obtaining means by using the reference identifier for the existence of the circuit specified by the reference identifier obtained from the storage means, wherein the obtaining means In the case where the circuit indicated by the reference identifier at the time of the inquiry exists in the programmable logic circuit, the layout information of the circuit on the programmable logic circuit is edited by the editor. And the editing means having received the arrangement information uses the reference identifier of the circuit which does not exist in the programmable logic circuit obtained from the storage means, and the other circuit information indicated by the reference identifier from the storage means. And the circuit information is generated in a state where the circuit portion configured in the programmable logic circuit is used without being reconfigured.

According to a fifth aspect of the present invention, in the information processing system according to the first aspect, each of the plurality of circuit information stored in the storage means includes an identifier of its own circuit information, and When a part or the whole is configured by other circuit information, an identifier of the other circuit information is provided as a reference identifier as circuit data for configuring a circuit in the programmable logic circuit. Generating the circuit information of the circuit specified by the specification information from the acquisition unit by obtaining the circuit information of the specified circuit and other circuit information indicated by the reference identifier from the storage unit Thing,
The acquisition unit sends information of a circuit configured in the programmable logic circuit to the editing unit together with the designation information, and the editing unit responds to the designation information from the acquisition unit, and When the circuit information of the designated circuit is referred to the storage unit by the identifier, the storage unit responds to the inquiry from the editing unit, and the circuit information indicated by the identifier at the time of the inquiry includes the reference identifier. Returns the reference identifier to the editing means, and the editing means determines the presence of the circuit specified by the reference identifier obtained from the storage means in the programmable logic circuit obtained from the acquisition means by the reference identifier. By referring to the information of the configured circuit, the circuit indicated by the reference identifier of the circuit information of the circuit specified by the specification information is referred to as the program. Identifying whether or not the circuit exists in the mable logic circuit, and using the reference identifier of the circuit not existing in the programmable logic circuit obtained from the storage means, obtaining the other circuit information indicated by the reference identifier from the storage means However, the circuit portion configured in the programmable logic circuit is used without being reconfigured,
The circuit information is generated.

According to a sixth aspect of the present invention, in the information processing system according to the first aspect, each of the plurality of circuit information stored in the storage means includes a circuit data portion and an additional information portion thereof. The additional information section includes an identifier of its own circuit information and, when a part or all of the circuit information is configured by other circuit information, includes the identifier of the other circuit information as a reference identifier. The circuit data portion is described by a pair of an address of a configuration memory of the programmable logic circuit and circuit data stored at the address,
When part or all of the circuit information is constituted by other circuit information, part or all of the circuit information of the circuit information is described using the reference identifier and the reference identifier is used. Is described in the circuit information as circuit data of an address corresponding to a position to refer to the other circuit information, and the editing unit responds to the designation information from the acquisition unit, and according to the designation information, The storage unit is queried for the circuit information of the designated circuit by the identifier, and the storage unit responds to the inquiry from the editing unit, and the additional information section of the circuit information indicated by the identifier at the time of the inquiry Contains a reference identifier, the reference identifier is returned to the editing unit, and the editing unit uses the reference identifier obtained from the storage unit to store the reference identifier. The other circuit information is obtained, and the obtained other circuit information is indicated by an address in which a reference identifier is described as circuit data of circuit information of the circuit specified by the specification information, and a reference identifier existing in the processing unit. A difference address from the address of the circuit to be connected to all the addresses of the circuit data portion of the other circuit information corresponding to the reference identifier, and combining the address with the circuit information in which the reference identifier is described. .

According to a seventh aspect of the present invention, in the information processing system according to any one of the first to sixth aspects, a part constituting the storage means, a part constituting the editing means, the acquisition means and the processing means Are connected via a network.

[0039]

In the information processing system according to the first aspect of the present invention, when the application program is executed, the circuit constituting the programmable logic circuit is specified by the application program so that the program is executed by the programmable logic circuit of the processing means. Is sent to the acquisition means. The acquisition means passes this information to the editing means as circuit information designation information. The editing means sends the specified information to the storage means.

Then, the storage returns the circuit information specified by the specified information to the editing means. When the editing unit receives this and determines that other circuit information of the storage unit is necessary to generate the specified circuit information, the editing unit acquires the other circuit information from the storage unit. At this time, the editing unit refers to the information of the circuit configured in the programmable logic circuit obtained from the acquisition unit, and determines whether the specified circuit information includes the circuit configured in the programmable logic circuit. Determine.

The editing means converts the designated circuit information from the plurality of pieces of circuit information obtained from the storage means into a state in which the circuit part configured in the programmable logic circuit is used, that is, to the programmable logic circuit. Except for the configured circuit part, it is generated and returned to the acquisition means as information requested by the designated information. The acquisition unit reconfigures the circuit information acquired from the editing unit into a programmable logic circuit of the processing unit.

The processing means can execute the processing specified by the application program using the circuit reconfigured into the programmable logic circuit.

As described above, in the information processing system according to the first aspect of the present invention, when the designation information is passed to the acquisition unit when the application program is executed, the editing unit responds to the request from the acquisition unit. In a state in which the circuit already configured in the programmable logic circuit of the processing means is used as it is, circuit information to be configured in the programmable logic circuit of the processing means is automatically generated and returned to the obtaining means, and the obtaining means is configured by the programmable logic circuit. To reconfigure the circuit information.

Therefore, it is not necessary to reconfigure a circuit already configured on the programmable logic circuit.
The reconfiguration time is shortened by that amount, and the processing time can be reduced, and the circuit configured on the programmable logic circuit can be efficiently used.

Further, according to the present invention, the acquisition means and the editing means generate necessary circuit information using the information of the storage means in accordance with the instruction of the application program. It is not necessary to store it in the program.

Further, in the information processing system according to the second aspect of the present invention, the acquisition means stores circuit arrangement information of a circuit formed in the programmable logic circuit, and the editing means uses the circuit arrangement information based on the circuit arrangement information. Necessary circuit information can be generated by determining whether the circuit specified by the specified information can be configured using a circuit already on the programmable logic circuit.

Therefore, efficient use of the circuit formed on the programmable logic circuit can be ensured.

In the information processing system according to the third aspect of the present invention, the structure of the circuit information stored in the storage means is a so-called circuit information having a configuration of circuit data which does not refer to other circuits, which is a so-called lowermost circuit information. It has a tree structure.

That is, each circuit information has, for example, a circuit name as its own identifier. Then, when each circuit information is configured partially or entirely with other circuit information,
As circuit data, an identifier of the other circuit information is provided as a reference identifier. As the reference identifier, the circuit name of other circuit information can be used. Other circuit information indicated by the reference identifier can also be partially or entirely composed of other circuit information. Then, the circuit information of the lowest layer has a structure in which the circuit data does not have the reference identifier. The information of the circuit configured in the programmable logic circuit stored in the acquisition unit has this reference identifier, for example, as a circuit name.

Then, the editing unit inquires the storage unit of the circuit information based on the identifier of the circuit information indicated by the designation information passed from the obtaining unit. When receiving the identifier of the circuit information from the editing means, the storage means returns the circuit information to the editing means, and when the circuit information indicated by the identifier includes a reference identifier, returns the reference identifier to the editing means.

The editing means inquires of the obtaining means by using the reference identifier whether the circuit specified by the received reference identifier exists in the programmable logic circuit. In response to the inquiry from the editing means, if the circuit indicated by the reference identifier at the time of the inquiry exists in the programmable logic circuit, the obtaining means returns the arrangement information on the programmable logic circuit to the editing means.

When the editing means receives the arrangement information,
Using the circuit information obtained from the storage unit, the circuit information is generated in a state where the circuit part configured in the programmable logic circuit is used without being reconfigured.

According to the third aspect, a part of the plurality of circuits constituting the designated circuit information can be made to use a circuit existing in the programmable logic circuit. Reconfiguration of an existing circuit becomes unnecessary, and efficient use of the circuit can be achieved.

In the fourth invention, the editing means determines whether or not the circuit designated by the reference identifier received from the storage means exists in the programmable logic circuit.
The acquisition means is inquired by the reference identifier, and the circuit constituted by the programmable logic circuit among the circuit information designated by the designation information is recognized by the response from the acquisition means. Then, of the circuit information specified by the specification information,
Other circuit information not configured on the programmable logic circuit is obtained from the storage unit using the reference identifier obtained from the storage unit. Then, circuit information of a circuit portion other than the circuit portion configured in the programmable logic circuit is generated as designated circuit information.

According to the fourth aspect, only the circuit information that does not exist on the programmable logic circuit needs to be obtained from the storage means, and only the circuit information existing on the programmable logic circuit is obtained from the storage means. Processing can be accelerated by the acquisition time.

Further, in the fifth invention, the information of the circuit formed in the programmable logic circuit from the acquiring means is sent to the editing means together with the designation information of the circuit information. Therefore, as in the third invention, the editing means does not refer to the acquisition means for the reference identifier acquired from the storage means, but checks the circuit constituted by the programmable logic circuit in the editing means. Thus, in the same manner as in the above-described third aspect, it is possible to generate necessary circuit information while using a circuit configured as a programmable logic circuit as much as possible.

In the sixth invention, the circuit data portion of the circuit information is described by a pair of an address of a configuration memory of the programmable logic circuit and circuit data stored at the address, and When a part or all of the information is constituted by other circuit information, the reference identifier is described as circuit data of an address corresponding to a position where the other circuit information is referred to in the circuit information.

Therefore, the editing means can quickly assemble the circuit information of the circuit specified by the specified information by allocating the circuit information indicated by the reference identifier according to the data content of the circuit data portion.

In particular, when the circuit information of the circuit specified by the specification information includes a circuit already configured in the programmable logic circuit, when generating the circuit information so as to use the circuit portion as it is, The difference address between the address of the circuit indicated by one reference identifier existing in the programmable logic circuit and the address of the circuit indicated by the other reference identifier acquired from the storage means is stored in the circuit data portion of the other circuit information. In addition to the address of
The required circuit information is generated by combining the reference identifier with the described circuit information.

As described above, according to the sixth aspect, simply:
By simply adding an offset to the address, the circuit information indicated by the reference identifier can be combined with the circuit information in which the reference identifier is described, and almost no calculation time for arrangement and wiring is required. Therefore, the editing unit can generate the circuit information in a short time.

Further, by adding the above-described offset to the address to the other circuit information, the circuit information part of the circuit part configured in the programmable logic circuit is not included in the generated circuit information. Can be Therefore, it is easy to generate circuit information in a state where a circuit existing in the programmable logic circuit is used.

In the information processing system according to the seventh aspect of the present invention, a part constituting storage means, a part constituting editing means, and a part constituting acquisition means and processing means are connected via a network. Therefore, there is no need to have an editing unit and a storage unit in one information processing apparatus. For this reason, from the viewpoint of the information processing device operating with the acquisition unit and the processing unit and the application program, when the designated information is transmitted through the network, the circuit structure corresponding to the designated information is automatically transmitted, and the system has a structure. The configurations of the storage unit, the editing unit, the acquisition unit, and the processing unit can be arbitrarily set.

[0063]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an information processing system according to the present invention will be described below with reference to the drawings.

[Outline of Configuration of Entire Information Processing System] A first embodiment of an information processing system according to the present invention in which at least a part of the processing is processed by processing means having a programmable logic circuit capable of reconfiguring a circuit configuration. FIG. 1 shows the main conceptual configuration of the embodiment.

The information processing system in this case includes an information processing unit 100, a storage unit 200, and an editing unit 300. The information processing unit 100, the storage unit 200, and the editing unit 300 may be configured in one information processing device, or may be configured as separate devices and connected to each other via a network. You can also.

Further, the storage section 200 and the editing section 300 are constituted by one computer system, and the information processing section 100 constituted by the computer system is connected through a network to constitute the information processing system. You can also.

In the example described below, the information processing unit 100, the storage unit 200, and the editing unit 300 will be described as being separate devices and connected to each other via a network.

In the information processing section 100, the application program 101 divides a series of processes to be executed into a plurality of processes, and
2 or a hardware processing unit 103 having a programmable logic circuit. In the application program 101, processing performed by the CPU 102 includes the CPU 10
The processing described in the instruction code 2 is performed by the hardware processing unit 103. The processing name included in the programmable logic circuit 104 owned by the hardware processing unit 103 and the hardware processing unit configured as a part of the circuit. This is described by the control code 103.

The hardware processing section 103 constitutes processing means, and has a programmable logic circuit of an FPGA type in this example as the programmable logic circuit 104, and utilizes the circuit configured in the programmable logic circuit 104. Process.

Circuit information acquisition section 105 constituting acquisition means
Receives a request for a circuit included in the programmable logic circuit 104 of the hardware processing unit 103 (designation information of the circuit) from the application program 101, and requests the editing unit 300 for circuit information for configuring the circuit. The requested circuit information is acquired from the editing unit 300. As described later, the circuit information includes a header section and a code section (circuit data section).

Then, the circuit information obtaining unit 105 converts the circuit data described in the code part of the obtained circuit information into
The program is loaded into the hardware processing unit 103 and a circuit is configured in the programmable logic circuit 104. Further, the circuit information obtaining unit 105 converts the input / output port information described in the header of the circuit information into the application program 1.
01.

The application program 101 inputs / outputs data to / from a circuit configured in the programmable logic circuit 104 of the hardware processing unit 103 based on the input / output port information from the circuit information acquisition unit 105.

The circuit information acquiring unit 105 stores information on what kind of circuit is arranged in the programmable logic circuit 104 of the hardware processing unit 103 at that time in the constituent circuit memory 106. And saved. The storage information includes a circuit name existing in the programmable logic circuit 104 and arrangement address information of an area where the circuit is configured on the programmable logic circuit.

Further, in this embodiment, the circuit information acquiring unit 105 determines what kind of circuit is arranged in the programmable logic circuit 104 at that time in response to an inquiry from the editing unit 300 described later. Is returned to the editing unit 300.

The storage section 200 stores a plurality of pieces of circuit information constituting the circuit of the programmable logic circuit 104. As will be described later, in this case, the circuit information can be described by referring to other circuit information, and can be stored in the storage unit 200 by a so-called tree data structure. In addition, the circuit information resources generated in the past can be effectively used, and the storage capacity of the storage element of the storage unit 200 is reduced.

In this case, the storage unit 200 stores
As described later, the information processing unit 100 is provided in a computer system on a network connected to the information processing unit 100, but may be provided in a computer system integrated with the information processing unit 100.

The editing section 300 acquires from the storage section 200 the circuit information necessary for generating the circuit information of the circuit requested by the circuit information acquiring section 105 of the information processing section 100. Then, the acquired circuit information is edited as necessary, and circuit information of a circuit to be reconfigured into the programmable logic circuit 104 is generated.

At the time of editing and generating the circuit information, the editing unit 300 instructs the circuit information obtaining unit 105 to output the programmable logic circuit to the circuit for which circuit information is to be generated for reconfiguration. An inquiry is made to determine whether or not a circuit existing at 104 is included.

When a circuit to be reconfigured includes a circuit existing in the programmable logic circuit 104, the circuit existing in the programmable logic circuit 104 is used as it is. Generate circuit information for reconfiguring the new circuit. Therefore, as the circuit information, the circuit portion existing on the programmable logic circuit is generated as a space. The generated circuit information is provided to the circuit information acquisition unit 105.

The circuit information obtaining unit 105, which has been provided with the circuit information from the editing unit 300, loads the circuit information into the hardware processing unit 103 and reconfigures a circuit based on the circuit information into a programmable logic circuit 104. Then, the circuit information including the arrangement address of the reconfigured circuit is stored in the constituent circuit memory 1.
06 is stored.

As will be described in detail later, since the circuit information has a data structure capable of referring to other circuit information, the editing unit 300 refers to the circuit information requested from the storage unit 200 and refers to the reference information. And a rearrangement process for editing the circuit information based on the result of the reference solution process.

The editing unit 300, in this case,
As described later, the information processing unit 100 is provided in a computer system on a network connected to the information processing unit 100, but may be provided in a computer system integrated with the information processing unit 100.

[Structure of Circuit Information Stored in Storage Unit 200] As shown in FIG. 2, the circuit information 201 stored in the storage unit 200 includes a header unit 202 serving as an additional information unit and a code unit serving as a circuit data unit. It comprises a unit 203. Header section 20
2 includes circuit name information 204 and input / output port information 205
Is described.

In the circuit name information 204, in this example, the circuit name of the programmable logic circuit 104 (hereinafter referred to as “own circuit name”) is described as the identifier ID of its own circuit information. I have. The own circuit name as the identifier ID of the own circuit information is also the name given to the circuit information 201. In this example, as described later, the application program 101 uses its own circuit name as an identifier ID of the circuit information as designation information of a circuit included in the programmable logic circuit 104.

In addition to the own circuit name, the circuit name information 204 of the header section 202 includes, as a reference identifier refID for specifying other circuit information referred to by the circuit information 201, the circuit name of the referenced circuit information. (Hereinafter, referred to as a reference circuit name). Although the own circuit name described in the header section 202 as the identifier ID of the own circuit information is one, the reference circuit name is determined according to the number of the circuit information to be referred to.
A plurality of reference circuit names may be described in the header section 202.

Input / output port information 205 of header section 202
Is described after the description of the circuit name information 204. The input / output port information 205 includes a port type 206 selected from input (IN), output (OUT) or bidirectional (IN / OUT) according to the direction of signal flow to the circuit.
It is composed of port position coordinates (X, Y) 207 in units of logic cells (described later) and port data width (number of bits) 208.

The code section (circuit data section) 203 is composed of a set of pairs of an address ADR and data DT. The address ADR is an address of a configuration memory (described later) that determines a state of a logic cell or wiring configuring the programmable logic circuit 104. The data DT determines the state of a logic cell or a wiring corresponding to the written address of the configuration memory.

The address of the code section 203 of each circuit information 201 stored in the storage section 200 is a specific address (for example, 0x0000 for a 16-bit address).
Etc .: Ox means hexadecimal notation. The same applies hereinafter). As will be described later, by adding a fixed value to this address and offsetting, the address of the code part is converted into an address corresponding to the circuit position actually configured on the programmable logic circuit 104 of the hardware processing unit 103. You.

When the reference circuit name is described in the circuit name information 204 of the header section 202, the circuit information indicated by the reference circuit name is constituted by the circuit information in which the reference circuit name is described. In the circuit, reference circuit information that determines how the circuits are connected is described in the code section 203.

The reference circuit information is described in the code portion of the reference source circuit information as a pair of an address (referred to as a reference address) and a reference circuit name. For example, it is described as the address i and the reference circuit name p, the address k and the reference circuit name q in the example of FIG. As will be described later, the editing unit 300
The reference circuit is obtained by adding the reference address of the reference circuit information to the start address of the code part of the circuit information referred to by the reference circuit name, and combining the offset circuit data with the code part of the reference source circuit information. Is connected to the reference source circuit.

As will be described later, the address AD
Since there is a certain correspondence between R and the logic cell, the editing unit 30
0 calculates the offset coordinates of the input / output port position of the reference circuit from the reference address, and adds the offset coordinates to the input / output port position coordinates of the reference circuit, and outputs the input / output port information of the reference circuit. Link to the header of circuit information.

Circuit information that does not use other circuit information to be referenced does not have a reference circuit name in the header section 202. The circuit information of the minimum unit such as the basic circuit module is stored in the header 2
02 has no reference circuit name. Other circuit information referred to by the reference circuit name is stored in the header section 20.
2 may have a reference circuit name. In the case of such a multi-layer tree structure, the editing unit 300 generates circuit information of the circuit name specified by the acquisition unit 105 by sequentially combining circuit information from the lowest layer circuit information. To

The circuit information of the programmable logic circuit stored in the constituent circuit memory 106 of the circuit information acquisition unit 105 is the circuit information of the circuit name specified by the application program 101. The address of the data section 203 is converted into an arrangement address on the programmable logic circuit 104. Therefore, if the circuit information of the circuit name includes the reference circuit, the reference circuit portion includes the reference address and the reference circuit name. Then, the reference circuit name is described in the header section 202 of the circuit information.

[Hardware Configuration of Information Processing System]
FIG. 3 is a block diagram illustrating a hardware configuration example of the information processing system according to the present embodiment. In the information processing system of this embodiment, the information processing unit 100
The chipset 112 is connected to the host bus 111B of the U111.
Via a memory controller (not shown) included in
For example, a main memory 113 composed of a DRAM is connected.

The host bus 111B is connected to a PCI bus 114 via a host-PCI bus bridge (not shown) included in the chipset 112. PC
The I bus 114 has a programmable logic circuit 116 via a programmable logic circuit interface 115.
The hard disk drive 118 and the communication interface 119 are connected via the hard disk interface 117. Programmable logic circuit 116
Corresponds to the programmable logic circuit 104 of the hardware processing unit 103 in FIG.

[0096] The communication interface 119 is connected to a plurality of computer systems 500 via a network 400 such as a LAN or the Internet. The computer system 500 has at least a storage device such as a CPU (not shown), a main memory (not shown), and a hard disk drive (not shown).

The hard disk read / written by the hard disk drive 118 stores an application program (not shown). The application program is stored in the hard disk interface 11
7, loaded from the hard disk drive 118 to the main memory 113 via the PCI bus 114 and a host-PCI bridge (not shown) included in the chipset 112, and executed by the CPU 111.

The application program may be stored in a storage device (not shown) of one of the computer systems 500 connected to the network 400. In this case, the information processing unit 100 acquires the application program from the computer system 500 connected to the network 400 to the main memory 113 via the communication interface 119 and executes the application program.

Storage device (not shown) of one of computer systems 500 connected to network 400
Configures the storage unit 200 of FIG. 1 by storing circuit information. The hard disk drive 118 of the information processing unit 100 may store the circuit information and configure the storage unit 200 of FIG.

The computer system 500 searches for circuit information stored as the storage unit 200 in FIG.
The function of transferring to “0” is implemented as software as one of the functions of the computer system 500.

The editing unit 300 shown in FIG.
0 connected to any computer system 500
It is implemented as software as one of the functions.
Computer system 5 constituting editing unit 300 of FIG.
00 and the computer system 500 configuring the storage unit 200 in FIG. 1 may be the same computer system or different computer systems.

When the computer system 500 constituting the editing unit 300 of FIG. 1 and the computer system 500 constituting the storage unit 200 of FIG. 1 are different computer systems, they communicate with each other via a network 400.

The circuit information acquisition unit 105 of FIG. 1 of the information processing unit 100 has a function of communicating with the editing unit 300 constituted by any computer system connected to the network 400 via the communication interface 119, and a PC
A programmable logic circuit 1 via a programmable logic circuit interface 115 connected to the I bus 114
16 is implemented in software in the information processing unit 100 as a function including a function of loading circuit data.

As described above, since the circuit information acquisition unit 105 is implemented in software in the information processing unit 100, it can communicate with an application program executed in the information processing unit 100.

The hardware processing section 103 shown in FIG. 1 comprises a programmable logic circuit interface 115 and a programmable logic circuit 116. The hardware processing unit 103 transmits the CP via the programmable logic circuit interface 115 connected to the PCI bus 114.
It has a function of communicating with the application program executed in U111.

[Description of Programmable Logic Circuit of FPGA Type] As described above, in this embodiment, a programmable logic circuit 116 (programmable logic circuit 104 in FIG. 1) is used as a programmable logic circuit of the FPGA type. FIG. 4 shows a plan structure of the programmable logic circuit 50 of the FPGA type, and FIG. 5 shows a block diagram of the internal structure.

This programmable logic circuit 50 has a configuration memory 6 for storing circuit information.
1 and a circuit element 6 composed of a logic cell 51 and a wiring region 52
2 and an input / output terminal 53.

The configuration memory 61 stores E
It is composed of rewritable memory elements such as EPROM and SRAM. The circuit data is composed of a pair of an address ADR and data DT. An address ADR is given to the configuration memory 61 and the address AD
When the data DT paired with the address ADR is stored in the memory cell corresponding to R, the circuit configuration in the logic cell 51 and the logic cell 51 and the input / output terminal 53 are interconnected according to the data DT. The connection state of the wiring region 52 is reconfigured. By rewriting a part of the configuration memory 61, the circuit can be partially reconfigured even when the programmable logic circuit 50 is operating.

The data to be processed is input to the circuit element 62 reconfigured in the programmable logic circuit 50 via the input / output terminal 53, and the processing result is output. An application program (the application program 101 in the example of FIG. 1) specifies a logic cell as a data input destination and a logic cell as a data output source by a control code indicating a cell coordinate corresponding to the position of the logic cell.

[Explanation of the processing operation of the information processing system of the embodiment] The processing operation of the information processing system of the embodiment configured as described above is shown in the configuration diagram of FIG.
This will be described with reference to the flowchart shown in FIG.

An application program 101 started by an information processing apparatus (not shown) executes a series of processing by a CP.
The processing is executed by the U102 or the programmable logic circuit 104 of the hardware processing unit 103. The instruction of the processing from the application program 101 to the CPU 102 is performed in the same procedure as the processing using a normal computer.

The following description is an example of a case where a circuit necessary for the application program 101 to execute a process is reconfigured into a programmable logic circuit 104 using a circuit already configured in the programmable logic circuit 104. is there. That is, the information processing system generates circuit information with reference to the circuit configured in the programmable logic circuit 104, configures the circuit in the programmable logic circuit 104 of the hardware processing unit 103 based on the circuit information, and It shows a procedure for performing processing using the configured circuit.

(Circuit Information Request) As shown in the flowchart of FIG. 6, the application program 101 started by the information processing apparatus (not shown) sends the circuit designation information necessary for the processing executed by the hardware processing unit 103. An instruction is given to the circuit information acquisition unit 105 (step S101). In this example, the circuit name (own circuit name) is used as the circuit designation information.

From the application program 101,
The circuit information acquisition unit 105 that has received the circuit name as the circuit designation information transmits the circuit name to the editing unit 300, and edits the circuit information that can configure the circuit required by the hardware processing unit 103. An instruction is given to the unit 300 (step S102).

(Reference Resolution Processing) The editing unit 300 passes the circuit name received from the acquisition unit 105 to the storage unit 200, and
By inquiring, the circuit information of the circuit name is acquired. As described above, in this example, the circuit information specified by the circuit name refers to other circuit information. Since there is a case, reference resolution processing is performed as processing for knowing the reference circuit name (step S103).

The processing procedure of this reference solution will be described with reference to the flowcharts of FIGS. 7, 8 and 9. FIG.
FIG. 8 is a flowchart of a process executed by the editing unit 300 as the reference solution process, FIG. 8 is a flowchart of a process executed by the storage unit 200 as the reference solution process, and FIG. Part 105
This is the process executed by

First, as shown in FIG.
Stores the circuit name obtained from the circuit information acquisition unit 105 in the storage unit 20
0 is inquired (step S111).

As shown in FIG. 8, when the storage unit 200 detects that there is an inquiry about the circuit name from the editing unit 300 (step S121), the storage unit 200 acquires the circuit name (step S122), and Circuit information 201 corresponding to the circuit name
By examining the header section 202 of the
It is determined based on whether or not a reference circuit name is described (step S123). If the reference circuit name is described, the reference circuit name described in the header section 202 is answered to the editing section 300 (step S124).

When the end notification of the inquiry of the circuit name is not received from the editing unit 300, the storage unit 200 returns to step S121 and waits for the inquiry of the circuit name from the further editing unit 300. When the notification of the end of the inquiry of the circuit name is received from, the reference resolution processing routine of FIG. 8 is ended (step S125).

The editing section 300 determines whether or not there is a reply of the reference circuit name from the storage section 200 in response to the inquiry of the circuit name in step S111 (step S112). Then, the reference resolution processing ends.
If there is a reply of the reference circuit name, the reference circuit name is obtained and stored from the storage unit 200 (step S113).
Then, the acquired reference circuit name is referred to the circuit information acquisition unit 105 (step S114).

As shown in FIG. 9, the circuit information obtaining unit 105
When detecting the inquiry by the reference circuit name from the editing unit 300 in step S131, the reference circuit name is acquired (step S132) and is configured on the programmable logic circuit 104 stored in the configuration circuit memory 106. The circuit name of the reference circuit is checked, and it is determined whether or not the circuit of the reference circuit name is configured on the programmable logic circuit 104 (step S133).

When the circuit having the reference circuit name is formed on the programmable logic circuit 104, the arrangement of the circuit having the reference circuit name stored in the constituent circuit memory 106 on the programmable logic circuit 104 is performed. The address is checked, and the layout address is returned to the editing unit 300 (step S134). If the circuit with the reference circuit name is not configured, in this example, the editing unit 300 is notified that there is no corresponding circuit on the programmable logic circuit 104. Note that, by not returning the arrangement address, the fact that the corresponding circuit does not exist on the programmable logic circuit 104 may be indicated.

The editing unit 300 is provided with the circuit information obtaining unit 10
5 is used to determine whether the circuit of the reference circuit name inquired is configured in the programmable logic circuit 104 based on the response of the arrangement address of the circuit of the reference circuit name or the absence of the corresponding circuit (step S115). If the circuit with the circuit name is configured in the programmable logic circuit 104, the circuit arrangement address from the circuit information acquisition unit 105 is temporarily stored together with the circuit name (step S1).
16). Then, the process proceeds to the next step S120.

On the other hand, if it is determined in step S115 that the circuit having the referred reference circuit name is not configured in the programmable logic circuit 104, the editing unit 300
In order for the circuit corresponding to the reference circuit name received from the storage unit 200 to know the reference circuit name further referred to,
The storage unit 200 is again inquired about the received reference circuit name (step S117).

In response to this inquiry, the storage unit 200 executes the steps after step S121 in the flowchart of FIG. 8 again to check the header part of the circuit information corresponding to the reference circuit name, and finds that the reference circuit name is When the reference circuit name is described, the reference circuit name is answered to the editing unit. When the reference circuit name is not described, the process proceeds to the next processing.

The editing unit 300 determines whether or not there is a reference circuit in the circuit name inquired of the storage unit 200 based on whether or not there is a reply of the reference circuit name from the storage unit 200 (step S118). Is returned, it is acquired and temporarily stored (step S119). If there is no reference circuit, the process proceeds to the next processing step S120.

In step S120, the circuit information obtaining section 1
It is determined whether or not the inquiry to the circuit information acquisition unit 105 and the storage unit 200 has been completed for all the reference circuit names for generating the circuit information of the designated circuit received from step S05. And the above operation is repeated. When the editing unit 300 knows all the reference circuit names referred to by the circuits, the editing unit 300 ends the reference resolution processing.

When the reference resolution is completed by the editing unit 300, the storage unit 200 and the acquisition unit 105 also terminate the reference resolution processing (steps S125 and S1).
35).

As a result, all the circuit names required to configure the circuit having the circuit name requested by the circuit information acquisition unit 105 to the editing unit 300 and, among them, the programmable logic circuit 104 of the hardware processing unit 103 The editing unit 300 can obtain the name of the circuit and the circuit arrangement address.

(Relocation Processing) Next, as shown in FIG.
The editing unit 300 uses the circuit information necessary for generating the circuit information of the circuit name requested from the storage unit 200 by the circuit information acquisition unit 105 to the editing unit 300 based on the information obtained in the above-described reference resolution processing. Are acquired, the circuit information is combined, and a rearrangement process is performed (step S104). FIG. 10 shows the procedure of the rearrangement process.

The editing section 300 first determines whether or not circuit information of a designated circuit is generated by using a circuit on the programmable logic circuit 104 (step S14).
0) If the circuit configured in the programmable logic circuit is not used, step S142 and subsequent steps are executed.

When a circuit configured in the programmable logic circuit 104 is used, the address of the reference circuit name of the circuit to be used is obtained from the circuit data section 203 of the circuit information of the specified circuit name acquired from the storage section 200. That is,
The reference address is extracted, and the programmable logic circuit 104 is extracted.
The offset address is calculated by subtracting the reference address from the arrangement address of the circuit configured in (1) (step S141).

This processing is performed by the programmable logic circuit 10.
4 so that the circuit to be used can be used without changing the arrangement position of the circuit to be used on the basis of the position of the circuit to be used. Is generated by combining the above. After step S141, step S141
Go to step 142 and subsequent steps.

If the circuit configured on the programmable logic circuit 104 is not used in step S140, the offset address is set to the zero address (for example, 0
(x0000).

That is, the editing unit 300 requests the storage unit 200 for the circuit information of the designated circuit received from the circuit information acquisition unit 105 and the circuit information of the reference circuit that refers to the designated circuit as a reference source circuit. In addition, if there is a reference circuit with the reference circuit as a reference source circuit, if there is a reference circuit, circuit information of the reference circuit is also requested, and all necessary circuit information is acquired (step S142).

Here, the circuit information of the circuit in the programmable logic circuit 104 may also be obtained from the storage unit 200. In the case of this embodiment, however, the reference circuit recognized as existing in the programmable logic circuit 104 The circuit information is unnecessary for generation of the line information, and the transfer time of the circuit information from the storage unit 200 to the editing unit 300 is wasted.

The storage unit 200 provides the circuit information of the requested circuit name to the editing unit 300, and the editing unit 300 receives the information (step S143). Note that the circuit information of the designated circuit may be obtained from the storage unit 200 at the time of inquiring the first circuit name for reference resolution.

When the circuit information is obtained from the storage unit 200 as described above, the editing unit 300 determines whether or not the circuit is a circuit existing on the programmable logic circuit 104 (step S144). If not, the editing unit 300 adds the reference address of the reference source circuit and the offset address calculated in step S141 to the address of the received circuit data of the reference circuit, and performs offsetting. Link to the code part (step S145). This processing will be described later in detail with a specific example.

In step S145, if it is determined in step S140 that the circuit formed on the programmable logic circuit 104 is not used, the offset address is a zero address. Is added. That is, the offset address is not added.

As a result of the above combination, it is determined whether or not the generated circuit fits in the circuit configuration area on the programmable logic circuit 104 (step S146).
Proceeding to step S147, all the rearrangement processes are redone. That is, since the circuit configured on the programmable logic circuit 104 cannot be used, the rearrangement is performed again including the circuit portion to be used. Then, the rearrangement processing routine ends.

If it is determined in step S144 that the reference circuit is constituted by the programmable logic circuit 104, step S145 for linking the circuit data to the code part of the circuit information of the reference source is not performed, and Step S
Proceed to 146.

If it is determined in step S146 that the combined circuit fits in the circuit configuration area on the programmable logic circuit 104, the flow advances to step S148. In step S148, the editing unit 300 calculates the offset cell coordinates of the input / output port position of the reference circuit from the reference address or, if the circuit of the programmable logic circuit 104 is used, from the reference address and the offset address. Then, the offset cell coordinates are added to the input / output port position coordinates of the reference circuit, and the result is coupled to the header part of the circuit information of the reference source circuit. As for this processing, a specific example will be described later in detail.

The editing section 300 repeats the above procedure until the above procedure is performed for all circuit names (step S149).

When the rearrangement process is completed as described above, as shown in FIG. 6, the editing unit 300 provides the generated circuit information to the circuit information acquisition unit 105 (Step S).
105). When the circuit on the programmable logic circuit 104 is used, the generated circuit information does not include the circuit information of the circuit part because the step S145 is bypassed.

(Load) The circuit information acquisition unit 105 loads the circuit data described in the code part of the circuit information obtained from the editing unit 300 into the hardware processing unit 103 and stores the circuit data in the programmable logic circuit 104. Reconfigure (step S106), and provide the input / output port information described in the header section to the application program 101 (step S107).

When circuit information is generated in a state where a circuit existing in the programmable logic circuit 104 is used, another circuit part is coupled to the existing circuit as it is. In this manner, the specified circuit is formed on the programmable logic circuit 104. Then, the circuit information including the arrangement address of the formed circuit is stored in the constituent circuit memory 106.

(Processing by Application) The hardware processing unit 103 inputs and outputs data to and from the reconfigured circuit in the programmable logic circuit 104 according to the control code from the application program 101 based on the input / output port information. Logic circuit 10
Then, information processing using the circuit reconfigured as No. 4 is performed (step S108).

[Example of Processing by Information Processing System:
Line Drawing Processing] Next, a more detailed example in which the information processing system of the above embodiment is applied to image processing will be described. In this embodiment, a multi-tone image is converted into a line image by performing three types of processing, namely, binarization processing, edge detection processing, and inversion processing on image data using three types of image filters described below. This is the case of the line drawing process. In the following description, the edge detection circuit having the circuit name “Laplace” used in the above-described edge detection processing is replaced with the programmable logic circuit 104 of the hardware processing unit 103.
In this case, it is already configured. First, the above three types of image filters will be described.

[Explanation of Filter] In the spatial filter processing which is one of the image processing, an operation is performed on one or a plurality of pixels of an image file composed of unit pixels. This is the pixel (data x _{l, m)} near the pixel (data p _{l, m)} of the mask data filter _l, summed over the _m, the pixel value x after processing are multiplied by coefficients N _The processing to be obtained as _{l and m} can be expressed as in the following equation (1). Here, the spatial filter can execute various processes by changing the values of the mask data filter _{l, m} and the coefficient N.

X _{l, m} = N × {l−1 to l + 1} {{m−1 to m + 1}} (p _{l, m} × filter _{l, m} ) (1) where {l− 1 ~ l + 1} Σ () means the summation of the values in () from (l-1) to (l + 1). Similarly, {m-1 to m +
1} Σ () means the operation of the sum of the values in () from (m-1) to (m + 1).

(Edge detection Laplacian filter) FIG. 11 shows a Lap detection filter for detecting an edge by the second derivative.
It is an example of mask data of an image filter called a lacian filter. By performing this filter processing, it is possible to detect an outline of an image.

FIG. 12 shows an example of a circuit configuration of a circuit (circuit name Laplace) for realizing the Laplacian filter processing of FIG. First, p [l] [m] and p [l-
1] [m], p [l] [m-1], p [l] [m + 1], p [l + 1] [m] for 5 pixel data, for example, 8 bit data per pixel To the circuit.

The transferred data for five pixels is input to the input ports LaplaceIn0 and LaplaceIn of the circuit.
1, LaplaceIn2, LaplaceIn3, L
Each of the registers 301, 302, 303, 304, and 305 is input to the
Is input to The input data is the output D of the register.
1, D2, D3, D4, and D5, outputs D1 and D2 are input to an adder 311, and outputs D3 and D4 are added to an adder 31.
2 is input. The output A13 of the adder 313 is calculated by the adders 311, 312 and 313.
A13 = p [l-1] [m] + p [l] [m-1] + p [l] [m + 1] + p [l +
1] [m].

On the other hand, the shifter 321 shifts the output D5 of the register 305 upward by 2 bits and connects it, and always inputs 0 to the lower 2 bits.
14 is A14 = 4 × p [l] [m].

The shifter 321 is operated by the subtractor 314.
Is subtracted from the output A14 of the adder 313, and the output A15 of the subtractor 314 is A15 = 4
× p [l] [m]-(p [l-1] [m] + p [l] [m-1] + p [l]
[m + 1] + p [l + 1] [m]), and the result is output port Lap
It is output to placeOut0. Thus, the Laplacian filter processing in the unit mask area is completed. Thereafter, by repeating this processing, processing of the entire image is performed.

(Binary Binary Filter) FIG.
Is a circuit for realizing the binarization filter processing (circuit name Bin)
2) shows an example of the circuit configuration of FIG. In this example,
Data per pixel processes image data of 8 bits. The logic cell of the programmable logic circuit 104 used has an input / output signal line of 8 bits. Therefore,
An 8-bit register and an inverter described below are realized by one logical cell, and an 8-bit comparator and selector are realized by two logical cells.

In FIG. 13, data for one pixel is input to the input port BinaryIn0, and is held in the register 401 at the first clock. The register 402 holds a value that is a threshold value for binarization in advance.

At the next clock, the comparator 403
The input data held in the register 401 is compared with the threshold value held in the register 402. If the value of the input data is smaller than the threshold, the “<” output is in a low level state. Otherwise, the "<" output retains the default high state.

The “<” output of the comparator 403 is input to the S input of the selector 404. When the S input is in the high level state, the 8-bit “0xFF (hexadecimal notation)”
Is output from the 8-bit Y output, and when the S input is in a low level state, the value of the B input to which 8-bit "0x00" is input is changed to the 8-bit Y output. Output from

That is, when the input data is smaller than the threshold value, the S input of the selector 404 goes to a low level state, and BinaryOut0 to which the Y output is connected outputs 8-bit "0x00". In this case, the S input of the selector 404 becomes a high level state, and 8-bit “0xFF” is output from BinaryOut0 to which the Y output is connected.
Pixels are binarized.

(Inverted Inverse Filter) FIG.
Is a circuit that implements inversion processing (circuit name Inverse)
2 shows an example of the circuit configuration of FIG. In this embodiment, image data of 8 bits per pixel is processed.

In FIG. 14, data for one pixel is input to the input port InverseIn0, and data obtained by inverting the value of each data bit is output from InverseOut0. That is, the pixels are inverted.

[Address Configuration of FPGA-type Programmable Logic Circuit] The FPGA-type programmable logic circuit used in this embodiment has a total of 1024 in which 32 are arranged in the column direction and 32 are arranged in the row direction.
It is composed of logic cells. One logic cell is 64
Is set in the configuration memory of the address,
The configuration memory of one address holds 8-bit data. That is, one logic cell is
It is set with 64 bytes of circuit data.

FIG. 15 shows a method of setting the address of the configuration memory. The cell coordinates of the programmable logic circuit are defined with the lower left as the origin (0,0).
The configuration memory for setting one logic cell corresponds to an 8 × 8 memory space, and the entire programmable logic space forms a 256 × 256 memory space. The address is a 16-bit address "0x000
0 ”as the start address, the origin of the cell coordinates (0, 0)
To “0xFFFF”.

At this time, the address and the cell coordinates have the following relationship. That is, as shown in the table of FIG. 15, the upper 8 bits A [15:] of the 16-bit address A [15: 0].
8] at the column address of the 256 × 256 memory space,
The lower 8 bits A [7: 0] correspond to the row addresses in the memory space, respectively.

Then, the 16-bit address A [15:
0] is the 3 bits A [1] in the column cell coordinates.
0: 8] (lower 3 bits of an 8-bit column address) respectively correspond to column memory coordinates. Also, 5-bit A [7: 3] of the 16-bit address A [15: 0] (upper 5 bits of the 8-bit row address) is used as 3-bit A [2: 0] (8-bit row The lower 3 bits of the address) correspond to the row memory coordinates, respectively. By using this relationship, the offset cell coordinates of the input / output port information can be easily known from the reference address.

(Procedure of Line Drawing Processing) Next, the processing procedure of the application program 101 for performing line drawing processing will be described. The application program 101 performs another image processing prior to the line drawing processing as shown in FIG.
The address “0x201” of the programmable logic circuit 104
8 "constitutes an edge detection circuit (circuit name" Laplace "). The circuit information of the circuit name “image processing” in FIG.
It is equal to the contents stored in the constituent circuit memory 106 of the circuit information acquisition unit 105.

(Line Image Processing Reference Solution) The application program 101 transmits the circuit name “LineArt” of the line image processing to the circuit information acquisition unit 105 and instructs the hardware processing unit 103 to configure the line image processing circuit. (Step S101 in FIG. 6 described above).

Then, as described above, the circuit information acquisition unit 105 transmits the circuit name “LineArt” of the line drawing processing to the editing unit 300, and the editing unit 300
According to the procedure shown in FIGS. 9 and 10, reference resolution processing and rearrangement processing are performed, and circuit information of a circuit for line drawing processing is generated using circuit information stored in the storage unit 200.

In the case of this example, as shown in FIG. 16, the circuit information of the circuit name “LineArt” includes the reference circuit name “B
inary "," Laplace "and" Inver "
“se” is described in the header portion, and the code portion (circuit data portion) has a circuit name “Binary”.
With reference addresses “0x0000”, “0x001”
0, 0x0020, 0x0030, 0x0
040 ”and the circuit name“ Inverses ”at the address“ 0x1800 ”.
"e" is described at an address "0x3800" so as to be referred to.

Therefore, in the reference solution processing (step S103 in FIG. 6, see FIGS. 7 to 9), the storage unit 200
Responds to the inquiry of the circuit name “LineArt” from the editing unit 300, by referring to the reference circuit names “Binary” and “Lapl”.
ace "and" Inverse ".

Next, the editing unit 300 stores the data in the storage unit 200
Inquiry is made to the circuit information acquisition unit 105 as to whether or not the circuits having the reference circuit names are configured on the programmable logic circuit 104 of the hardware processing unit 103 using the reference circuit names acquired from (step S114). .

If the reference circuit is configured on the programmable logic circuit 104, the editing unit 300 acquires and holds the arrangement address (step S116), and then places the next reference circuit on the programmable logic circuit 104. An inquiry is made to the circuit information acquisition unit 105 as to whether or not it is configured.

If the reference circuit is not configured on the programmable logic circuit 104, the storage unit 200 is inquired as to whether the reference circuit refers to another circuit (step S117). As a result of this inquiry, if another circuit is referred to, the above-described reference resolution processing is performed for the reference circuit. When the reference resolution processing is performed on all the reference circuits, the reference resolution ends.

In the case of this embodiment, first, the circuit name "B
It is checked whether the binary circuit of “inary” is configured on the programmable logic circuit 104. In the case of this example, since the binarization circuit with the circuit name “Bianry” is not configured on the programmable logic circuit 104,
The circuit information acquisition unit 105 returns the fact to the editing unit 300. Therefore, the editing unit 300 inquires the storage unit 200 of a reference circuit for the circuit name “Bianry”. At this time, since the binarized circuit with the circuit name “Binary” does not refer to another circuit, the reference circuit name from the storage unit 200 does not return to the editing unit 300.

Next, the editing unit 300 outputs the circuit name "Lapl
When the circuit information acquisition unit 105 is queried for the edge detection circuit of “ace”, the circuit information acquisition unit 105 returns the layout address “0x2018” to the editing unit 300 because it exists on the programmable logic circuit 104. Therefore, the editing unit 300 recognizes that the circuit with the circuit name “Laplace” exists on the programmable logic circuit 104, acquires and stores the arrangement address (steps S115 and S116 in FIG. 7). This edge detection circuit “L
Inquiry of the reference circuit to the storage unit 200 for “place” is not performed because the programmable logic circuit 104 does not need this reference because this circuit exists.

[0177] Finally, the editing unit 300 outputs the circuit name "Inv
When the circuit information obtaining unit 105 is inquired of the inversion circuit of “erse”, since it is not configured on the programmable logic circuit 104, a reply to that effect is returned to the editing unit 300. Therefore, the editing unit 300 stores in the storage unit 200
When the circuit name “Invers” is queried, the circuit name “Inv”
The reference circuit name does not return because the inversion circuit of "erse" does not refer to another circuit. As described above, the reference to all the reference circuits has been completed, and the reference resolution ends.

(Line drawing processing rearrangement) The editing unit 300 includes a binarization circuit “Binary” and an edge detection circuit “Lapla”.
ce ”and the inversion circuit“ Inverse ”, the relative relationship of each circuit module is determined based on the reference relationship of the respective circuits.

That is, the edge detection circuit “Laplac”
Since “e” is already configured at the arrangement address “0x2018” of the programmable logic circuit 104 of the processing unit 103, the editing unit 300 outputs the remaining binarization circuit “Bin
ary ”and the circuit information of the inversion circuit“ Inverse ”are acquired from the storage unit 200, and the position coordinates of the circuit information of each circuit module are translated based on the relative positional relationship.

Since the circuit information is described in a relocatable format, an offset address corresponding to the origin position of the circuit module based on the position of the edge detection circuit "Laplace" is obtained (step S14 in FIG. 10).
1).

In the case of this embodiment, this offset address is (0x2018-0x1800 = 0x081).
8). Each location address of the reference circuit is obtained by adding the offset address and the reference address.

That is, since the circuit information of the circuit name “LineArt” is configured as shown in FIG.
Of the binarization circuits “Binary” are “0x
0000 + 0x0818 "," 0x0010 + 0x08
18 "," 0x0020 + 0x0818 "," 0x00
30 + 0x0818 "," 0x0040 + 0x081 "
8 "to determine the arrangement address by offsetting the address, and the inverting circuit" Inverse "
The layout address is determined by offsetting by “0x3800 + 0x0818”, and the circuit name is respectively “LineArt”
As circuit information.

In this case, the edge detection circuit “Laplac
Since “e” exists at the arrangement address “0x1800 + 0x0818 = 0x0218” on the programmable logic circuit 104, this part is a space without circuit information in the circuit information of the circuit name “LineArt”. Are combined (step S1
46) On the programmable logic circuit 104, the three circuits are combined to generate a line drawing processing circuit.

As described above, the circuit data of the binarization circuit “Binary” for which the rearrangement has been completed and the inversion circuit “I”
The entire circuit information including the circuit data of “nverse” and the space corresponding to the edge detection circuit “Laplace” configured in the programmable logic circuit is transferred to the circuit information acquisition unit 105 as a line drawing processing circuit “LineArt”. The circuit information acquisition unit 105 downloads the received circuit information to the programmable logic circuit 104,
Perform circuit reconfiguration.

Thus, as described above, the binarization circuit "Binary" and the edge detection circuit "Laplac"
e) and a line drawing processing circuit “LineArt” composed of an inversion circuit “Inverse”
04. A line drawing processing circuit “LineArt” configured on the programmable logic circuit 104 is shown in FIG.
FIG.

(Execution of Line Drawing Processing Application) Since the line drawing processing circuit requested by the application program 101 has been reconfigured on the programmable logic circuit 104, by executing processing using this circuit, a desired processing is performed. Line drawing processing is performed.

[Other Embodiments] In the reference resolution processing in the above-described embodiment, the editing section 300 causes the circuit information acquisition section 105 to change the reference circuit to the programmable logic circuit 104.
Query whether it is configured above,
The reference resolution processing can also be performed as follows.

That is, since the circuit information acquiring unit 105 stores the information of the circuits configured on the programmable logic circuit 104 in the constituent circuit memory 106, the circuit information acquiring unit 105 receives the circuit designation information from the application program 101 and edits the information. When requesting the unit 300 to generate the circuit, the editing unit 300 adds together the circuit name and arrangement address information configured on the programmable logic circuit 104.
Can be notified. Thereby, the inquiry from the editing unit 300 to the circuit information acquisition unit 105 can be eliminated.

In this case, the editing unit 300 needs an internal storage unit for storing the information of the circuit name and the arrangement address notified from the circuit information acquisition unit 105. The reference resolution procedure in this case is the same as that described above except that the reference circuit is configured on the programmable logic circuit 104 of the processing unit 103, instead of querying the circuit information acquisition unit 105, instead of querying the internal storage unit. Same as the procedure.

In the above description of the embodiment, reference is made only to the case where the reference circuit constituting the circuit specified by the application program 101 is formed on the programmable logic circuit 104. However, when the specified circuit itself is configured on the programmable logic circuit 104, the editing unit 300 does not need to reconfigure the circuit information at all, and the circuit existing on the programmable logic circuit 104 is deleted. , Can be used as is.

That is, the circuit information acquisition unit 105 is the programmable logic circuit 104 of the hardware processing unit 103.
The information of the circuit configured above is stored in the constituent circuit memory 10.
6, the circuit information acquisition unit 105 can detect whether the circuit specified by the specification information from the application program 101 is a circuit existing on the component circuit memory 106.

If the designated circuit exists in the programmable logic circuit 104, it is not necessary to instruct the editing unit 300 to edit the circuit information as described above, and the designated circuit exists in the programmable logic circuit 104. The processing can be performed by using the circuit. However, in that case, the circuit information acquisition unit 105 notifies the application program 101 of the position information of the input port and the output port of the existing circuit. As a result, the application program 101 can execute processing by inputting necessary input data to the input port of the circuit and obtaining a processing result from the output port.

[0193]

As described above, according to the present invention, circuit information of a circuit to be reconfigured is generated in a state where a circuit already configured as a programmable logic circuit is used as it is, so that the circuit information The reconstruction by
The time required to configure a circuit on the programmable logic circuit can be saved, and the time required for reconfiguration can be reduced. Further, since the circuit on the programmable logic circuit can be used, the use efficiency of the programmable logic circuit can be improved.

According to the present invention, in an information processing system for processing at least a part of an application program by a programmable logic circuit, there is provided an information processing system which does not need to have circuit information of the programmable logic circuit in advance. it can.

Further, according to the present invention, it is not necessary to generate circuit information in advance before starting an application program, and a circuit existing on the programmable logic circuit when the circuit information is generated can be used. Meanwhile, it is possible to generate circuit information for efficient reconfiguration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall outline of an embodiment of an information processing system according to the present invention.

FIG. 2 is a diagram for describing circuit information management in the embodiment.

FIG. 3 is a hardware configuration diagram of an embodiment of an information processing system according to the present invention.

FIG. 4 is a diagram for explaining an FPGA type programmable logic circuit;

FIG. 5 is a diagram illustrating an FPGA type programmable logic circuit.

FIG. 6 is a flowchart of a specific processing procedure according to the embodiment of the information processing system according to the present invention;

FIG. 7 is a flowchart of a detailed procedure of a part of the process of the flowchart of FIG. 6;

FIG. 8 is a flowchart of a detailed procedure of a part of the process of the flowchart of FIG. 6;

FIG. 9 is a flowchart of a detailed procedure of a part of the process of the flowchart of FIG. 6;

FIG. 10 is a flowchart of a detailed procedure of a part of the process of the flowchart of FIG. 6;

FIG. 11 is a diagram for explaining an example of a specific process used in the embodiment of the information processing system according to the present invention.

FIG. 12 is a diagram illustrating an example of a circuit configured in a programmable logic circuit.

FIG. 13 is a diagram illustrating a circuit example configured in a programmable logic circuit.

FIG. 14 is a diagram showing an example of a circuit configured in a programmable logic circuit.

FIG. 15 is a diagram illustrating an address arrangement for forming a circuit in a programmable logic circuit in the embodiment;

FIG. 16 is a diagram illustrating a specific processing procedure used in the embodiment of the information processing system according to the present invention;

FIG. 17 is a diagram illustrating an example of a circuit configured in a programmable logic circuit.

FIG. 18 is a diagram illustrating an example of a conventional information processing system.

19 is a diagram illustrating a circuit example of a programmable logic circuit generated in the conventional example of FIG. 18;

FIG. 20 is a diagram for explaining another example of the conventional information processing system.

DESCRIPTION OF SYMBOLS 100 information processing section 101 application program 102 CPU 103 hardware processing section (processing means) 104 programmable logic circuit 105 circuit information acquisition section (acquisition means) 106 constituent circuit memory 200 storage section 300 editing section 201 circuit information 202 Header part (additional information part) 203 Code part (circuit data part) ADR address DT Circuit data 400 Network 500 Computer system

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiichi Yamada 430 Sakai Nakai-cho, Kanagawa Prefecture Green Tech Nakai Fuji Xerox Co., Ltd. (72) Inventor Hiroyuki Miyake 430 Sakai-Nakai-cho Sakaigami, Kanagawa Prefecture Green Tech Nakai Fuji Xerox Co., Ltd. In-house (72) Inventor Eigo Nakagawa 430, Nakai-cho, Ashigami-gun, Kanagawa Prefecture Green Tech Nakai Fuji Xerox Co., Ltd. F-term (reference) 5F064 AA08 BB09 BB13 BB15 DD01 DD25 DD47 HH06 HH11 HH12

Claims (7)

[Claims] An information processing system for processing at least a part of processing by an application program by a programmable logic circuit, comprising: the programmable logic circuit, wherein a circuit configured in the programmable logic circuit is executed by an instruction from the application program. Processing means for performing processing using the same; storage means for storing a plurality of pieces of circuit information for configuring the circuit in the programmable logic circuit; circuit information of one circuit designated by designation information; Editing means having a function of generating using a plurality of circuit information stored in the means, information specified by the application program to specify a circuit to be configured in the programmable logic circuit, as the specified information, Hand over to the editing means,
The circuit information of the circuit designated by the designation information coming from the editing means is obtained, and the circuit information is used to configure the designated circuit in the programmable logic circuit of the processing means, and to be configured in the programmable logic circuit. Acquiring means for storing information of a circuit being provided, wherein the editing means is configured in the programmable logic circuit obtained from the acquiring means when generating circuit information of the circuit specified by the designation information. An information processing system for generating the circuit information in a state where the circuit part configured in the programmable logic circuit is used without being reconfigured with reference to the information of the circuit in question. 2. The circuit information included in the programmable logic circuit stored in the acquisition unit includes a circuit identifier and information on the arrangement of the circuit on the programmable logic circuit. By referring to the identifier of the circuit and the placement information, when the circuit information of the circuit specified by the specification information can be generated in a state where the circuit configured in the programmable logic circuit can be used, The information processing system according to claim 1, wherein the circuit information is generated in a state where a circuit portion configured in a programmable logic circuit is used without being reconfigured. 3. A method according to claim 1, wherein each of the plurality of circuit information stored in said storage means has an identifier of its own circuit information, and a part or all of said circuit information is constituted by other circuit information. And an identifier of the other circuit information as a reference identifier as circuit data for configuring a circuit in the programmable logic circuit, wherein the editing unit is a circuit specified by the specification information from the acquisition unit. And generating the circuit information of (a) by obtaining circuit information of the designated circuit and other circuit information indicated by the reference identifier from the storage means.
The information processing system according to claim 1, wherein the editing unit refers to the acquisition unit by using the reference identifier for the existence of the circuit specified by the reference identifier obtained from the storage unit. While recognizing that the circuit indicated by the reference identifier is configured, from the obtaining unit, obtain the arrangement information of the circuit configured in the programmable logic circuit, and use the circuit information obtained from the storage unit. An information processing system, wherein the circuit information is generated in a state where a circuit portion included in the programmable logic circuit is used without being reconfigured. 4. The information processing system according to claim 3, wherein the editing unit, in response to the specification information from the acquisition unit, stores circuit information of a circuit specified by the specification information.
Inquiring the storage means by the identifier, the storage means edits the reference identifier when the circuit information indicated by the identifier at the time of the inquiry includes the reference identifier in response to the inquiry from the editing means. Returning to the means, the editing means inquires of the obtaining means by using the reference identifier for the existence of the circuit specified by the reference identifier obtained from the storage means, and the obtaining means responds to the inquiry from the editing means When the circuit indicated by the reference identifier at the time of the inquiry is present in the programmable logic circuit, the layout information of the circuit on the programmable logic circuit is returned to the editing means, and the editing means receiving the layout information Using the reference identifier of a circuit that does not exist in the programmable logic circuit obtained from the storage means, An information processing system comprising: acquiring the other circuit information indicated by (1), and generating the circuit information in a state where a circuit portion included in the programmable logic circuit is used without being reconfigured. 5. When each of a plurality of circuit information stored in said storage means has an identifier of its own circuit information and a part or all of said circuit information is constituted by other circuit information, And an identifier of the other circuit information as a reference identifier as circuit data for configuring a circuit in the programmable logic circuit, wherein the editing unit is a circuit specified by the specification information from the acquisition unit. And generating the circuit information of (a) by obtaining circuit information of the designated circuit and other circuit information indicated by the reference identifier from the storage means.
The information processing system according to claim 1, wherein the acquisition unit sends information of a circuit configured in the programmable logic circuit to the editing unit together with the designation information, and the editing unit sends the designation information from the acquisition unit to the designation information from the acquisition unit. Correspondingly, the circuit information of the circuit specified by this specification information is
Inquiring the storage means by the identifier, the storage means edits the reference identifier when the circuit information indicated by the identifier at the time of the inquiry includes the reference identifier in response to the inquiry from the editing means. Returning to the means, the editing means refers to the information of the circuit configured in the programmable logic circuit obtained from the obtaining means by using the reference identifier of the existence of the circuit specified by the reference identifier obtained from the storage means. By doing so, it is determined whether the circuit indicated by the reference identifier of the circuit information of the circuit specified by the specification information exists in the programmable logic circuit, and the circuit not existing in the programmable logic circuit obtained from the storage means Acquiring the other circuit information indicated by the reference identifier from the storage means using the reference identifier of the Maburu circuit portion configured in a logic circuit in a state of use, without the need to reconfigure, an information processing system and generating the circuit information. 6. The information processing system according to claim 1, wherein each of the plurality of circuit information stored in the storage means includes a circuit data part and an additional information part thereof, and the additional information part is In the case where a part or all of the circuit information is configured by other circuit information, the identifier of the other circuit information is included as a reference identifier. The unit is described as a pair of an address of a configuration memory of the programmable logic circuit and circuit data stored at the address, and a part or all of the circuit information is configured by other circuit information. In this case, part or all of the circuit data of the circuit information is described using the reference identifier, and the reference identifier is The information is described as circuit data of an address corresponding to a position referring to the other circuit information, and the editing unit corresponds to the specification information from the acquisition unit, and the circuit specified by the specification information The memory information is referred to the storage means by the identifier, and the storage means responds to the inquiry from the editing means, and the additional information section of the circuit information indicated by the identifier at the time of the inquiry refers to the reference identifier. If it includes, the reference identifier is returned to the editing unit, and the editing unit acquires the other circuit information from the storage unit using the reference identifier acquired from the storage unit, and acquires the acquired other circuit information. The circuit information is indicated by an address in which a reference identifier is described as circuit data of circuit information of the circuit specified by the specification information, and a reference identifier existing in the processing means. A difference address from the address of the circuit to be connected to all the addresses of the circuit data portion of the other circuit information corresponding to the reference identifier, and combining the address with the circuit information in which the reference identifier is described. Information processing system. 7. The information processing system according to claim 1, wherein a part constituting said storage means, a part constituting said editing means, and a part constituting said obtaining means and processing means. Is connected through a network.