JP2000122929A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly efficient non-volatile memory architecture. SOLUTION: In this information processor, a cache memory 11, DRAM (dynamic random access memory) 20 and a flash memory 30 are connected to respective system buses. When the PP(page present) bit of an address conversion table 43 shows the absence of a page and the LD(line dirty) bit of the cache memory 11 shows that the line is updated, namely, when the line in the cache memory 11 becomes dirty even if the page does not exist in DRAM 20, a page fault occurs and the page which becomes dirty is paged in DRAM 20 from the flash memory 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory management technique in an information processing apparatus using a flash memory.

[0002]

2. Description of the Related Art DRAM (dynamic random access memory) and SRAM
(Static random access memory: static rando
A flash memory (batch erase EEPROM) is used as one of the important semiconductor memories along with the m access memory. While flash memory has the advantages of non-volatility, large capacity, and high-speed reading, it has the disadvantage that it requires a long time for erasing and writing, and that the guaranteed number of writes is very small compared to DRAM and SRAM. It is.

Japanese Patent Application Laid-Open No. Hei 7-114499 discloses an information processing apparatus including a processor having a paging mechanism, a DRAM, and a flash memory in order to take advantage of the above-mentioned flash memory. According to this, a flash memory is basically treated as a virtual memory, and information is referred to via a DRAM which is a main memory. However, only when a reference target is an instruction page, the flash memory is directly read from the flash memory. It has a reading function.

[0004]

SUMMARY OF THE INVENTION The above-mentioned JP-A-7-114
According to the information processing apparatus disclosed in Japanese Patent No. 499, basically, a page fault is caused and a page in is performed from the flash memory to the DRAM. Then, only the updated dirty page is paged out from the DRAM to the flash memory. The page of executable code is accessed directly from the flash memory without page-in from the flash memory to the DRAM. However, as a result, there is a problem that a page fault for storing information that is only read out in the DRAM prolongs the interruption time of the processing of the processor.

An object of the present invention is to provide a highly efficient nonvolatile memory architecture for an information processing device.

[0006]

SUMMARY OF THE INVENTION The present invention employs an information processing apparatus having a cache memory, a DRAM (or an SRAM), and a flash memory connected to a system bus, respectively. Not only information that is known to be read-only in advance but also data that may be rewritten, when a read miss occurs in the cache memory, unnecessary fetching is performed directly from the flash memory to the cache memory without passing through the DRAM. The purpose is to transfer information and reduce the capacity of the DRAM.

More specifically, according to the present invention, reference to information is performed via a cache memory. At the time of reading, no page-in is performed on the DRAM. Then, a page fault is caused by combining the state of the cache memory and the state of the page. In other words, a page fault occurs when a line in the cache memory becomes dirty even though there is no page in the DRAM, and the dirty page is paged into the DRAM from the flash memory.

[0008]

FIG. 1 shows an example of a configuration of an information processing apparatus according to the present invention. In FIG. 1, reference numeral 10 denotes a processor having a paging mechanism, 11 denotes a small-capacity cache memory, 12 denotes a system bus, and 20 denotes a medium-capacity DRA.
M and 30 are large-capacity flash memories. The processor 10 transmits a TLB (translation loL) for paging.
ok-aside buffer). The state management (tag management) of the cache memory 11 is performed by a so-called write-back method. The information processing apparatus of FIG.
The virtual address space, which is a virtual space, is provided to the program irrespective of the physical address space where 0 and 30 exist. Further, in the example of FIG. 1, “priority read” and “non-priority write” are adopted as an access method to the flash memory 30. That is, information is directly read from the flash memory 30 except when the updated information is in the DRAM 20, while writing is always performed on the DRAM 20. Since the read speed of the flash memory 30 is high, the priority read can avoid performance degradation due to page faults. Also, due to the locality of reference, the frequency of updating the flash memory 30 can be reduced by performing non-priority writing. In the configuration of FIG.
M20 may be replaced with an SRAM.

FIG. 2 shows details of a memory architecture in the information processing apparatus of FIG. In FIG.
41 is a logical address, 42 is a physical address, 43 is an address conversion table, and 44 and 45 are comparators for hit / miss determination. Each entry of the cache memory 11 has an LV (line valid) bit, an LD
(Line dirty) bits. Each entry of the address conversion table 43 is a PP (page present).
Bit, a PD (page dirty) bit, and a PR (property) bit.

According to the configuration of FIG. 2, the cache memory 1
The information stored in 1 is managed by a cache tag,
Whether or not a page exists in the DRAM 20 is managed by the address conversion table 43. In this configuration, a page fault occurs when a write access by the processor 10 miss-hits and there is no page containing the information in the DRAM 20. On the other hand, when a miss occurs during reading and a page fault occurs, information is directly fetched into the cache memory 11. That is, the page does not exist in the DRAM 20 but the cache memory 1
1 exists. There is no problem that the information fetched into the cache memory 11 is evicted from the cache memory 11 without being updated. When this information is updated in the cache memory 11, a page fault occurs. This means that the updated information will eventually have to be written back to the flash memory 30,
By writing back via the AM 20, the writing speed to the flash memory 30 is low and the frequency of updating the flash memory 30 can be reduced. In the case of a write-back cache, a page fault may be caused when it becomes necessary to replace updated information. The replacement algorithm is, for example, LRU (least recently used).

More specifically, the access attribute of each page indicated by the PR bit in the address conversion table 43 is determined, and the “read” page is fetched directly from the flash memory 30 to the cache memory 11.
Since the page is not replaced in the DRAM 20,
The PP bit of the address conversion table 43 does not stand. Next, in the case where the information in the page having the attribute of “write” is “read”, the cache memory 1
1 will be described.

FIG. 3 shows the state of the page and the cache line, and the state of information having the attribute of "write" in each state. The information in the page having the attribute of “write” is transferred from the flash memory 30 to the cache memory 1
1 (the page does not exist in the DRAM 20 and is clean, the information exists in the line of the cache memory 11 and is clean), and then the information is updated in the cache line (the page is in the DRAM 20).
, But is dirty, and the information exists in the line of the cache memory 11 and is dirty. ), It is necessary to reflect the update result in the DRAM 20 and the flash memory 30. Therefore, when the cache line is updated, that is, when it becomes necessary to rewrite the cache line, a page fault occurs, and the corresponding page is replaced from the flash memory 30 into the DRAM 20. As a result, only the information that needs to be written back to the flash memory 30 is replaced in the DRAM 20, so that the capacity of the DRAM 20 can be reduced. The page on the flash memory 30 replaced in the DRAM 20 is erased as appropriate in preparation for updating information.

When a write miss occurs in the cache memory 11, the corresponding page is immediately replaced in the DRAM 20.

In the information processing apparatus shown in FIG. 1, the logical address of the processor 10 is subjected to one or two address conversions. These are called one-level address translation and two-level address translation, respectively.

FIG. 4 shows one-level address conversion in the information processing apparatus of FIG. Address conversion is performed only once from a logical address to a physical address. D
The RAM 20 and the flash memory 30 are allocated on the same physical address space so as not to overlap each other. Next, an access procedure will be described for each logical address area.

(A) Read [address conversion area] (1, 2 in FIG. 4): The logical address output by the processor 10 is converted into a physical address in an address conversion table, and is directly accessed from the flash memory 30 because of read access. Read information.

(B) Writing [address conversion area] (3-1 to 3-4 in FIG. 4):
1) A page fault occurs because the page to be written does not exist on the DRAM 20. Next, the page at the address P (2) of the flash memory 30 is stored in the DRAM 2
0 is replaced at address P (8), the address conversion table is updated, and the replacement process is completed (3).
-2). Then, address conversion is performed, and P
(8) Write to the address (3-3). The page at the address P (8) is replaced out to an arbitrary free area on the flash memory 30 when the page is to be replaced out (3-4).

(C) Reading [direct access area] (4 in FIG. 4): By placing information in the direct access area, high-speed reading can be performed without performing address conversion. As a result, not only can the area be used as a boot area, but also the overhead of managing the address translation table can be reduced.

(D) Write [direct access area]: No address conversion is performed, but updating takes a long time.

FIG. 5 shows two-level address conversion in the information processing apparatus of FIG. As shown in FIG.
The RAM 20 is allocated on a physical address space, and the physical address of the flash memory 30 (one-dimensional address space different from the physical address space where the DRAM 20 exists) is overlaid on a space called a real address. Address conversion is performed in two stages, that is, conversion from a logical address to a real address and conversion from a real address to a physical address.
Whether or not to perform the address conversion at the stage depends on the type of access. Next, an access procedure will be described.

(A) Read [address conversion area] (1 in FIG. 5): Information is read directly from the flash memory 30 using the real address converted by the logical-to-real address conversion table as a physical address indicating the flash memory 30.

(B) Write [address conversion area] (2-1 to 2-4 in FIG. 5): At the time of write (2-1),
In the second-stage real-physical address conversion mechanism, a page including information to be written is copied to an area P (0) on the DRAM 20 designated by a physical address, and then the conversion destination of the real address R (2) is set to P Set to (0) (2-
2) The information is updated on the DRAM 20 (2-3).
When P (0) on the DRAM 20 is to be replaced and replaced on the flash memory 30, the pointer from the real address to the physical address is interrupted (2-4).

(C) Direct access area (3 in FIG. 5): The same as in the case of the one-level address conversion in FIG.

It can be considered that the two-level address conversion is obtained by extracting the management of the address conversion table at the time of writing in the one-level address conversion as the second-stage address conversion. When the second-stage address conversion is performed independently of the first-stage address conversion, the first-stage address conversion mechanism only needs to be aware of the physical address space where the flash memory 30 exists, and is aware of the presence of the DRAM 20. No need to do. Also, by separating the second-stage address conversion from the first-stage address conversion, it becomes easy to carry the flash memory 30 as a removable medium.

However, in the two-level address conversion, no relocation occurs in the real address space, and access to a specific page in the flash memory 30 is determined. This is because if the address translation mechanism in the second stage replaces a page in the DRAM 20 with the flash memory 30 and selects a location different from the real address from which the page was replaced, the first stage Must also be updated. As a method for avoiding this, the occurrence of a page fault (replace-in process from the flash memory 30 to the DRAM 20) caused in the second-stage address translation mechanism by writing is transmitted to the first-stage address translation mechanism. The first address translation mechanism may reserve an area for replacing out the page that has just been replaced in, and transmit that area to the first-stage address translation mechanism.

As described above, according to the configuration of FIG. 1, the occurrence of page-in from the flash memory 30 to the DRAM 20 itself is reduced, so that the traffic on the system bus 12 is reduced, and the performance of the information processing apparatus is reduced. improves. Also, the number of times of writing to the same page of the flash memory 30 is reduced, and the life of the flash memory 30 is extended. By distributing the relocation destinations using an operating system or the like, the life of the flash memory 30 can be extended.

Further, since information such as a stack in which an application is operating is also stored in the flash memory 30 by replacement out of the DRAM 20, the transition to the hibernation state of the information device and the return from the state can be performed at high speed. Can be done. Also, by removing the flash memory 30 and connecting it to another information device,
In the same environment, high portability of information can be realized, for example, processing can be immediately resumed before stopping.

[0028]

As described above, according to the present invention, a page fault occurs when a line in the cache memory becomes dirty even though there is no page in the random access memory, and the page becomes dirty. Page-in from the flash memory to the random access memory, so that only the pages that are actually updated are paged in, thereby reducing the time during which the processor processing is interrupted due to the processing of the page fault. This improves the performance of the information processing device.

Also, in the present invention, a page fault occurs only with respect to an actually updated page.
By comparing the conventional information processing apparatus disclosed in Japanese Patent No. 14499 with the information processing apparatus of the present invention, if the same number of page faults can be caused, the capacity of the random access memory used in the information processing apparatus of the present invention is The capacity becomes smaller than the capacity of the random access memory used in the information processing device, so that cost reduction and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to the present invention.

FIG. 2 is a conceptual diagram showing details of a memory architecture in the information processing apparatus of FIG. 1;

FIG. 3 illustrates various states in the memory architecture of FIG. 2;

FIG. 4 is a conceptual diagram illustrating one-level address conversion in the information processing apparatus of FIG. 1;

FIG. 5 is a conceptual diagram for explaining two-level address conversion in the information processing apparatus of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Processor 11 Cache memory 12 System bus 20 DRAM 30 Flash memory 41 Logical address 42 Physical address 43 Address conversion table 44, 45 Comparator

Claims (3)

[Claims] 1. An information processing apparatus comprising a cache memory, a random access memory, and a flash memory each connected to a system bus, wherein the random access memory has no page and the cache memory has no page. An information processing apparatus wherein a page fault is caused when the line becomes dirty, and the dirty page is page-in from the flash memory to the random access memory. 2. The information processing apparatus according to claim 1, wherein the flash memory is allocated on the same address space as the random access memory so as not to overlap. 3. The information processing apparatus according to claim 1, wherein the flash memory is allocated in a different address space from the random access memory.