JP2000115768A - Connection controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the flexibility by connecting compression coding conversion units and line interface units for plural image communication systems with different compression coding rules to a single bus so as to avoid a fixed connection relation between the line interface and a transcoder. SOLUTION: A packet generating section 51 of data transmitter side transmission units 40, 42 generates a packet based on its own unit channel ID set in advance to a transmission channel ID setting section 50 and transmits the packet to a high speed serial bus 31. A reception section 53 of data receiver side reception units 44, 46 receives the packet and a channel ID check section 55 compares the channel ID of the received packet with its own unit reception channel ID set in advance of a reception channel ID setting section 54 and when they are coincident, the packet is outputted to an internal circuit 56 of its own unit. Since the internal circuit of its own unit receives the packet when the channel ID of the received packet is coincident with the channel ID of its own unit, various communication can be realized and an exclusive control unit for the purpose is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection control device, and more particularly to a connection control device for controlling connection between media having different specifications, networks having different specifications, or a plurality of compression coding rules having different specifications. About.
In recent years, with the generalization of compression encoding and the innovation of high-density LSI technology, many low-cost image / audio transmission devices have been provided. As for the image / sound compression / encoding technology, advanced algorithms have been put to practical use aiming at high quality and low cost, and high quality services have been provided. However, as new algorithms and high-speed networks are provided year by year, mutual communication compatibility between the image and voice communication devices is lost, and connection control for bridging communication between different media is demanded.

[0002]

2. Description of the Related Art As a connection control device for connecting communications between different media, an image gateway device having the function shown in FIG. 1 can be considered. In FIG. 1, an image gateway device 10 includes a plurality of MPEG2 (moving pics).
cure expert group-2) terminal 12A
To 12D, a plurality of TV conference terminals 14A to 14D are connected, and
AN 18 is connected.

In this image gateway device 10, the MP
The compression coding rule of the EG2 terminal and, for example, H.264 of the TV conference terminal. 320 (video telephone for ISDN recommended by ITU-T /
Conversion with compression coding rules of the conference terminal rules), MPEG
Two-terminal digital hierarchy G. 703 and ISDN user / network interface of TV conference terminal 431
A 1: 1 or 1: N transcoding function, etc. is required.

FIG. 2 is a block diagram showing an example of the image gateway device 10 which is considered to have such a function. In FIG. 2, a line I / F (interface) 20
A to 20D are connected to the G.2 terminals 12A to 12D. This is an interface of 703 lines, and is connected to the random switch 21. Also, line I / F22A
To 22D are connected to the TV conference terminals 14A to 14D. It is an interface of 431 lines, and is connected to the random switch 23.

[0005] Between the random switches 21 and 23 having functions such as switching, switching, and multicasting, an MP is provided.
EG2 and H.I. Transcoder 24 that performs conversion with 320
A to 24D, and from the general controller 25 to an external image gateway device 28 via an inter-device I / F 26, and a LAN server I / F 27
Is connected to the LAN server 29 via the.

[0006]

In the configuration shown in FIG. 2, the random switches 21 and 23 having functions such as switching, switching, and multicasting, and the line I / Fs 20A to 20 are provided.
D, 22A to 22D and transcoders 24A to 24D
The connection relationship between them is fixed and there is no flexibility. Also,
The number of mounted channels is limited by the configuration of the random switches 21 and 23, and there is no flexibility for expansion beyond the number of mounted channels assumed at the time of design. Furthermore, line I / F20A ~
20D, 22A to 22D and random switches 21, 23
Interface is fixed depending on the line type, and there is a problem that flexibility for expanding the line type is low.

The present invention has been made in view of the above points, and has a high flexibility without a fixed connection relationship between a line interface and a transcoder, and a large flexibility in extending the number of mounted channels and a line type. It is an object to provide a control device.

[0008]

According to a first aspect of the present invention, there is provided a connection control apparatus for controlling connection between a plurality of image communications having different compression coding rules, wherein a line interface of each of the plurality of image communications is provided. The unit and the compression encoding conversion unit are connected to a single bus.

As described above, since the line interface unit and the compression / encoding conversion unit of each of the plurality of image communications are connected to a single bus, the connection relationship between the line interface and the transcoder is not fixed. Flexibility is increased, and circuit switching and broadcast distribution functions are diversified. The invention according to claim 2 is the connection control device according to claim 1, wherein a high-speed serial bus is used as the bus.

As described above, since the high-speed serial bus is used, the line interface unit and the compression / encoding / conversion unit can be easily connected. Claim 3
The connection control device according to claim 1 or 2, wherein the line interface unit and the compression encoding conversion unit add an identification code for specifying a transmission source unit to the data and transmit the data to the bus. Each of the units determines from the identification code added to the data transmitted through the bus whether or not the data is received by itself.

As described above, each unit determines whether or not the data is received by itself from the identification code added to the data transmitted through the bus, so that the connection relationship between the line interface and the transcoder is fixed. However, flexibility is increased, and 1: 1 and 1: N transcoding and broadcasting can be performed with simple control. According to a fourth aspect of the present invention, in the connection control device according to the first aspect, the units are chain-connected by the single bus, and a priority is given in the order of the chain connection.

As described above, the units are chain-connected by a single bus, and the priority is given in the order of the chain connection. Therefore, the priority can be given to each unit with a simple configuration. According to a fifth aspect of the present invention, in the connection control device according to the fourth aspect, each of the units sends data to a single bus according to the priority order.

As described above, since each unit sends data to a single bus in accordance with its priority, bus contention and congestion control can be performed. According to a sixth aspect of the present invention, in the connection control device according to the fifth aspect, a data transfer period in which data is transferred using the bus, and which of the units transfers data using the bus is determined. A determined congestion control period is provided.

As described above, since the data transfer period for transferring data using the bus and the congestion control period for determining which of the units transfers data using the bus are provided, It is possible to determine which unit will send data to the bus. According to a seventh aspect of the present invention, in the connection control device according to the sixth aspect, the congestion control is performed by notifying an operation mode between units having higher and lower priorities adjacent to the own unit.

As described above, the congestion control is performed by notifying the operation mode between units having higher and lower priorities adjacent to the own unit, so that it is not necessary to provide a dedicated control unit for performing the congestion control. . The invention according to claim 8 is
5. The connection control device according to claim 4, further comprising a branch path branched from a unit chain-connected by said single bus and connecting another unit.

As described above, since there is a branch path branching from a unit connected in a chain by a single bus and connecting another unit, a port having a large data transfer amount can be preferentially selected. If the chain is not broken, the unit can be actively loaded. According to a ninth aspect of the present invention, in the connection control device according to the seventh aspect, when an abnormality occurs in any of the plurality of units chain-connected by the single bus, the unit is adjacent to the unit in which the abnormality has occurred. Under the control of the unit, the unit in which the abnormality has occurred is disconnected from the single bus.

As described above, the unit adjacent to the unit in which the abnormality has occurred is separated from the single bus by controlling the unit adjacent to the unit in which the abnormality has occurred. Can be prevented and normal operation can be performed only with a normal unit. According to a tenth aspect of the present invention, in the connection control device according to the sixth aspect, each of the plurality of units chain-connected by the single bus has an abnormality in its own unit when the congestion control is not detected within a predetermined period. Is disconnected from the single bus.

As described above, when congestion control is not detected within a predetermined period, it is determined that an abnormality has occurred in the own unit, and the own unit is separated from the single bus, so that the entire apparatus becomes abnormal due to an abnormality in one unit. Can be prevented,
Only a normal unit can operate normally. According to an eleventh aspect of the present invention, in the connection control device according to the first aspect, a plurality of cooling fans for cooling the device are provided, and a fan pulse for driving a fan motor of each of the plurality of cooling fans is stopped for a predetermined period or more. Alarm generating means for generating an alarm when the alarm is issued, and alarm recording means for recording which of the plurality of cooling fans generated the alarm.

As described above, an alarm is generated when the fan pulse for driving the fan motor of each of the plurality of cooling fans is stopped for a predetermined period or more, and it is recorded which of the plurality of cooling fans generated the alarm. The failure of the fan can be accurately detected and its record can be recorded. According to a twelfth aspect of the present invention, in the connection control device according to the first aspect, the compression-encoding conversion unit includes:
An audio encoding / decoding circuit for encoding / decoding PCM audio data into audio data at a first transmission rate; audio data at the first transmission rate; and audio data at a second transmission rate different from this. And a compression coding conversion and multiplexing / demultiplexing circuit that performs compression coding conversion of image data and multiplexing / demultiplexing of the audio data of the second transmission rate.

As described above, since the audio speed conversion circuit for converting the audio data at the first transmission rate and the audio data at the second transmission rate is provided, the existing audio encoding / decoding circuit and compression circuit are used. Encoding conversion and multiplexing / demultiplexing circuits can be used. According to a thirteenth aspect of the present invention, in the connection control device according to the first aspect, the compression / encoding / conversion unit is a C / C converter.
It has a PU and a programmable gate array, and performs initialization of the CPU and the programmable gate array in parallel when power is turned on.

As described above, since the initialization of the CPU and the programmable gate array is performed in parallel when the power is turned on, the time required for the initialization can be reduced. According to a fourteenth aspect of the present invention, in the connection control device according to the first aspect, the line interface unit has a FIFO using a DRAM, and receives data using a clock faster than a clock of the received data. The data is written into the FIFO and read using the high-speed clock, and the data read from the FIFO is latched by the clock of the received data and output.

As described above, the received data is written into the FIFO by using a clock faster than the clock of the received data, and is read by using the faster clock.
Since the data read from O is latched and output by the clock of the received data, the received data can be reliably read from the FIFO even when the clock of the received data is slow.

[0023]

FIG. 3 is a block diagram showing an embodiment of a connection control device according to the present invention. In the figure, line I / F 30A
30D are connected to the MPEG2 terminals 12A to 12D shown in FIG. It is an interface of 703 lines and is connected to, for example, a high-speed serial bus 31 having a transmission speed of 200 Mbps. The line I / Fs 32A to 32D are connected to the TV conference terminals 14A to 14D shown in FIG.
It is an interface of 431 lines, and is connected to the high-speed serial bus 31.

The high-speed serial bus 31 has M
PEG2 and H. Transcoder 3 that performs conversion with 320
Transcoder sections 35A to 35 constituting 4A to 34D
D and 36A to 36D are connected to each other. The transcoder units 35A to 35D convert MPEG2 images into digital video compression and encoding rules according to the R.R. 601 (CCI
The image is converted into an image of R recommendation 601 (4: 2: 2 component signal). The transcoder units 36A to 36D are R. 6
01 to H.01. Convert to 320 images. Further, the high-speed serial bus 31 has an external image gateway device 3 connected thereto.
8 and LAN server 39 are connected.

The line I / F 30A shown in FIG.
30D and transcoder units 35A-35D are MPE
It can be regarded as a G2 decoder / encoder, and includes transcoder units 36A to 36D and line I / Fs 32A to 32D.
Is H. 320 decoder / encoder. FIG. 4 is a block diagram of a first embodiment of a connection portion of each component unit of the connection control device with the high-speed serial bus 31. In the figure, transmission units 40 and 42 (30A to 30A) which are units on the data transmission side with respect to the high-speed serial bus.
D, 32A-32D, 35A-35D, 36A-36D
), Each transmission channel ID setting unit 50
The packet generation unit 51 generates a packet using the channel ID of its own unit which is set in advance and sends the packet to the high-speed serial bus 31. This packet includes, as shown in FIG. 5, the channel ID (chID) of the transmission source unit,
It comprises a data length, additional information, data, and check data (CRC) for these. That is, the destination is not specified for the packet.

The receiving units 44 and 46 (30A to 30A) which are units on the data receiving side with respect to the high-speed serial bus.
D, 32A-32D, 35A-35D, 36A-36D
), The receiving unit 53 receives all the packets transmitted through the high-speed serial bus 31, and sets the channel ID of the received packet to the channel ID to be received by the own unit which is set in the receiving channel ID setting unit 54 in advance. Are compared with each other by the channel ID check unit 55, and when they match, the signal is supplied to the internal circuit 56 of the own unit.

Here, when performing the 1: 1 transcoding, as shown in FIG.
Packets from each of the 12Ds (# 1 to # 4) are connected to the
/ F 30A to 30D to the high-speed serial bus 31 in time series, and transcoders 34A to 34D (# 1 to #D).
4) Received by each, transmitted again to the high-speed serial bus 31, received by each of the line I / Fs 32A to 32D, and received by the TV conference terminals 14A to 14D (H.431 # 1 to #.
4) is supplied 1: 1.

When 1: N transcoding is performed, as shown in FIG.
Packets from each of the 2Ds (# 1 to # 4) are
F30A to 30D are transmitted in a time series to the high-speed serial bus 31. Of these, packets transmitted by the line I / F 30A are received by the transcoder 34A and transmitted again to the high-speed serial bus 31, and are transmitted by the line I / Fs 32A to 32D respectively. Received, and the TV conference terminals 14A to 14D (H.4
31 # 1 to # 4) at 1: N.

MPEG2 multicast transmission 1:
N, the MPEG2 terminal 1 as shown in FIG.
2A (# 1) is transmitted in a time series from the line I / F 30A to the high-speed serial bus 31, and is transmitted to the line I / F 3A.
0B to 30D and received by the MPEG2 terminal 12
B to 12D (# 2 to # 4). When performing another mode of the MPEG2 multicast transmission 1: N, as shown in FIG.
Packets from A and 12B (# 1 to # 2) are sent to the line I / F
30A and 30B send out to the high-speed serial bus 31 in chronological order. Among them, packets from the line I / F 30A are received by the line I / Fs 30C and 30D, respectively.
It is supplied to each of the two terminals 12C and 12D (# 3, # 4).

When performing simultaneous 1: 1 transcoding multiple channel operation and LAN distribution, as shown in FIG. 10, MPEG2 terminals 12A to 12D (# 1 to # 2)
4) Packets from each are line I / Fs 30A-30
D is transmitted to the high-speed serial bus 31 in time series, received by the transcoders 34A to 34D (# 1 to # 4) and transmitted again to the high-speed serial bus 31,
/ F32A-32D, and received at TV conference terminal 14A-
14D (H.431 # 1 to # 4) at a ratio of 1: 1 and received by the LAN server 39 from the high-speed serial bus 31. In the LAN server 39, the high-speed serial bus 3
Buffering the received data stream from No. 1 to select necessary data, detecting the congestion state of the LAN, and transmitting the data to the LAN.

When performing high-speed LAN distribution, as shown in FIG. 11, MPEG2 terminals 12A to 12D (# 1
~ # 4) Packet from each is line I / F 30A ~
30D is transmitted in time series to the high-speed serial bus 31,
The data is received by the LAN server 39 from the high-speed serial bus 31. The LAN server 39 buffers the received data stream from the high-speed serial bus 31, selects necessary data, detects the congestion state of the LAN, and sends the data to the LAN.

As described above, the receiving unit receives all the packets transmitted on the high-speed serial bus 31 of the common bus format, and the channel ID of the received packet (the channel ID of the transmission source unit) is the channel to be received by the own unit. When the ID coincides with the ID, switching is performed by capturing the ID in the own unit, and various kinds of communication such as 1: 1 or 1: N transcoding and multicast transmission can be realized. Therefore, a dedicated control unit is not required.

When the high-speed serial bus 31 of the common bus format is used, since all the constituent units have the same priority, control when data transfer competes and congestion control are important. Next, the contention control and the congestion control will be described. FIG. 12 is a block diagram of a second embodiment of a connection portion of each connection unit of the connection control device with the high-speed serial bus 31. In FIG.
46 (30A-30D, 32A-32D, 35A-35
D, 36A to 36D), two or more serial bus connection ports are provided, and the high-speed serial bus 31 is connected in a chain. Then, all the constituent units 40 to 46
One of the constituent units 40 is determined as the master unit having the highest priority, and the closer to the master unit in the chain connection, that is, the constituent units 42, 4
The higher priority is given in the order of 4,46. Further, FIG.
As shown in (1), a data transfer cycle T1 to be sent to the high-speed serial bus 31 of all the constituent units 40 to 46 is determined, and within this data transfer cycle T1, the operation mode desired by each constituent unit in the next data transfer cycle ( (Transmission mode / reception mode) is declared to the adjacent constituent units, and a control period T2 for performing congestion control is set.

In this control period T2, each component unit determines the operation mode of its own unit by looking at the operation mode of the component unit having a higher priority than its own unit. As shown in FIGS. 12 and 14, if the operation mode desired by the constituent unit 42 is the transmission mode, it is checked in step 1 whether or not there is a constituent unit having a higher priority than the own unit in the transmission mode. When there is no such unit, the own unit determines that transmission is possible, determines the operation mode in step 2, and notifies this to the constituent unit 40 having a higher priority. In step 3, if permission for the operation mode (transmission mode) is given from the constituent unit 40 having the higher priority, the operation mode of the own unit is determined. Then, in step 4, the operation mode (transmission mode) of the own unit is notified to the constituent unit 44 having a lower priority. This constituent unit 42
The operation mode (transmission mode) is notified from the configuration unit 44 to the configuration unit 46 as shown in FIG. 14, whereby the request for the transmission mode of the configuration unit 46 is rejected, and the operation mode of each configuration unit is determined. And
In the next data transfer phase, the configuration unit 42 sends out the packet to the high-speed serial bus 31.

In the above embodiment, by performing the congestion control, it is possible to know where the chain was broken when an operation failure occurred at a certain port in the middle of the chain connection. However, when the above-described chain connection is performed, when an operation failure occurs at a certain port in the middle of the chain connection, the entire system becomes abnormal. Further, in order to perform congestion control of the order of priority of the chain connection, there is a possibility of data failure due to waiting for data transmission in a constituent unit of a lower priority. Also, if the component unit is actively loaded for periodic inspection, the chain will break,
As in the case of the above-described port abnormality, there is a problem that the entire system becomes abnormal. An embodiment for solving this is shown in FIG.
It is shown in FIG.

FIG. 15 is a block diagram showing a third embodiment of the connection of each component unit of the connection control device with the high-speed serial bus 31. In the figure, three ports for connecting to the high-speed serial bus 31 are provided in each component unit, and the higher the priority, the higher the priority. Then, the first priority port of the component unit 42 is connected to the second (or third) priority port of the higher-level component unit 40 via the high-speed serial bus 31, and the same connection is performed.
The constituent units 40, 42, 44, and 46 constitute a path serving as a backbone. The remaining third (or second) priority ports of the constituent units 40, 42, 44, and 46 are connected to the constituent units 60, 60 by the high-speed serial bus 61.
62, 64, and 66 are connected to each other to form a branch path. The constituent units constituting the main path are arranged with a large data transfer amount, and the constituent units constituting the branch path are arranged with a small data transfer amount. In this case, the priority of each port is indicated by a number in parentheses in the figure.

As a result, even when a certain congestion control process is performed, a port having a large data transfer amount is automatically selected with a higher priority, and the constituent units are activated if the chain is not interrupted by the main path. Inspection after loading and replacement of constituent units are possible. Each of the above-described main path and branch path may be configured to form a loop.

FIG. 16 shows each of the line I / Fs 30A to 30D and 32A to 32D, and the transcoders 35A to 35D and 36A to 36D, which are the constituent units shown in FIG.
An embodiment of a chain connection when the above three ports are provided is shown. In this embodiment, the line I / F 30B
The first port is connected to the priority of the higher-level line I / F 30A or the third port, and a trunk path is similarly configured by the line I / Fs 30A to 30D.
F30A to 30D each priority second port is assigned to each of the transcoder units 35A to 35D priority 1
Connected to the third port, and transcoders 34A-34D
Is a branch path. This branch path is a block for performing transcoding (for example, line I / F3).
0A, transcoder units 35A, 36A and line I / F3
2A) as a lump. Line I / F3 above
0A to 30D, 32A to 32D, transcoder unit 35
Each of A to 35D and 36A to 36D is configured as one board, and the connection control device 10 is configured by piercing and connecting each board to a slot.

FIG. 17 is a block diagram of a fourth embodiment of the connection section of each component unit of the connection control device with the high-speed serial bus 31. In the figure, each constituent unit 40, 42, 44
Each is provided with a pass-through control pattern detection unit 70 that can be controlled from an adjacent constituent unit. The pass-through switches 71, 72, and 73 are provided for each port, and usually connect the port to an internal circuit as shown by a solid line. When a control signal is supplied from an adjacent component unit, the pass-through control pattern detection unit 70
1, 72 and 73 are switched so that all ports are short-circuited as shown by the broken lines. The serial bus control unit 74
Sends a control signal from an own constituent unit to an adjacent constituent unit when the adjacent constituent unit fails. At this time, the pass-through control pattern detection unit 7 of the self-constituting unit
0 indicates an inhibit so as not to operate.

Thus, when each component unit fails, a control signal can be sent from an adjacent component unit to automatically disconnect the failed component unit from the high-speed serial bus 31, and some abnormalities can be spread throughout the system. Can be prevented and the remaining normal part can be utilized to the full. FIG. 18 is a block diagram of a fifth embodiment of the connection section of each component unit of the connection control device with the high-speed serial bus 31. In the figure, pass-through switches 71, 72, 73, a congestion control detector 75, a timer controller 76, a serial port controller 77, and a reset pattern generator 78 are provided in each of the constituent units 40, 42, and 44, respectively. I have. When receiving the congestion control for notifying the operation mode from the adjacent constituent unit within the data transfer cycle T1 shown in FIG. 13, the congestion control detection unit 75 supplies the detection signal to the timer control unit 76. If the detection signal is not supplied even when the data transfer period T1 is exceeded, the timer control unit 76 considers that the port of the own unit has a failure, and supplies a reset signal to the serial port control unit 77 and the reset pattern generation unit 78. .

The serial port control unit 77 resets by the reset signal to perform self-recovery, and switches the pass-through switches 71, 72, 73 so that all ports are short-circuited as shown by broken lines. The reset pattern generation unit 78 generates a predetermined reset pattern according to the reset signal and sends the generated reset pattern to an adjacent constituent unit. Thus, the reset of the serial port control unit 77 can be known in the adjacent constituent units.

By the way, in the embodiment of FIG.
The first port of the priority order of the F30B is set to the higher-level circuit I / F.
Connect to the priority or third port of 30A, and similarly configure a trunk path with the line I / Fs 30A to 30D,
Four branch paths for transcoding (for example, line I / F 30A and transcoder units 35A and 36A)
And a line I / F 32A), and MPEG2 input 4 channels × H. 320 output 4 channel connection control device 10
However, as shown in FIG. 19, the line I / F3
0A, transcoder units 35A, 36A and line I / F3
2A only, MPEG2 input 4 channels × H. 32
It is also possible to configure the connection control device 10 having 0 outputs and 4 channels.

Further, as shown in FIG.
0A, Transcoder 35A, 36A, Line I / F3
2A, line I / F 30B, transcoder 35B,
MPEG2 input 2 channels × H.36B and line I / F 32B. 1 and 2 channels of 320 outputs.
The line I / Fs 37A and 37B may be arranged at the positions where the 6 transcoder units 35C and 35D are arranged. Here, the line I / Fs 30C, 37A, 32C and the line I / F 30D,
37B and 32D constitute an MPEG2 branch path for input and output, respectively.

The connection control device 10 shown in FIGS. 3, 16 and the like has a plurality of cooling fans. If this cooling fan breaks down, each part of the circuit of the connection control device 10 will cause a thermal runaway, so that the power supply of the connection control device 10 needs to be cut off. Conventionally, the power supply was cut off when the frequency of the fan pulse supplied to the cooling fan motor was reduced to half of the normal frequency. In this case, the frequency of the fan pulse was changed even if the fan pulse was momentarily interrupted. This is half the normal value, and the power is shut off due to a malfunction. The next embodiment solves this problem.

FIG. 21 is a circuit diagram of a first embodiment of the fan alarm detection circuit. In the figure, a terminal 100 receives a fan pulse having a frequency of, for example, 100 Hz supplied to a motor of a cooling fan and is supplied to a retrigable monostable multivibrator (hereinafter referred to as a retrigable monomulti) 104 through a buffer 102. . The retriggerable monomulti 104 is set to a time constant of approximately 18 msec by the resistor R1 and the capacitor C1, and when an instantaneous interruption occurs in which even one fan pulse with a frequency of 100 Hz shown in the upper part of FIG. And supplies it to the D-type flip-flop 106 and the latch circuit 108. The flip-flop 106 latches this signal at the rising edge of the fan pulse, and
10 and the AND circuit 110 supplies the flip-flop 1
06 output is passed when the fan pulse is at a high level, and supplied to the retriggerable mono-multi 112. The latch circuit 108 latches the low-level signal and outputs it from the terminal 116 to a subsequent register as an instantaneous interruption detection signal.

The retrigable mono-multi 112 has a resistance R
2 and the capacitor C2, the time constant is set to approximately 1 sec. When the lack of the fan pulse continues for 1 sec, a low-level signal is generated and supplied to the latch circuit 114. The latch circuit 114 latches the low-level signal and outputs the signal from the terminal 116 to a subsequent register as a disconnection duration detection signal. Latch circuits 108 and 114 are connected to terminal 119
When the clear signal is supplied from, the contents of the latch are cleared.

As described above, since not only the instantaneous interruption of the fan pulse but also the duration of the fan pulse for 1 second or longer is detected, it is possible to prevent the power from being shut down due to a malfunction due to the instantaneous interruption of the fan pulse. FIG. 22 is a circuit diagram of a second embodiment of the fan alarm detection circuit. In the figure, the same parts as those in FIG. 21 are denoted by the same reference numerals. In FIG.
A terminal 100 receives a fan pulse having a frequency of, for example, 100 Hz supplied from the power control pulse generator 128 to the motor of the cooling fan, and is supplied to the retrigable monomulti 104 through the buffer 102.

The retriggerable monomulti 104 has a resistor R
1 and the capacitor C1 are set to a time constant of approximately 18 msec. When an instantaneous interruption occurs in which even one fan pulse with a frequency of 100 Hz is lost, a low-level signal is generated to generate a D-type flip-flop 106 and a latch circuit. 108. The flip-flop 106 latches this signal at the rise of the fan pulse and supplies it to the AND circuit 110. The AND circuit 110 passes the output of the flip-flop 106 when the fan pulse is at the high level and supplies it to the retrigable mono-multi 112. The latch circuit 108 latches the low-level signal and outputs it from the terminal 116 to a subsequent register as an instantaneous interruption detection signal.

The retriggerable mono-multi 112 has a resistance R
2 and the capacitor C2, the time constant is set to approximately 1 sec. When the lack of the fan pulse continues for 1 sec, a low-level signal is generated and supplied to the latch circuit 114. The latch circuit 114 latches the low-level signal and outputs the signal from the terminal 116 to a subsequent register as a disconnection duration detection signal. Latch circuits 108 and 114 are connected to terminal 119
When the clear signal is supplied from, the contents of the latch are cleared.

When the latch circuit 114 outputs a low-level disconnection duration detection signal, the switch 120 is turned on, a current flows from the power supply 122 to the fuse 124, and the fuse 124 is thermally blown. Power supply monitoring unit 126
Prohibits the power supply control pulse generator 128 from generating a fan pulse upon detecting the blow of the fuse 124.
The terminals 100 to the fuses 124 are provided for the respective fan motors of the plurality of cooling fans. When a failure occurs in any one of the cooling fan motors, the fuse 124 corresponding to the fan motor is blown. Therefore, it is possible to recognize which fan motor has failed at the time of restoration without performing a separate test.

Next, the internal circuits of the transcoder units 34A to 34D will be described. In FIG. 23, MMC
The (multi-mode codec) 130 is an existing circuit having a function of encoding / decoding PCM audio data having a transmission rate of 32 Kbps into audio data having a transmission rate of 64 Kbps in the audio section. The VCP (Video Codec Processor) 132 is a R.V. The image data of H.601 is converted to H.264 image data using the frame buffer 133. H.320, which encodes / decodes image data and multiplexes / demultiplexes image data and audio data. 22
This is an existing circuit having one framing function. Where V
Transmission speed of audio data input / output to / from CP 132 is 1.5
36 Kbps.

The above-mentioned existing circuits, MMC 130 and VC
A PLD (programmable logic device) 134 having FIFOs (first-in first-out) 135 and 136 is provided between
The speed conversion between the audio data of Kbps and the audio data of 1.536 Kbps and the timing generation are performed. The PLD 134 has a frequency of 64 KH shown in FIG.
z, a line clock LCLK, a universal pulse LXSYNC having a frequency of 8 kHz (8 bits of data are present in one cycle of this pulse) shown in FIG. 7B, and a transmission frame pulse SFS having a period of 10 msec shown in FIG. The audio data LDIN shown in FIG.
35 and 136, and transmit them to the MMC 130.

Further, a period of 10 msec shown in FIG.
Is supplied to the MMC 130, and the audio data LDOUT shown in FIG.
It is received from C130 and stored in FIFOs 135 and 136. 25A to 25D show the transmission frame pulse SFS, the reception frame pulse RFS, the universal pulse LXSYNC, the audio data LDIN or LDOU.
I change the time axis of each T.

The VCP 132 supplies an AUX pulse of VCP software control having a period of 8.5 msec to 11.5 msec shown in FIG. 26 (A) to the PLD 134. 5M
In synchronization with the reception frame pulse ARFS for 40 pulses at Hz, the audio data shown in FIG. 3C is supplied and received. After receiving the audio data shown in FIG. 10C, the VCP 132 synchronizes with the PLD 134 at a frequency of 1.5 MHz shown in FIG. Is transmitted.

As described above, by performing the speed conversion of the audio data by the VCP 132, the existing circuit MMC1
30 and the VCP 132 can be used. VCP
132 is an image section (camera and monitor). The image data of H.601 is converted to H.264 image data using the frame buffer 133. 32
0 is encoded / decoded to the image data of R.0. The image data of 601 is 30 frames / sec, and this image data is entirely written in the frame buffer 133. H. The image data of H.320 is 30 frames / sec or less, for example, 10 frames / sec. On the 320 side, image data is read from the frame buffer 133 as necessary, and
The image data is converted into image data 320 and output. At this time, the image data not read from the frame buffer 133 is lost, but there is no problem.

Next, the line I / F of the board configuration shown in FIG.
30A-30D, 32A-32D, transcoder unit 3
Initialization of each of 5A to 35D and 36A to 36D will be described. Each of the above boards is often configured with a CPU and an FPGA (Flexible Programmable Gate Array). In this case, the circuit configuration shown in FIG. 27 was conventionally used. Here, when the power supply monitoring unit 140 detects that the power is turned on, the power supply monitoring unit 140 instructs the FPGAs 142 and 144 to initialize.
After these initializations are completed, the FPGAs 142, 14
4. The CPU 150 is reset and activated. In such a configuration, the time required for initializing the FPGAs 142 and 144 and the time for resetting the CPU 150 are required, so that the startup time is long. The circuit configuration shown in FIG. 28 attempts to solve this problem.

In FIG. 28, when detecting that the power is turned on, the power supply monitoring unit 140 instructs the FPGAs 142 and 144 to perform initialization and also instructs the CPU 150 to reset.
As a result, each of the FPGAs 142 and 144 has the RO
The circuit configuration data is read from M143 and 145, and initialization (circuit configuration) is performed. When these initializations are completed, D
The ONE signal is output, and the reset of the FPGAs 142 and 144 is started via the AND circuit 146 and the delay circuit 147.

Then, the CPU 150 checks a predetermined register of the FPGA 142 via the bus 152, and
When the resetting of 42 is completed, the next operation is started. It is assumed that the reset completion of the FPGA 142 is later than that of the FPGA 144. Thus, the FPGA 142, 14
4 and the reset of the CPU 150 are performed in parallel, so that the startup time can be reduced. It should be noted that FIGS.
(D) shows the timing at the time of startup by the conventional circuit configuration of FIG. 27, and FIGS. 29 (E) to (H) show the timing at the time of startup by the circuit configuration of the present embodiment of FIG.

Next, control of the FIFO used in the line I / Fs 32A to 32D will be described. Some FIFOs for storing a large amount of data use a DRAM internally. Due to the characteristics of such a FIFO, when writing and reading certain data, the interval between the write address and the read address is set to a predetermined number of bits (for example, 200 bits).
Bit) required. In this case, if the interval between the write address and the read address is 200 bits or less, the write data cannot be accurately read.

ISD at line I / Fs 32A to 32D
N.I. When detecting a multi-frame (a configuration in which a 1-bit frame pulse is followed by 24 8-bit time slots per time slot) from the received data in the 431 interface, the frame pulse has a frequency of 8
KHz, line clock LINECLK is 1.544M
Assuming a burst clock of Hz, there is only 193 bits of data between frame pulses. For this reason, FIG.
When data is written to the FIFO 160 using a line clock LINECLK having a frequency of 1.544 MHz as shown in FIG. 0, the data written to the FIFO 160 between the frame pulses cannot be read accurately. That is, the multi-frame cannot be detected accurately. The embodiment shown in FIG. 31 solves this problem.

In FIG. 31, a differentiating circuit 162 differentiates a frame pulse having a frequency of 8 KHz, generates a differential pulse having a clock width of 12 MHz at the rising edge of the frame pulse, and supplies it to the FIFO 160 as a reset signal. After resetting the write / read address by this reset signal, the FIFO 160
Hz, the write / read address is counted up, and input data DATA (received data of ISDN I.431 interface) is written.
Read stored data in the order of input. In this case, the input data DATA having the same value is written a plurality of times. The input data DATA is input to the data input terminal DI1 of the FIFO 160.
, And the output data of the data output terminal DO1 is looped and supplied to the data input terminal DI0. Thereafter, the stored data is shifted in the same manner as in the frame pulse cycle.

Using the above clock having a frequency of 12 MHz, 1500 bits can be written into the FIFO 160 between frame pulses having a frequency of 8 KHz.
Data can be read from the FIFO 160 at a frame pulse period of KHz. The 4-bit output data of the data output terminals DO1 to DO4 of the FIFO 160 is latched by the flip-flop 166 at the rising edge of the inverted line clock obtained by inverting the line clock LINECLK having the frequency of 1.544 MHz by the inverter 164.
This is because the data is not stable when the line clock LINECLK rises, and is stable when the line clock LINECLK falls.

The output data of the flip-flop 166 is
The signal is latched by the flip-flop 168 at the rise of the line clock LINECLK, and the line clock L
The signal is supplied to the pattern detector 170 in synchronization with INECLK. The pattern detector 170 performs multi-frame detection by comparing the output data of the flip-flop 168, which is the input data DATA sampled at the frame pulse period, with a predetermined pattern of a multi-frame frame pulse.

The line I / Fs 30A to 30D, 32A
To 32D correspond to the line interface unit, the transcoder units 35A to 35D and 36A to 36D correspond to the compression / encoding conversion unit, and the retrigable monomultis 104 and 112, the D-type flip-flop 106, the latch circuits 108 and 114. , AND circuit 110 is the signal generator 2
5A to 25C correspond to the alarm generating means, and the fuse 1
Reference numeral 24 corresponds to an alarm recording unit, MMC 130 corresponds to a voice encoding / decoding circuit, PLD 134 corresponds to a voice speed conversion circuit, and VCP 132 corresponds to a multiplexing / demultiplexing circuit.

[0065]

As described above, the first aspect of the present invention provides
A connection control device for controlling connection between a plurality of image communications having different compression encoding rules, wherein a line interface unit and a compression encoding conversion unit of each of the plurality of image communications are connected to a single bus. .

As described above, since the line interface unit and the compression coding conversion unit of each of the plurality of image communications are connected to a single bus, the connection relationship between the line interface and the transcoder is not fixed. Flexibility is increased, and circuit switching and broadcast distribution functions are diversified. The invention according to claim 2 uses a high-speed serial bus as a bus.

As described above, since the high-speed serial bus is used, the line interface unit and the compression / encoding / conversion unit can be easily connected. Claim 3
The line interface unit and the compression-encoding conversion unit may add an identification code identifying a transmission source unit to the data and transmit the data to the bus, and each unit may transmit the data transmitted through the bus. It is determined whether or not the data is received by the own unit based on the identification code added to.

As described above, each unit determines whether or not it is data to be received by itself from the identification code added to the data transmitted on the bus, so that the connection relationship between the line interface and the transcoder is fixed. However, flexibility is increased, and 1: 1 and 1: N transcoding and broadcasting can be performed with simple control. According to the fourth aspect of the present invention, the units are chain-connected by the single bus, and the priority is given in the order of the chain connection.

As described above, the units are connected in a chain by a single bus, and the priority is given in the order of the chain connection. Therefore, the priority can be given to each unit with a simple configuration. According to the fifth aspect of the present invention, each unit sends data to a single bus according to its priority.

As described above, since each unit sends data to a single bus in accordance with its priority, bus contention and congestion control can be performed. The invention according to claim 6 is provided with a data transfer period for transferring data using a bus, and a congestion control period for determining which of the units transfers data using the bus.

As described above, since the data transfer period for transferring data using the bus and the congestion control period for determining which of the units transfer data using the bus are provided, It is possible to determine which unit will send data to the bus. According to the seventh aspect of the invention, the congestion control is performed by notifying the operation mode between the units adjacent to the own unit and having higher and lower priorities.

As described above, the congestion control is performed by notifying the operation mode between units having higher priorities and lower units adjacent to the own unit, so that it is not necessary to provide a dedicated control unit for performing the congestion control. . The invention according to claim 8 is
It has a branch path that branches from a unit connected in a chain by a single bus and connects other units.

As described above, since there is a branch path branched from a unit connected in a chain by a single bus and connected to another unit, a port having a large data transfer amount can be preferentially selected. If the chain is not broken, the unit can be actively loaded. According to a ninth aspect of the present invention, when an abnormality occurs in any of a plurality of units chain-connected by a single bus, by controlling a unit adjacent to the unit in which the abnormality has occurred,
Disconnect the failed unit from the single bus.

As described above, by controlling the unit adjacent to the unit in which the abnormality has occurred, the unit in which the abnormality has occurred is separated from the single bus. Can be prevented and normal operation can be performed only with a normal unit. The invention according to claim 10 is that, when the congestion control is not detected within a predetermined period, each of the plurality of units chain-connected by a single bus determines that an abnormality has occurred in the own unit and the single unit has the single unit. Disconnect from the bus.

As described above, when the congestion control is not detected within a predetermined period, it is determined that an abnormality has occurred in the own unit, and the own unit is disconnected from the single bus. Can be prevented,
Only a normal unit can operate normally. The invention according to claim 11, comprising a plurality of cooling fans for cooling the device, an alarm generating means for generating an alarm when a fan pulse for driving a fan motor of each of the plurality of cooling fans is stopped for a predetermined period or more. Alarm recording means for recording which of the plurality of cooling fans has generated an alarm.

As described above, an alarm is generated when the fan pulse for driving the fan motor of each of the plurality of cooling fans stops for a predetermined period or more, and which of the plurality of cooling fans has generated the alarm is recorded. The failure of the fan can be accurately detected and its record can be recorded. In the twelfth aspect of the present invention, the compression encoding conversion unit encodes / decodes the PCM audio data into audio data having a first transmission rate, and an audio encoding / decoding circuit encoding the first transmission rate. An audio speed conversion circuit for performing a speed conversion between data and audio data having a second transmission speed different from the data, a compression coding conversion of image data, and multiplexing / multiplexing of the audio data having the second transmission speed; It has a compression coding conversion and multiplexing / demultiplexing circuit for performing separation.

As described above, since the audio speed conversion circuit for performing the speed conversion between the audio data at the first transmission speed and the audio data at the second transmission speed is provided, the existing audio encoding / decoding circuit and the compression Encoding conversion and multiplexing / demultiplexing circuits can be used. According to a thirteenth aspect of the present invention, the compression coding conversion unit has a CPU and a programmable gate array, and performs initialization of the CPU and the programmable gate array in parallel when power is turned on.

As described above, since the initialization of the CPU and the programmable gate array is performed in parallel when the power is turned on, the time required for the initialization can be reduced. According to the fourteenth aspect, the line interface unit comprises a DRA
M, and the received data is transmitted to the FIFO using a clock faster than the clock of the received data.
O is read out using the high-speed clock, and the data read out from the FIFO is latched by the clock of the received data and output.

As described above, the received data is written into the FIFO using a clock faster than the clock of the received data, and read out using the faster clock.
Since the data read from O is latched and output by the clock of the received data, the received data can be reliably read from the FIFO even when the clock of the received data is slow.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an image gateway device.

FIG. 2 is a block diagram illustrating an example of an image gateway device.

FIG. 3 is a block diagram of a connection control device according to an embodiment of the present invention.

FIG. 4 is a block diagram of a first embodiment of a connection part of each component unit of the connection control device with the high-speed serial bus 31.

FIG. 5 is a configuration diagram of a packet.

FIG. 6 is a diagram illustrating 1: 1 transcoding according to the present invention.

FIG. 7 is a diagram for explaining 1: N transcoding of the present invention.

FIG. 8: MPEG2 multicast transmission 1: N of the present invention
FIG.

FIG. 9 shows MPEG2 multicast transmission 1: N of the present invention.
FIG. 10 is a diagram for explaining another embodiment of the present invention.

FIG. 10 is a diagram for describing simultaneous operation of 1: 1 transcoding multiple channels and LAN distribution according to the present invention.

FIG. 11 is a diagram for explaining high-speed LAN distribution according to the present invention.

FIG. 12 is a block diagram of a second embodiment of a connection section of each component unit of the connection control device with the high-speed serial bus 31.

FIG. 13 is a diagram for explaining congestion control according to the present invention.

FIG. 14 is a diagram illustrating congestion control according to the present invention.

FIG. 15 is a block diagram of a third embodiment of a connection unit of each component unit of the connection control device with the high-speed serial bus 31.

FIG. 16 is a diagram showing one embodiment of a chain connection of the present invention.

FIG. 17 is a block diagram of a connection portion of each component unit of the connection control device with the high-speed serial bus 31 according to a fourth embodiment.

FIG. 18 is a block diagram of a fifth embodiment of a connection part of each component unit of the connection control device with the high-speed serial bus 31.

FIG. 19 is a diagram showing another embodiment of the chain connection of the present invention.

FIG. 20 is a diagram showing another embodiment of the chain connection of the present invention.

FIG. 21 is a circuit configuration diagram of a first embodiment of a fan alarm detection circuit of the present invention.

FIG. 22 is a circuit configuration diagram of a second embodiment of the fan alarm detection circuit of the present invention.

FIG. 23 is a block diagram of an internal circuit of the transcoder units 34A to 34D of the present invention.

FIG. 24 is a waveform chart for explaining the internal circuit of FIG. 23;

FIG. 25 is a waveform chart for explaining the internal circuit of FIG. 23;

FIG. 26 is a waveform chart for describing the internal circuit of FIG. 23.

FIG. 27 is a circuit configuration diagram of a conventional initialization.

FIG. 28 is a circuit configuration diagram of one embodiment of initialization of the present invention.

FIG. 29 is a timing chart for explaining the initialization of FIG. 28;

FIG. 30 is a circuit configuration diagram of a conventional multi-frame detection circuit.

FIG. 31 is a circuit configuration diagram of an embodiment of the multi-frame detection circuit of the present invention.

[Explanation of symbols]

 12A to 12D MPEG2 terminal 14A to 14D TV conference terminal 30A to 30D, 32A to 32D Line I / F 31 High-speed serial bus 34A to 34D Transcoder 35A to 35D, 36A to 36D Transcoder unit 38 Image gateway device 39 LAN server 40, 42 transmission unit 44, 46 reception unit 50 transmission channel ID setting unit 51 packet generation unit 54 reception channel ID setting unit 55 channel ID check unit 56 internal circuit 102 buffer 104, 112 retrigable mono-multi 106 D-type flip-flop 108, 114 Latch circuit 110 AND circuit 120 Switch 124 Fuse 126 Power supply monitor 128 Power supply control pulse generator 130 MMC 132 VCP 134 PLD 135, 136 FIFO 1 2,144 FPGA 143,145 ROM 150 CPU 147 delay circuit 160 FIFO 162 differentiating circuit 166, 168 flip-flop 170 pattern detector

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seiji Sugiyama 3-22-8 Hakata-ekimae, Hakata-ku, Fukuoka, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Kiyoshi Kitamura Hakata-ku, Fukuoka Prefecture Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inside of Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Yuji Ishii 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture (72) Inventor Jun Endo 3-22-8 Hakata-ekimae, Hakata-ku, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Akifumi Arita 3-2-28 Hakata-ekimae, Hakata-ku, Fukuoka Prefecture Fukuoka Kyushu Digital Technology Co., Ltd. (72) Inventor Kenji Oyachi Kanagawa Fujitsu Co., Ltd. (1-1) Umi Odanaka 4-1-1, Nakahara-ku, Saki-shi Inventor Akinori Kunai 4-1-1, Kamio-Danaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd. (72) Inventor Noriyuki Ihara Kanagawa Fujitsu, Ltd. (1-1) Kamitsudanaka 4-1-1, Nakahara-ku, Kawasaki-shi Inventor Yuichi Terui 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (reference) 5C059 KK34 MA00 RB01 RC22 RC32 RF02 SS06 SS30 TA72 TA75 TC22 UA02 UA05 UA09 UA23 UA29 UA32 5K032 CB01 CC02 CC06 DB15 DB20 DB22 DB26 DB31 EA04 EB08 EC01

Claims (14)

[Claims] 1. A connection control device for controlling connection between a plurality of image communications having different compression / encoding rules, wherein a line interface unit and a compression / encoding conversion unit of each of the plurality of image communications are connected to a single bus. A connection control device, wherein the connection control device is connected. 2. The connection control device according to claim 1, wherein a high-speed serial bus is used as said bus. 3. The connection control device according to claim 1, wherein the line interface unit and the compression coding conversion unit add an identification code for specifying a transmission source unit to data, and transmit the data to the bus. The connection control device according to claim 1, wherein each of the units determines whether or not the data is to be received by the own unit based on an identification code added to the data transmitted through the bus. 4. The connection control device according to claim 1, wherein the units are chain-connected by the single bus,
A connection control device, wherein priorities are given in the order of chain connection. 5. The connection control device according to claim 4, wherein each unit sends data to a single bus in accordance with its priority. 6. The connection control device according to claim 5, wherein: a data transfer period for transferring data using the bus;
A congestion control period for determining which of the units transfers data using the bus. 7. The connection control device according to claim 6, wherein the congestion control is performed by notifying an operation mode between units having higher and lower priorities adjacent to the own unit. Control device. 8. The connection control device according to claim 4, further comprising a branch path branched from a unit connected in a chain by the single bus and connected to another unit. 9. The connection control device according to claim 7, wherein when an abnormality occurs in any of the plurality of units chain-connected by the single bus, control of a unit adjacent to the unit in which the abnormality has occurred is performed. A connection control device for disconnecting the unit in which the abnormality has occurred from the single bus. 10. The connection control device according to claim 6, wherein each of the plurality of units chain-connected by the single bus determines that an abnormality has occurred in its own unit when the congestion control is not detected within a predetermined period. A connection control device, wherein the own unit is disconnected from the single bus. 11. The connection control device according to claim 1, further comprising a plurality of cooling fans for cooling the device, wherein an alarm is generated when a fan pulse for driving a fan motor of each of the plurality of cooling fans stops for a predetermined period or more. A connection control device comprising: an alarm generating unit that generates an alarm; and an alarm recording unit that records which of the plurality of cooling fans has generated an alarm. 12. The connection control device according to claim 1, wherein the compression encoding conversion unit encodes / decodes the PCM audio data into audio data of a first transmission rate; An audio speed conversion circuit for performing a speed conversion between audio data of a first transmission speed and audio data of a second transmission speed different from the first transmission speed; A connection control device comprising a compression coding conversion and multiplexing / demultiplexing circuit for multiplexing / demultiplexing voice data at a high speed. 13. The connection control device according to claim 1, wherein the compression coding conversion unit has a CPU and a programmable gate array, and performs initialization of the CPU and the programmable gate array in parallel when power is turned on. A connection control device, characterized in that: 14. The connection control device according to claim 1, wherein the line interface unit has a FIFO using a DRAM, and writes received data to the FIFO using a clock faster than a clock of the received data. The connection control device reads the data using the high-speed clock, latches the data read from the FIFO with the clock of the received data, and outputs the latched data.