JP2000092066A - Atm cell assembly/disassembly device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve transfer efficiency on a host bus by transferring payloads for plural cells to a host memory in the DMA cycle at a time. SOLUTION: A cell reception/disassembly part 6 disassembles received cells, stores the payload obtained by disassembly in a reception payload buffer 13 for each VC, and when a prescribed transfer command issuance condition is satisfied, prepares a DMA command for DMA transferring the stored payload and stores the DMA command in a second FIFO buffer as a queue. A host bus interface part 8 successively reads the DMA command stored in a DMA command FIFO 16 and DMA transfers the payload stored inside the reception payload buffer 13 to the host bus 4 corresponding to the read DMA command. A mode for forcibly issuing a transfer command is prepared as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode) The present invention relates to an ATM cell assembling / disassembling apparatus arranged on an ATM terminal connected to a network, and particularly, as a receiving function, disassemble a received ATM cell sent from a physical layer device into a header and a payload, Furthermore, virtual channels (hereinafter, “V
C (abbreviated as “VirtualChannel”)), and configures a received packet and transfers it to a higher-level application.
The present invention relates to a TM cell assembling / disassembling apparatus.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing a configuration of a conventional ATM cell assembling / disassembling apparatus. As shown in FIG. 12, the ATM cell assembling / disassembling apparatus 81 is connected to a physical layer device 85 that transmits and receives frame data to and from an ATM network. On the other hand, it is connected via a host bus 84 to a host CPU 82 for operating a host application and a host memory 83 for storing transmission / reception packets and the like. Host CPU 8
2 also manages the host memory 83 and issues commands to the ATM cell assembling / disassembling device 81.

[0003] The ATM cell assembling / disassembling device 81 has a cell receiving / disassembling device for receiving and disassembling cells as an internal configuration.
A physical layer device interface unit 89 for transmitting and receiving ATM cells to and from the physical layer device 85; and a host bus 84. And a host bus interface unit 88 for transferring data to a host CPU 83 and a host memory 83 connected thereto via a USB port.

[0004] A cell receiving / disassembling section 86 performs filtering and cell disassembly of the received cell sent from the physical layer device interface section 89, and transfers the disassembled payload to the host memory 83 by DMA transfer. Reception / disassembly control unit 8 for instructing
0, a reception parameter storage unit 91 for storing necessary information (reception parameters) such as a DMA transfer destination at the time of reception control, and a disassembled payload stored in the host memory 3 as D.
Receive FIFO, temporarily stored until MA transfer
901.

The received cell received by the physical layer device interface section 89 is transmitted to a cell reception / disassembly control section 80.
After being filtered by the channel identifier VPI / VCI, the packet is decomposed into a 5-byte header and a 48-byte payload. The decomposed payload is transferred to the reception FIFO 9 until DMA transfer to the host memory 83.
01 is temporarily stored.

[0006] The cell reception / disassembly control unit 80 refers to the DMA transfer destination address stored in the reception parameter storage unit 91 and transfers the payload temporarily stored in the reception FIFO 901 to the host memory 83 by DMA transfer. Request to the bus interface unit 88. Receive FIFO
The payloads stored in the DMAs 901 are sequentially stored in the DMAs in the order of storage.
The data is transferred and reconstructed as a packet for each VC in the host memory 83.

Here, since the host memory 83 stores packets for each VC, an area is reserved for each VC, and it is not possible to transfer payloads of different VCs to a continuous address area. A DMA transfer is usually a single D
The transfer is performed at a rate of one cell payload per MA transfer cycle. This is because, when a certain payload stored in the reception FIFO 901 differs from the VC to which the next stored payload belongs, the storage addresses on the host memory 83 to which the two payloads should be transferred are consecutive. This is because, in rare cases, burst transfer (a DMA transfer format in which an address is output once and then only data is continuously transferred) cannot be performed in one DMA transfer cycle.

When a plurality of cells of the same VC are successively stored in the reception FIFO 901 and their transfer destination is a continuous address space in the host memory 83, one cell is stored.
In a single DMA transfer cycle, for example, data may be transferred collectively for five cells. A retrospective search of technologies belonging to the field of the present invention from past patent applications shows that
Japanese Unexamined Patent Publication No. 209 discloses a means for storing a line-input cell in a FIFO control buffer configured for each VC, and judging from the past output status and the like, discriminating a time at which output can be performed for each input cell. And a means for outputting a corresponding cell at the timing of the determined time.

Japanese Patent Application Laid-Open No. 7-99494 discloses that
Means for accumulating the arriving cells in a buffer for each VC, means for accumulating the accumulated cells for each VP (Virtual Path) triggered by counting a predetermined number of cells,
There is disclosed a technique of outputting cells accumulated for each P to a transmission line at intervals of time slots set for each VP.

Further, Japanese Patent Application Laid-Open No. 10-32591 discloses means for accumulating arriving cells in a buffer for each VC, generating a transmission request at predetermined cell intervals, reading the cell time at that time from a clock, and reading out the FIFO. Means for accumulating data in a control request queue, and a VC to be transmitted at the next cell time according to the time information of the request queue and the accumulation status of the buffer.
And a means for determining

[0011]

The above-described conventional ATM cell assembling / disassembling apparatus has a drawback that the transfer efficiency on the host bus 4 is not good.

The reason is that, conventionally, a FIFO (first-in-first-out) control buffer is used as the reception FIFO 901 as means for temporarily storing the reception payload in the ATM cell assembling / disassembling apparatus. Incidentally, the FIFO control means storing data in the order of arrival and reading out the data in the order in which the data was stored.

For this reason, the temporarily stored payload of the reception cell is stored in the reception FIFO 901 in the order of storage, that is,
It can only be read out in the order in which it was received.

On the other hand, an area in the host memory 83, which is the destination of the DMA transfer of the payload, is secured for each VC, and it is not possible to transfer a payload of a different VC to a continuous address area.

In general, a DMA transfer is performed by one DMA transfer.
In a cycle, data can be transferred only to a continuous address area.

However, in general, in an ATM cell assembling / disassembling apparatus, one VC cell is not always received continuously, and a plurality of VC cells may be received separately. Is appropriate.

For this reason, the reading of the received payload is performed as follows.
It is appropriate to consider that the VC changes every time, and it is considered that the address of the DMA transfer destination is not continuous.

Therefore, except for the case where a plurality of cells of the same VC are received consecutively by accident, generally one DMA
It is impossible to DMA-transfer a payload of a plurality of cells in a cycle.

For this reason, in the conventional example, it is necessary to perform the DMA transfer for each payload of one cell.
Each time the transfer is performed, an overhead occurs at the start of the DMA cycle, and the transfer efficiency on the host bus 4 is degraded.

In the following, the above situation will be described based on the host bus 84.
As a well-known “PCI bus interface”
An example in which a 32-bit bus (hereinafter abbreviated as "PCI") is used will be described.

The literature, "PCI LOCAL BUS S
PECIFICATION REVISION 2.1
(Published by PCI SIG).
The A transfer corresponds to a memory write operation of the PCI.

FIG. 13 is a timing chart showing the most typical PCI memory write operation. When performing DMA transfer, master (conventional ATM cell assembling / disassembling device)
Makes the REQ # signal LOW at time T1, and requests the right to use the bus. The right to use the bus is given by a device called an arbiter on the PCI bus system setting the GNT # signal to LOW at time T2. In response,
The master sets FRAME # to LOW at time T3 and
A transfer is started. Between time T1 and time T3,
This is a period for acquiring the right to use the bus, and requires at least two clocks.

The master sets FRAME # to LOW and simultaneously outputs the address of the DMA transfer destination for one clock. The period from time T3 to time T4 is a period called “address phase”.

Following the address phase, the master
The bit data is transferred one word (4 bytes) per clock, and at time T5, the output of all data ends, and the DMA transfer ends.

The period from the time T4 to the time T5 when this data is output is called a "data phase".
When transferring byte payload data, it takes 12 clocks. As described above, at least 15 clocks are required for DMA transfer of the payload of one cell. In the DMA cycle from time T1 to time T5, the acquisition of the bus use right and the address phase from time T1 to time T4 are independent of the data transfer amount.
This is an overhead required once per DMA cycle, and requires three clocks. That is, every time the payload is DMA-transferred for one cell, three clocks are wasted.

Conventionally, the payload of 5 cells is
Attempting to perform MA transfer requires five DMA cycles, and the time required for DMA transfer is (overhead + data phase) × 5 = (3 + 1)
2) × 5 = 75, and a time for a total of 75 clocks is required. If the payload of 5 cells can be transferred in one DMA cycle, (overhead + data phase) × 1 = (3 + 6)
0) × 1 = 63, so that the overhead can be reduced by four times and the DMA transfer can be performed in a time equivalent to 63 clocks.

Further, of the overhead, a period for acquiring the bus use right (from time T1 to time T3).
During the period, when a host other than the ATM cell assembling / disassembling apparatus (for example, the host CPU 2) is using the host bus 3, the bus use right cannot be obtained immediately, and a longer time is required. Has the potential. Therefore, the overhead generally takes a longer time even if it is at least two clocks.

According to the above fact, the prior art has a drawback that the transfer efficiency on the host bus 4 is not good because only one cell payload can be DMA-transferred to the host memory 3 in one DMA transfer cycle. Understood. The present invention has been made in view of the above-described problems in the conventional ATM cell assembling / disassembling apparatus.
An object of the present invention is to provide an ATM cell assembling / disassembling apparatus which improves transfer efficiency on a host bus by transferring data to a host memory in an A cycle.

[0029]

In order to solve the above problems, an ATM cell assembling / disassembling apparatus according to a first aspect of the present invention is arranged in an ATM terminal connected to an ATM network,
In an ATM cell assembling / disassembling apparatus including a physical layer device interface unit, a cell receiving / disassembling unit, a host bus interface unit, and a cell assembling / transmitting unit, the cell receiving / disassembling unit includes the physical layer device interface unit. And a payload storage unit for decomposing the cell received via the header into a header and a payload, and storing the payload obtained by the decomposition in the first first-in first-out memory for each virtual channel, and when a predetermined transfer command issuing condition is satisfied. A direct memory access command generating means for generating a direct memory access command for causing the stored payload to be transferred by direct memory access, and a direct memory access command storing means for storing the direct memory access command in a second first-in first-out memory The host bus interface unit sequentially reads the direct memory access commands stored in the second first-in first-out memory, and accumulates in the first first-in-first-out memory according to the read direct memory access commands. Transferring the transferred payload to an external memory via a bus connected to the bus host interface unit.

Here, the predetermined transfer command issuance conditions include: (1) when the last cell of a received packet is received, the data capacity of the payload of the number of cells obtained by adding 1 to the number of received cells is equal to a predetermined value. (3) when the number of cells stored in the storage payload in the first first-in first-out memory reaches a predetermined maximum number of transferable cells that can be continuously transferred,
It is possible to specify any one of

In the first first-in first-out memory, a chain for managing the area in the buffer for each virtual channel is provided, and the area for each virtual channel for storing the payload is stored in the chain for the corresponding virtual channel. Can be logically combined.

In the first first-in first-out memory, an empty block area is provided, and when storing a new payload, a block is cut out from the empty block area and used as a storage area for the new payload. When direct memory access transfer of the stored payload ends, the area occupied by the stored payload can be released as the free block area.

Further, the direct memory access command generating means includes at least a cell reception / disassembly control unit and a reception buffer management unit for the reception payload buffer as information necessary for generating the direct memory access command. (1) Direct memory access transfer destination address indicating the direct memory access transfer destination of the payload; (2) Direct memory access transfer destination buffer capacity indicating the remaining capacity of the continuous address space in the direct memory access transfer destination of the payload; (3) once The maximum number of continuous transfer cells corresponding to the upper limit of the number of payloads to be transferred in the direct memory access transfer cycle, (4) the first storage address in the first first-in first-out memory, (5) the last storage address in the first first-in first-out memory, 6) The number of cells corresponding to the payload stored in the first first-in-first-out memory,
It is possible to have means for storing any of the items.

In order to solve the above problem, in addition to the above configuration, the cell receiving / disassembling unit is adapted to handle the entire payload specified in the entire direct memory access command stored in the second first-in first-out memory. Means for counting the number of cells in the entire cell, and issuing the direct memory access command when the number of cells is smaller than a predetermined forced transfer threshold.
A TM cell assembling / disassembling apparatus is provided.

The ATM cell assembling / disassembling apparatus according to the present invention is different from the conventional ATM cell assembling / disassembling apparatus in that the received payload is temporarily stored in a first-in first-out memory.
Since direct memory access transfer was performed by reading one cell at a time, this point was improved. As a temporary storage area for the received payload, the received payload was stored and managed for each virtual channel, and the payloads of a plurality of cells were read together. The transfer efficiency on the host bus is improved by providing "payload temporary storage means" for transferring the payload of a plurality of cells to the host memory in one direct memory access cycle. .

That is, with the above configuration, the AT of the present invention
In the M-cell assembling / disassembling apparatus, since the payload of a plurality of cells is transferred to the external memory connected to the host bus in one direct memory access cycle, the overhead related to the DMA transfer can be reduced. Thus, the transfer efficiency on the host bus can be improved.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a structure of an ATM cell assembling / disassembling apparatus according to a first embodiment of the present invention.

Referring to FIG. 1, an ATM cell assembling / disassembling apparatus 1 is similar to a conventional ATM cell assembling / disassembling apparatus.
It is connected to a physical layer device 5 that transmits and receives frame data to and from the TM network. On the other hand, it is connected via a host bus 4 to a host CPU 2 for operating a host application and a host memory 3 for storing transmission / reception packets and the like. Host C
The PU 2 manages the host memory 3 and assembles ATM cells.
It also issues commands to the disassembly device 1 and the like.

The ATM cell assembling / disassembling apparatus 1 has, as its internal configuration, a cell receiving / disassembling apparatus for receiving cells and disassembling cells.
A physical layer device interface unit 9 for transmitting and receiving ATM cells to and from the physical layer device 5; a host bus 4; And a host bus interface unit 8 for transferring data to the host CPU 2 and the host memory 3 connected thereto via the. Up to the above configuration, it is the same as the conventional ATM cell assembling / disassembling apparatus.

The cell receiving / disassembling unit 6 performs filtering and cell disassembly of the received cells sent from the physical layer device interface unit 9 as in the conventional ATM cell assembling / disassembling apparatus, and stores the disassembled payload in the host. Memory 3
Host bus interface unit 8 to perform DMA transfer to
, A cell reception / disassembly control unit 10 that instructs a DMA transfer destination, and information (reception parameters) required for a DMA transfer destination and the like during reception control
Is provided with a reception parameter storage unit 11 for storing.

In addition to the above configuration, the cell receiving / disassembling unit 6 in the first embodiment of the present invention serves as a means for temporarily storing the disassembled payload until it is DMA-transferred to the host memory 3. , Random access memory (R
AM) is provided.

The receiving payload buffer 13 has a "dual port R" in which writing and reading can be performed independently.
AM "is suitable. Receive payload buffer 1
The area of the RAM used as 3 is divided into areas each of which can store one cell of payload data (hereinafter, referred to as “payload storage block”) as a minimum unit. The payload storage blocks are sequentially and logically connected to each other to form a payload storage block chain.
O method is used.

The payload of each reception cell temporarily stored in the reception payload buffer 13 is stored in the above-mentioned payload storage block, and a payload data chain is formed for each virtual channel (hereinafter abbreviated as “VC”). With this configuration, the reception payload buffer 13 has a configuration in which a plurality of FIFO buffers storing the payload of the reception cell for each VC exist.

For example, n Vs from VC1 to VCn
Assuming that the payload data is temporarily stored in the reception payload buffer 13 with respect to C, as shown in FIG. 1, the reception payload buffer 13 includes the VC1 payload data chain 14a to the VCn payload data chain 14z. There are n payload storage block chains, and a payload is stored in each payload storage block chain for each corresponding VC. In the RAM of the reception payload buffer 13, payload storage blocks in which no payload data is stored (hereinafter, referred to as “empty payload storage blocks”) are also logically connected to form an empty storage block chain 15.

The cell receiving / disassembling unit 6 also includes a receiving buffer managing unit 12 for managing a payload storage block chain for storing the payload in the receiving payload buffer 13 described above.
3 and the reception buffer management unit 12 are used together as a temporary storage unit of the reception payload.

FIG. 2 is a block diagram showing a configuration of the reception payload buffer 13 according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a payload storage block provided in the reception payload buffer 13.

Referring to FIG. 2, the VC1 payload data chain 1
4a and an empty storage block chain 15 are installed. (Since the configuration of the payload storage block chain of the other VC is the same as that of the VC1 payload data chain 14a, the description is omitted.)

Assuming that a payload of 3 cells is stored in the VC1 payload data chain 14a, the VC1 payload data chain 14a has
There are a total of three payload storage blocks, a C1 payload storage block (1) 21a, a VC1 payload storage block (2) 21b, and a VC1 payload storage block (3) 21c. Is stored.

As shown in FIG. 3, each payload storage block stores a 48-byte payload data 41 and a link pointer 42 indicating the storage address of the storage block to be connected next in the RAM. The individual payload storage blocks are logically connected by the link pointer 42 to form a payload storage block chain.

In the VC1 payload data chain 14a, the VC1 payload storage block (1) 21a
Of the VC1 payload storage block (2) 21b indicates the storage address of the VC1 payload storage block (2) 21b, and the link pointer of the VC1 payload storage block (2) 21b indicates the storage address of the VC1 payload storage block (3) 21c. Shows the connection relationship to the storage block, thus forming the payload storage block chain. (Hereinafter, such a connection relationship by the link pointer is expressed as “logically connected”.)

The empty storage block chain 15 also forms an empty storage block chain with a similar configuration. V
The storage address of the VC1 payload storage block (1) 21a of the first payload storage block and the storage address of the VC1 payload storage block (3) 21c of the last payload storage block in the C1 payload data chain 14a are respectively the first storage address 22, It is stored in the reception parameter storage unit 11 as the last storage address 23. In addition, the number of payload storage blocks in the VC1 payload data chain 14a is also stored in the reception parameter storage unit 11 as the number of storage cells 24.

The storage address of the empty payload storage block (1) 31a of the first empty payload storage block in the empty storage block chain 15 and the empty payload storage block (4) of the last empty payload storage block
The storage addresses of 31d are stored in the reception buffer management unit 12 as the first free block address 32 and the last free block address 33, respectively. The number of empty payload storage blocks in the empty storage block chain 15 is also stored in the reception buffer management unit 12 as the number of empty blocks 34.

When a new cell is received from the VC1, the cell reception / disassembly control unit 10 requests the reception buffer management unit 12 to store the payload of the reception cell. In response, the reception buffer management unit 12
One new payload storage block is cut out from the beginning of the empty storage block chain 15 and the payload is stored here.
It is logically linked to the end of the payload data chain 14a.

Specifically, the reception buffer management unit 12
The head empty block address 32 is rewritten with the link pointer of the empty payload storage block (1) 31a indicated by the head empty block address 32. As a result, the empty payload storage block (1) 31a is separated from the empty storage block chain 15. The payload of the new received cell is stored in the empty payload storage block (1) 31a.

Further, the reception buffer management unit 12 rewrites the link pointer of the VC1 payload storage block (3) 21c of the last payload storage block in the VC1 payload data chain 14a with the head empty block address 32 before being rewritten. For this reason, the value before the rewriting of the head empty block address 32 is temporarily stored in the reception buffer management unit 12.

Thus, the empty payload storage block (1) 31a is cut out from the beginning of the empty storage block chain 15, and the VC1 payload data chain 14
Logically connected to the end of a.

When the payload of VC1 is not stored in the reception payload buffer 13 at all, there is no VC1 payload data chain 14a, and the reception buffer management unit 12 stores the payload of the reception cell. Generate a new payload storage block chain for VC1.

The reception buffer management unit 12 first extracts an empty payload storage block from the empty storage block chain 15 as described above, and stores the payload of a new reception cell here.

Then, the storage address of the empty payload storage block in which the payload is stored is stored in the cell
Notify the disassembly control unit 10 and notify the cell reception / disassembly control unit 10
Writes this in the start storage address 22 and the end storage address 23, and sets the storage cell number 24 to 1.

Thus, the storage block storing the new payload is recognized as the first storage block of the VC1 payload storage block chain, and a new payload storage block chain is generated.

The cell reception / disassembly unit 6 is adapted to transmit a DMA transfer command (hereinafter, referred to as a “DMA transfer command”) issued by the cell reception / disassembly control unit 10 to the host bus interface unit 8.
DMA command FIF for temporarily storing
O16 is provided.

When the storage of the received payload with respect to the VC 1 is completed, the cell reception / disassembly control unit 10 transfers the payload stored in the reception payload buffer 13 to the host bus interface unit 8 when a certain condition is satisfied.
A DMA command is issued to request transfer.

In order to issue the DMA transfer command, the reception parameter storage unit 11 stores the following information as shown in the schematic diagram of FIG. 4 showing the content configuration of the reception parameter storage unit 11. (1) DMA transfer destination address 51 indicating the DMA transfer destination of the payload, (2) DMA transfer destination buffer capacity 52 indicating the remaining capacity of the continuous address space in the DMA transfer destination of the payload, (3) Transfer in one DMA transfer cycle The maximum number 53 of continuously transferred cells as a threshold for limiting the number of payloads to be transmitted. In addition to these,
(4) The start storage address 22, (5) The end storage address 23, (6) The storage cell number 24 is also stored in the reception parameter storage unit 11, and these storage information is recorded for one VC. The same information is stored in the reception parameter storage unit 1 for all other VCs.
1 is stored.

The conditions under which the cell reception / disassembly control unit 10 issues a DMA transfer command, that is, the DMA transfer command issuance criterion in the present embodiment are as follows. (1) When the last cell of the received packet is received,
(2) When all of the stored payloads cannot be transferred to the host memory 3 in one DMA transfer cycle when cells are received any more, that is, when the number of stored cells is 24
The data capacity of the payload for the number of cells obtained by adding 1 to
(3) When the number 24 of cells stored in the payload stored in the payload buffer 13 reaches the maximum number 53 of continuous transfer cells. When any one of the above conditions is met, the DMA
The transfer command includes information as shown in the schematic diagram of the content structure of the DMA transfer command in FIG.

The cell reception / disassembly control unit 10 includes a DMA transfer destination address 51, a head storage address 22, a storage cell number 2
4 are respectively transferred to the DMA transfer destination address 61,
Stored in the head storage address 62 and the number of transfer cells 63, D
This is an MA transfer command.

The cell reception / disassembly control section 10 stores the DMA transfer command in the DMA command FIFO 16.
The host bus interface unit 8 reads the DMA transfer command from the beginning of the DMA command FIFO 16 and obtains a cell given by the number of transfer cells 63 from the payload storage block chain starting from the payload storage block indicated by the head storage address 62. The payload for several minutes is read, and the payload data is transferred to the area in the host memory 3 indicated by the DMA transfer destination address 61 in one DMA transfer cycle.

At this time, the host bus interface unit 8
Knows the address of the next connected payload storage block from the link pointer of the payload storage block indicated by the head storage address 62. By repeating the series of processes described above, the storage addresses of all the payload storage blocks in the payload storage block chain are confirmed prior to the DMA transfer, and are used when reading the payload.

The payload storage block chain from which the payload has been read is returned to the empty storage block chain.

Now, it is assumed that the VC1 payload data chain 14a shown in FIG. 2 has been returned to the empty storage block chain. In this case, VC1 payload data chain 1
4a is returned to the free storage block chain by being connected to the end of the free storage block chain 15.

For this reason, the host bus interface unit 8 notifies the reception buffer management unit 12 of the number of transfer cells 63. Further, the VC1 payload storage block (3) 21 which is the last of the VC1 payload data chain 14a
The storage address of c is also notified to the reception buffer management unit 12.

The reception buffer management unit 12 sets the link pointer of the empty payload storage block (4) 31d indicated by the last empty block address 33 to the head storage address 6
2 and rewrite the last empty block address 33 with VC
Rewriting is performed using the storage address of one payload storage block (3) 21c. Then, the number of empty blocks 34 is added by the number of transfer cells 63.

If the number of empty blocks 34 is 0 and there is no empty storage block chain 15, the first empty block address 32 is replaced with the first empty block address 32 with the first storage address 62, and the VC1 payload storage block (3) 2
The final empty block address 33 is stored using the storage address 1c, and the empty block number 34 is output using the transfer cell number 63.
Are respectively rewritten to replace the VC1 payload data chain 14a as an empty storage block chain.

FIG. 6 is a flowchart showing a receiving operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention. Hereinafter, the reception operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention will be described with reference to FIGS.

First, the channel identifier VPI / VCI of the received cell received by the physical layer device interface section 9 is confirmed by the cell reception / disassembly control section 10, and it is determined whether or not the ATM cell assembling / disassembling apparatus should receive the received cell. Is determined.

Here, the following operation will be described assuming that the received cell belongs to VC1 and it is determined that VC1 is received. At this time, the cell reception / disassembly control unit 10 determines the storage address of the reception parameter related to VC1 in the reception parameter storage unit from the channel identifier VPI / VCI. For this purpose, it is only necessary to have a correspondence table between VCs and the parameter storage addresses.

In step S1, based on the parameter storage address thus obtained, the cell reception / disassembly control unit 10
Is stored in the reception parameter storage unit 11 for subsequent reception processing.
, And temporarily stores the received parameters in the cell reception / disassembly control unit 10.

In step S2, the cell reception / disassembly control unit 10 stores the 53-byte received cell into a 5-byte header and a 4-byte header.
Decompose into an 8-byte payload. The cell reception / disassembly control unit 10 sends the payload of the disassembled reception cell to the reception buffer management unit 12.
3 to be temporarily stored. At this time, the storage cell number 24 is also notified.

In step S3, in response to this, the reception buffer management unit 12 stores the payload in the first empty storage block of the empty storage block chain 15, and in step S4, forms a payload storage block chain for VC1.

FIG. 7 shows the payload storing operation (step S3 and step S3) in the first embodiment of the present invention.
4 is a flowchart showing details of (operation 4). Less than,
The payload storing operation according to the first embodiment of the present invention will be described with reference to FIG. Here, it is assumed that the reception payload buffer 13 stores the payload of VC1 for three cells as shown in FIG.

In step S 21, when the reception buffer management unit 12 is notified from the cell reception / disassembly control unit 10 that the payload is to be stored, the reception buffer management unit 12 uses the head empty block address 32 stored in the reception buffer management unit 12. In order to use the indicated empty payload storage block (1) 31a as a storage area for a new payload, a head empty block address 32 is temporarily stored therein.

In step S22, the contents of the head empty block address 32 are rewritten by the link pointer of the empty payload storage block (1) 31a. Thus, a free storage block for storing a new payload is cut out from the free storage block chain 15 and written there. In step S23, the reception buffer management unit 12
Store the new payload received.

In step S24, the reception buffer management unit 12 reads the number of stored cells 24, and in step S25, checks the number of payloads of the VC1 in the reception payload buffer 13 based on the number of stored cells 24. If the number of stored payloads is 0 and there is no VC1 corresponding to the VC1 payload data chain 14a, the process proceeds to step S26 to create a new payload storage block chain. In contrast, if the VC1 payload data chain 14a exists, the above-mentioned empty payload storage block (1) 31a storing the received payload is stored in the VC1
The process proceeds to step S27 in order to link to the end of the payload data chain 14a. If the VC1 payload data chain 14a already exists and the payload of three cells has already been stored, the process proceeds from step S25 to step S27. At this time, in step S27,
The reception buffer management unit 12 reads the final storage address 23 and calculates the storage address of the link pointer of the VC1 payload storage block (3) 21c.

In step S28, the pointer is rewritten with the storage address of the empty payload storage block (1) 31a.

In step S29, the cell reception / disassembly control unit 10 rewrites the last storage address 23 with the link pointer of the empty payload storage block (1) 31a.
, And the cell reception / disassembly control unit 10 executes this. Further, the reception buffer management unit 12 notifies the cell reception / disassembly control unit 10 that the payload storage and the payload storage block chain have been configured.

In step S30, the cell reception / disassembly control unit 10 updates the number of stored cells 24 by adding 1 to it.
Thus, the received payload is stored in the payload storage block chain of VC1 in the received payload buffer 13.

If the number of storage cells 24 is 0 and there is no VC1 payload data chain 14a, and the process proceeds from step S25 to step S26, in step S26 the reception buffer management unit 12 Empty payload storage block (1) 31 at address 22
The cell reception / disassembly control unit 10 is notified to write the storage address of a, and the cell reception / disassembly control unit 10 executes this.

Thereafter, the processing flow includes step S29,
Proceeding to step S30, the final storage address 23 and the number of storage cells 24 are updated. Thus, the received payload is stored in the received payload buffer 13, and a payload storage block chain of VC1 is newly generated.

Hereinafter, the operation after step S5 will be described with reference to FIG. 6 again. In step S5, when the payload of the received cell is stored in the reception payload buffer 13, the cell reception / disassembly control unit 10 determines whether the cell is the last cell of the received packet, and determines that the cell is the last cell. In this case, the payloads belonging to VC1 stored in the current received
In order to issue a DMA transfer command for A transfer, the process proceeds to step S8.

If it is not determined in step S5 that the cell is the last cell, in step S6, the reception / disassembly control unit 10
Even if a new reception cell is received in addition to the payload belonging to VC1 stored in the current reception payload buffer 13 and the payload is stored, all the payloads are once stored in the continuous address area in the host memory 3. It is determined whether or not transfer can be performed in the DMA transfer cycle.
This is performed by calculating the buffer capacity required when the payload of the number of cells obtained by adding 1 to the storage cell number 24 is stored in the host memory 3 and comparing the calculated buffer capacity with the DMA transfer destination buffer capacity 52. Here, when the capacity for storing the payload is larger than the DMA transfer destination buffer capacity 52, one DM including the payload of the new reception cell is performed.
Since it is determined that transfer by A transfer is impossible, only the payload belonging to VC1 stored in the current received payload buffer 13 is transferred collectively in one DMA transfer cycle. Let go.

There is still room in the DMA transfer destination buffer capacity 52 and the DM
If it is determined that the A transfer is possible, in step S7,
The disassembly control unit 10 checks the maximum number 53 of continuous transfer cells in the reception parameter storage unit 11 and compares it with the number 24 of stored cells. When the storage cell number 24 has reached the maximum continuous transfer cell number 53, the payload belonging to VC1 currently stored in the reception payload buffer 13 is transferred to one DM
In order to perform the DMA transfer in the A cycle, the processing is performed in step S
Proceed to 8. Otherwise, step S8 is not executed, and the cell reception process is terminated with only the payload stored.

Step S5, Step S6, Step S
7, the reception / disassembly control unit 10 stores the DMA transfer destination address 51, the head storage address 22, and the storage cell number 24 in the reception parameter storage unit 11 in FIG. DMA transfer destination address 61 and start storage address 62 of the indicated DMA transfer command
And the transfer cell number 63, issue a DMA transfer command, and store it in the DMA command FIFO 16.
Then, the storage cell number 24 is returned to 0, and the DMA transfer destination address 51 is prepared in preparation for the next DMA transfer command issuance.
To update. In this case, the receiving process ends with the payload stored and the DMA transfer command issued.

FIG. 8 is a flowchart showing a DMA transfer operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention. Hereinafter, the first embodiment of the present invention will be described with reference to FIG.
Of the ATM cell assembling / disassembling apparatus according to the embodiment of the present invention
The transfer operation will be described in detail.

In step S41, the host bus interface unit 8 sets the DMA command FIFO 16
When a transfer command is stored, one is read. Then, in step S42, based on the head storage address 62 in the DMA transfer command and the number of transfer cells 63,
The storage address of each payload storage block in which the payload to be DMA-transferred is stored in the reception payload buffer 13 is read. For example, the head storage address 62
Is the VC1 payload data chain 14a shown in FIG.
Of the VC1 payload storage block (1) 21a. In this case, first, the link pointer of the VC1 payload storage block (1) 21a is read, and
From this link pointer, the storage address of the VC1 payload storage block (2) 21b is obtained. Thereafter, while following the link pointer in the same manner, the addresses of the subsequent payload storage blocks are acquired, and all addresses of the payload storage blocks indicated by the transfer cell number 63 are acquired. To be stored temporarily.

When the processing in step S42 is completed,
In step S43, the host bus interface unit 8
Starts the DMA transfer to the area in the host memory 3 indicated by the DMA transfer destination address 61 of the DMA transfer command. The payload to be DMA-transferred is determined in step S42.
Are sequentially read from the payload storage block pointed to by the storage address obtained in step (1), and the payloads of a plurality of cells are all transferred to the host memory 3 in one DMA transfer cycle.

When the DMA transfer is completed, step S44
In, the payload storage block from which the payload has been read is returned to the empty payload storage block chain 15 as an empty payload storage block. First, the host bus interface unit 8 stores the start storage address 6
2, the transfer cell number 63, and the address of the VC1 payload storage block (3) 21c from which the payload was last read are notified to the reception buffer management unit 12.

In response to this, in step S45, the reception buffer management unit 12 sets the last empty block address 33
The link pointer of the empty payload storage block (4) 31d indicated by (3) is rewritten with the head storage address 62, and the VC1 payload data chain 14a is linked to the empty payload storage block chain 15. At this time, if the number of empty blocks 34 is 0 and there is no equivalent to the empty payload storage block chain 15, the head empty block address 32 is also rewritten with the head storage address 62.

Then, in step S46, the reception buffer management unit 12 sets the last free block address 33 to VC
Rewriting is performed with the address of one payload storage block (3) 21c.

Further, in step S47, the reception buffer management unit 12 rewrites the value of the number of empty blocks 34 by adding the number of transfer cells 63. Through the above processing,
The empty payload storage block is returned to the empty payload storage block chain 15, and the DMA transfer process ends, and the host bus interface unit 8 returns to the next DMA.
The process proceeds to the step of the DMA transfer process requested by the transfer command.

The receiving operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention,
When the A transfer operation is summarized, the received payload is stored for each VC. (1) When the last cell of the VC is received in step S5, (2) In step S6, the payload of the next received cell of the VC is received. If all data cannot be transferred to the host memory 3 in one DMA transfer cycle,
(3) In step S7, when the number 24 of payload cells stored in the payload buffer 13 reaches the maximum number 53 of continuous transfer cells, a DMA transfer command is issued, and the DMA transfer command is issued. When this is issued, the payload of the VC stored in the payload buffer 13 is transferred to the host memory 3 in one DMA transfer cycle.

Note that, specifically, the payload of 5 cells stored in the reception payload buffer 13 is
In the case where an MA transfer request is generated and DMA transfer is performed on the host bus 4 using the PCI bus interface, in the conventional example in which only one cell payload can be transferred in one DMA transfer cycle, five cells are transferred. The time required to make the payload a DMA transfer is (overhead + data phase) × 5 = (3 + 1)
2) × 5 = 75, and a time of 75 clocks in total is required. On the other hand, in the first embodiment of the present invention, a payload of a plurality of cells can be transferred in one DMA cycle. The time required to transfer a 5-cell payload to DMA transfer is (overhead + data phase) × 1 = (3 + 6)
0) × 1 = 63, which means that the DMA transfer can be performed in a time equivalent to 63 clocks by reducing the overhead for four times, and it can be seen that the transfer efficiency on the host bus is improved as compared with the conventional example.

Further, if there is a request to perform a DMA transfer immediately after receiving one cell from a VC or the like that is communicating with the CBR service, which is a kind of ATM communication service class, The maximum continuous transfer cell number 53 of the VC is set to 1 and the maximum continuous transfer cell number 53 is set to 5 for other VCs.
For the R service, DMA transfer is performed for each cell, but for the other services, it is necessary to wait until five cells are stored and use the DMA transfer method with high transfer efficiency. It is possible.

(Second Embodiment) FIG. 9 is a block diagram showing a configuration of an ATM cell assembling / disassembling apparatus according to a second embodiment of the present invention. A according to the present embodiment
In the TM cell assembling / disassembling apparatus, in addition to the configuration of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention shown in FIG. 1, a DMA transfer request number counter 71 is added as a constituent element. . The DMA transfer request number counter 71
The number of cells for which the DMA transfer command stored in the current DMA command FIFO 16 requests DMA is stored.

For example, when a DMA transfer command is stored in the DMA command FIFO 16, the DMA transfer request number counter 71 counts up by the number of transfer cells 63 of the stored DMA transfer command. DMA for 1 cell payload
It is possible to adopt a structure in which the countdown is performed by one when the data is transferred.

Hereinafter, A according to the first embodiment of the present invention will be described.
A description will be given of how the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention was devised by examining the TM cell assembling / disassembling apparatus.

In the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention, when the host bus 4 is empty and a DMA transfer request is issued, DMA transfer can be performed at any time and one cell is received. Under the condition that the payload of one cell can be DMA-transferred in the interim, no payload is stored in the reception payload buffer 13 and if the reception of 10 cells is not received, the DMA is not transmitted.
Under extreme conditions, such as when the transfer is not started, some 1
The time required from the start of reception for one VC to the end of the DMA transfer of the payload of 10 cells is 2
This is the time required to receive 0 cells.

On the other hand, in the case of the conventional example in which one cell is received and the payload for one cell is immediately output, the above-mentioned one is used to temporarily transfer the payload for one cell in consideration of the poor DMA transfer efficiency. Even if it takes .5 times, the DMA transfer can be performed if there is enough time to receive 16 cells after the start of reception.

As described above, when the host bus 4 is vacant and the payload is the A according to the first embodiment of the present invention.
When the TM cell assembling / disassembling apparatus encounters a condition that does not reach the number necessary for the DMA transfer, the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention includes:
There is a possibility that the throughput temporarily decreases as compared with the conventional example.

However, even in the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention, the host bus 4 is crowded, and the DMA transfer processing cannot catch up with the cell reception. In the case where there is a DMA transfer command, the cell is received during the DMA transfer processing for the payload stored earlier,
Since the payload enough to issue the DMA transfer command can be stored in the reception payload buffer 13, the command in the DMA command FIFO 16 can be replenished without interruption, and the DMA transfer can be instantaneously performed even when the host bus 4 is vacant. It does n’t happen
Such a temporary decrease in throughput does not occur.
In addition, by transferring a plurality of cells in one DMA cycle, the DMA transfer efficiency is improved as compared with the conventional example, so that the throughput is improved as compared with the conventional example.

In the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention, in order to prevent a temporary decrease in throughput, the DMA command FI is used.
It is sufficient that a certain amount of DMA transfer command is always stored in the FO 16. The ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention includes the first cell as described above.
Focusing on the problem of the ATM cell assembling / disassembling apparatus according to the embodiment, the present invention has been devised to improve this.

FIG. 10 shows a reception parameter storage unit 1 of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention.
FIG. 2 is a schematic diagram showing an internal configuration of the first embodiment. The reception parameter storage unit 11 of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention stores the reception parameter of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention shown in FIG. In addition to the internal configuration of the storage unit 11, a field of a forced transfer threshold 75 for storing a forced transfer threshold is provided. The internal components of the reception parameter storage unit 11 according to the present embodiment are also described for one VC, and are used for all other VCs.
, The same information is stored in each field similar to the configuration. Cell reception / disassembly control unit 10
Compares the above-mentioned DMA transfer request number counter 71 with the forced transfer threshold value 75, and if the current DMA transfer waiting cell number indicated by the DMA transfer request number counter 71 is smaller than the forced transfer threshold value 75, the first DMA in Embodiment
The DMA transfer command is forcibly issued even if the transfer command is not satisfied.

FIG. 11 is a flowchart showing a receiving operation of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention. The receiving operation of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention is different from the receiving operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention shown in FIG. The difference is that an operation for forcibly performing the DMA transfer of the payload accumulated in the reception payload buffer 13 when the DMA transfer request is small is added.

Up to step S4, the receiving operation is the same as that of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention. After the completion of the payload chain configuration in step S4, the cell reception / disassembly control section 10 compares the DMA transfer request number counter 71 with the forced transfer threshold 75, and
If the current number of cells waiting for DMA transfer indicated by the A transfer request number counter 71 is smaller than the forced transfer threshold value 75, the DMA transfer in the receiving operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention. Since the DMA transfer command is forcibly issued even if the criterion for issuing the command is not satisfied, the process can proceed to the DMA transfer command issuance in step S8.

If not, the flow advances to the final cell determination processing in step S5, and thereafter, the operation is the same as that of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention. In the present embodiment, when the payload is not stored much and the number of DMA transfer commands to the DMA command FIFO 16 is small, in an extreme case, the DMA transfer command is issued every time the payload of one cell is stored. And the same throughput as the conventional example can be secured.

If the number of received VCs has increased or the host bus 4 has become crowded, so that DMA transfer is not immediately started even if a DMA transfer command is issued, 1
By storing a plurality of payloads for one VC, as in the first embodiment, one D
Since the payload of a plurality of cells can be DMA-transferred in the MA cycle, the DMA transfer can be performed efficiently. Even in this case, the throughput can be improved as compared with the conventional example.

Further, in the present embodiment, under the condition that the host bus 4 can be used immediately and the amount of payload to be DMA-transferred is small, one DMA transfer cycle corresponds to one cell as in the conventional example. Is transferred by DMA and the host bus 4 is crowded, and when the payload that cannot be DMA is accumulated, the transfer with high transfer efficiency as in the first embodiment, that is, in one DMA transfer cycle It is possible to use the method of transferring the payload of a plurality of cells by DMA, and to improve the transfer efficiency of the host bus in the first embodiment.
Since the time required for DMA transfer of the C payload can also be reduced, there is an effect that the throughput of the entire ATM cell assembling / disassembling apparatus is improved.

In this embodiment, for a VC such as an ABR service that does not require much real-time performance, the forced transfer threshold value 75 is set to a small value, for example, 1, and there is almost no payload to be DMA-transferred. Only at the time, the DMA transfer command is issued in consideration of the forced transfer threshold value 75, and in other cases, the forced transfer threshold value 75 is set to a value larger than 1, and the DMA transfer command is issued with priority given the forced transfer threshold value 75. It is also possible to use them properly.

[0117]

As described above, according to the present invention, A
According to the TM cell assembling / disassembling apparatus, since it is possible to transfer the payload of a plurality of cells to the host memory in one DMA cycle, the overhead related to the DMA transfer can be reduced. There is an effect that transfer efficiency on the bus is improved. Also, under the condition that the host bus can be used immediately and the amount of payload to be DMA-transferred is small, as in the conventional example, the payload of one cell is DMA-transferred in one DMA transfer cycle and the host bus is congested. When the amount of payload that cannot be DMA is accumulated, transfer with high transfer efficiency, that is, DMA transfer of the payload of a plurality of cells in one DMA transfer cycle can be used, thereby improving the transfer efficiency of the host bus. In addition to the above effect, the time required for DMA transfer of all VC payloads can be reduced as compared with the conventional example, so that there is an effect that the throughput of the entire ATM cell assembling / disassembling apparatus is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a structure of an ATM cell assembling / disassembling apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a reception payload buffer 13 according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a payload storage block installed in a reception payload buffer 13;

FIG. 4 is a schematic diagram showing a content configuration of a reception parameter storage unit 11;

FIG. 5 is a schematic diagram of a content configuration of a DMA transfer command.

FIG. 6 is a flowchart showing a receiving operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing details of a payload storing operation (operations in steps S3 and S4) according to the first embodiment of the present invention.

FIG. 8 is a flowchart showing a DMA transfer operation of the ATM cell assembling / disassembling apparatus according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an ATM cell assembling / disassembling apparatus according to a second embodiment of the present invention.

FIG. 10 is a schematic diagram showing an internal configuration of a reception parameter storage unit 11 of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention.

FIG. 11 is a flowchart showing a receiving operation of the ATM cell assembling / disassembling apparatus according to the second embodiment of the present invention.

FIG. 12 is a block diagram showing the structure of a conventional ATM cell assembling / disassembling apparatus.

FIG. 13 illustrates a typical PCI bus interface 32;
FIG. 5 is a timing chart showing a memory write operation of a bit bus.

[Explanation of symbols]

 Reference Signs List 1 ATM cell assembling / disassembling device 2 Host CPU 3 Host memory 4 Host bus 5 Physical layer device 6 Cell receiving / disassembling unit 7 Cell assembling / transmitting unit 8 Host bus interface unit 9 Physical layer device interface unit 10 Cell receiving / disassembling control unit 11 reception parameter storage unit 12 reception buffer management unit 13 reception payload buffer 14a VC1 payload buffer 14z VCn payload buffer 15 empty storage block chain 71 DMA transfer request number counter

Claims (6)

[Claims] An ATM terminal connected to an ATM network, comprising: a physical layer device interface unit;
In an ATM cell assembling / disassembling apparatus including a disassembling unit, a host bus interface unit, and a cell assembling / transmitting unit, the cell receiving / disassembling unit converts a cell received via the physical layer device interface unit into a header and a payload. Payload storing means for storing the payload obtained by the decomposition in a first-in first-out memory for each virtual channel, and direct memory access to the stored payload when a predetermined transfer command issuing condition is satisfied. A direct memory access command creating means for creating a direct memory access command for transfer, and a direct memory access command storage means for storing the direct memory access command in a second first-in first-out memory; Sequentially reads the direct memory access commands stored in the second first-in first-out memory, and transfers the payload stored in the first first-in-first-out memory to the bus host interface unit in accordance with the read direct memory access commands. ATM cell assembling / disassembling apparatus, wherein direct memory access transfer to an external memory is performed via a connected bus. 2. The conditions for issuing the predetermined transfer command include: (1) when the last cell of a received packet is received, (2) the data capacity of the payload of the number of cells obtained by adding 1 to the number of received cells, (3) when the number of cells of the storage payload in the first first-in first-out memory reaches a predetermined maximum number of transferable cells that can be continuously transferred, 2. The ATM cell assembling / disassembling apparatus according to claim 1, wherein any one of the following is designated. 3. A chain for managing an area in the buffer for each virtual channel in the first first-in first-out memory, and an area for each virtual channel for storing the payload is stored in the chain for each corresponding virtual channel. The ATM cell assembly according to claim 1 or 2, wherein the ATM cell is logically connected by:
Disassembly device. 4. An empty block area is set in the first first-in first-out memory, and when storing a new payload, a block is cut out from the empty block area and used as a storage area for the new payload. And releasing the area occupied by the stored payload as the area of the empty block when the direct memory access transfer of the stored payload is completed. A described in item
TM cell assembling / disassembling device. 5. The direct memory access command creating means includes at least: (1) a direct memory access transfer destination address indicating a direct memory access transfer destination of a payload; 2) Direct memory access transfer destination buffer capacity indicating the remaining capacity of the continuous address space at the direct memory access transfer destination of the payload; (3) maximum continuous transfer cells corresponding to the upper limit of the number of payloads transferred in one direct memory access transfer cycle (4) the first storage address in the first FIFO, (5) the last storage address in the first FIFO, (6) the number of cells corresponding to the payload stored in the first FIFO. Within Further comprising means for storing the items at will, ATM CLAD device according to any one of claims 1 to 4, characterized in. 6. The cell receiving / disassembling unit is provided with means for counting the total number of cells corresponding to the entire payload specified in the entire direct memory access command stored in the second first-in first-out memory, The A according to any one of claims 1 to 5, wherein the direct memory access command is issued when the number of cells is smaller than a predetermined forced transfer threshold.
TM cell assembling / disassembling device.