JP2000092033A - High speed data transmission reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a transmission reception system with high quality of data transmission reception by detecting an error based on check data added to data and controlling a data selection section so as to output a normal output for the received data. SOLUTION: According to a conversion system, 10B/8B converters 6A, 6B convert received 10-bit parallel data into 8-bit parallel data and generate a frame pulse at a head position of data by a start flag. Furthermore, on the occurrence of a pattern not in existence in a conversion code in this processing, error signals ERRA, B are outputted. CRC check sections 7A, 7B apply CRC arithmetic operation to data received from a data extract section A and output data from which an ERR signal denoting normality/abnormity of data and CRC arithmetic data are eliminated. A data selection section 9 selects data without error from the ERR signal outputted from two systems of A side and B side circuits and output normal data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a transmitter / receiver, and more particularly to a high-speed data transmission / reception system with improved transmission / reception quality.

[0002]

2. Description of the Related Art A conventional high-speed data transmission / reception system will be described with reference to a conventional data transmission / reception system shown in FIG. The conventional data transmission / reception method includes a data transmitter unit 31 and a data receiver unit 32. The data transmitter unit 31 includes a data receiver 41 and an 8B / 10B converter 42.
And the P / S converter 43, and the data receiver 3
2 includes an S / P converter 44, a 10B / 8B converter 45, and a data transmitter 46.

[0003] A data transmitter section 31 receives input data, a frame pulse, and a clock signal. The data receiving unit 41 performs a process of changing input data to an internal clock from a phase locked loop (PLL). The 8B / 10B converter 42 converts the transmission data to 8 bi according to the conversion rule.
At the same time as the process of converting t data to 10-bit data, a start flag is added. P / S converter 4
In step 3, a process of converting parallel data into serial data is performed, and an output is output to the data receiver unit 32.

[0004] The data receiver section 32 includes a data transmitter section 3.
1, the S / P converter 44 converts the data transmitted as serial data into parallel data by judging a break in byte data with reference to the start flag. The 10B / 8B conversion unit 45 performs a process of converting 10-bit received data into 8-bit data according to a conversion rule, and at the same time, performs a process of generating a frame pulse at the head position of the data from the start flag. Also,
If data that does not conform to the conversion rule is received, a process for outputting a data reception error is performed. Data transmission unit 4
Reference numeral 6 outputs output data, a clock and a frame pulse returned to 8 bits, and outputs a reception error (ERR signal) when error data is received.

[0005]

In the conventional high-speed data transmission / reception system, the data transmitter section transmits 8 data.
The B / 10B conversion is performed, and the data receiver section performs the 10B / 8B conversion of the data. In the method of repeating the data conversion between transmission and reception, even if a bit error occurs at the time of data conversion. There is a problem that data errors cannot be detected if an error is generated according to the conversion rule.

Further, in the conventional high-speed data transmission / reception method, the higher the data transmission speed, the higher the probability of occurrence of bit errors, but only has a data transmission function, so that bit errors that occur are covered. There was a problem that you can not.

(Object of the Invention) An object of the present invention is to provide a high-speed data transmission / reception system with high data transmission / reception quality.

Another object of the present invention is to provide a high-speed data transmission / reception system having an enhanced data check function.

[0009]

According to the high-speed data transmission / reception system of the present invention, first and second data transmission systems (1A to 1C in FIG. 1) for transmitting check data added to input data for transmission.
4A, 1B to 4B), and first and second data receiving systems (5A in FIG. 1) for receiving transmission data of the first and second data transmitting systems of the data transmitting unit, respectively. 7A, 5B to 7B), a data selector (9) for selectively switching and outputting the output data of the first and second data receiving systems, and a data selector for the first and second data receiving systems. A data receiver comprising: a control unit (8A, 8B, 9) for detecting an abnormality of received data based on the added check data and controlling the data selecting unit so as to output a normal output of a receiving system as received data. And a part.

Further, the first and second data transmission systems have a check data adding section and a bit number converting section for converting the number of bits of data connected to the check data adding section. The first and second data receiving systems include a bit number inverse converter for inversely converting the number of bits, and a data check unit connected to the bit number inverse converter, wherein the control unit includes the bit number inverse converter. The data selection unit is controlled by a logical sum of a detection result of a conversion rule violation in the unit and a data error detection result in the data check unit. Further, the check data is obtained by C
It is characterized by being RC data.

More specifically, a data receiving unit for receiving input data in units of parallel data of a predetermined number of bits and adding a free area to the data, and checking data and adding check data to the free area A check data adding section, a bit number converting section connected to the check data adding section for converting the number of bits, and a P / S converting section connected to the bit number converting section for performing parallel / serial conversion of data. A data transmitter section having first and second data transmission systems; and a serial data receiver for receiving the outputs of the first and second data transmission systems, respectively.
An S / P conversion unit for performing parallel conversion, a bit number inverse conversion unit connected to the S / P conversion unit for inversely converting the number of bits, and connected to the bit number inverse conversion unit to check data with check data. First and second data reception systems each including a data check unit, a data selection unit that selectively outputs output data of the first and second data reception systems, and conversion by the bit number inverse conversion unit. And a control unit that controls the data selection unit based on a logical sum of a detection result of a rule violation and a data error detection result in the data check unit to switch and output normal data. The high-speed data receiver includes first and second data in which check data is added to the same data.
First and second data receiving systems for receiving the first transmission data, a data selector for selectively switching and outputting the output data of the first and second receiving systems, and first and second data reception systems. And a control unit for controlling the data selection unit so as to detect an abnormality of the received data based on the check data added to the data in the system and output a normal output of the data receiving system as the received data.

More specifically, check data is added to the same data, bit number conversion and parallel / serial conversion are performed, and first and second receptions for receiving the transmitted first and second transmission data are performed. High-speed data receiver having a system for receiving each of the first and second transmission data and performing serial / parallel conversion of the data.
A P / P conversion unit, a bit number inverse conversion unit connected to the S / P conversion unit for inversely converting the number of bits, and a data check unit connected to the bit number inverse conversion unit and checking data with check data. First and second data reception systems, a data selection unit for selectively outputting output data of the first and second data reception systems, and a detection result of a conversion rule violation in the bit number inverse conversion unit And a control unit that controls the data selection unit based on the logical sum of the data error detection results in the data check unit to switch and output normal data. (Effect) Check data is added to the transmission data and the data is transmitted twice, and the reception side receives each of the data by the double reception system, checks the error by the bit conversion of the data, and checks the data by the check data. Normal data is used as received data, and the quality of data is improved against sudden bit errors or the like occurring in data transmission.

[0013]

FIG. 1 is a diagram showing a circuit configuration of a transmitter / receiver chip for high-speed data transmission / reception according to one embodiment of the high-speed data transmission / reception system of the present invention. This embodiment includes a data transmitter section and a data receiver section.

In FIG. 1, a data transmitter section 1 has a data receiving section 1A, 1B, and a CRC data section, which comprises a double signal processing system for receiving input data, a frame pulse and a clock, and outputting a transmission signal. Additional parts 2A, 2B,
8B / 10B converters 3A and 3B and P / S units 4A and 4B
And a phase locked loop (PLL) for the clock. The outline of the function of each unit of the data transmission unit is as follows.

The data receiving units 1A and 1B receive the input parallel data in synchronization with the clock and the frame pulse, and output the data as transmission data in 8-bit data units. The CRC data adding units 2A and 2B perform a CRC operation on the transmission data input from the data receiving units 1A and 1B, and add the CRC operation result to the data. 8B
The / 10B converters 3A and 3B convert the 8-bit data into 10-bit data according to the conversion method after adding the CRC data, and insert a start flag indicating the head of the data. The P / S units 5A and 5B convert the parallel data from the multiplexing unit into serial data, and transmit and output the serial data to the data receiver unit 2 side.

Next, the data receiver unit 2 includes an S / P unit 5
A, 5B, 10B / 8B converters 6A, 6B, CRC check sections 7A, 7B, and a data selection section 9. The outline of the function of each unit of the data receiver unit 2 is as follows.

In FIG. 1, S / P units 5A and 5B receive serial data transmitted from data transmitter unit 1, determine a break in byte data with reference to a start flag, and convert the data into parallel data. . The 10B / 8B converters 6A and 6B convert the received 10-bit data into 8-bit data according to the conversion method, and generate a frame pulse generated at the head position of the data by a start flag. If a pattern not included in the conversion code occurs in this process, an error (ERRA,
B) Output a signal. The CRC check units 7A and 7B
It performs a CRC operation on the data received from the data extraction unit A and outputs an ERR signal indicating whether the data is normal / abnormal and data from which the CRC operation data has been removed. (The CRC check unit B performs a CRC operation on the data received from the data extraction unit B, and outputs an ERR signal indicating normal / abnormal data, and a CRC
Outputs the data with the operation data removed. The data selector 9 selects data on the side where no error has occurred from the ERR signals output from the two systems of the A-side circuit and the B-side circuit, and outputs the data. CRC check section 7
If the data in both A and 7B is normal, the data of the system selected at the previous timing is continuously selected and output. CRC check section 7
If the data in both A and 7B is abnormal, a data abnormal signal is output as a data reception error.

(Operation of Embodiment) Next, the operation of each part of FIG. 1 will be described in detail with reference to FIGS. 2 to 8 are diagrams showing the configuration blocks shown in FIG. 1 together with their input / output signals.

First, in the data transmitter 1, 8-bit parallel data is input to the data receivers 1A and 1B, and as shown in FIG.
Two empty areas (time slots) are added after the parallel data 0 to n of the configuration (FIG. 2).

The CRC data adding units 2A and 2B are 8bi
The CRC operation is performed on the t-structured parallel data 0 to n, and the CRC operation result is converted to the 8-bit parallel data 0.
To the vacant time slot after .about.n (FIG. 3).

The 8B / 10B conversion 3A, 3B is 8 bit
10 bits of parallel data according to the conversion code
The data is converted into parallel data having the configuration, and a start flag S indicating the head of the data is inserted (FIG. 4).

The P / S units 4A and 4B convert 10-bit parallel data into serial data (FIG. 5).

Next, in the data receiving section, the S / P sections 5A and 5B determine the break of byte data by inputting the serial data and referring to the start flag being operated, and determine the 10-bit parallel data. (FIG. 6).

The 10B / 8B conversion 6A, 6B is 10 bi
8-bit parallel data of t configuration according to the conversion code
The data is converted into parallel data having the configuration, and a frame pulse is generated at the head position of the data from the start flag. When a pattern not included in the conversion code occurs and an error occurs in a corresponding data portion in each of the 10B / 8B conversions 6A and 6B, a data conversion error signal is output (FIG. 7).

The CRC checks 7A and 7B perform a CRC operation, output the operation result to an ERR signal, and output data from which the CRC data has been removed (FIG. 8).

The data selector 9 determines whether to select the A side data or the B side data based on the data from the A side circuit and the B side circuit and the ERR signal, and selects and outputs the normal data side. I do.

FIG. 9 is a diagram showing an example of occurrence of data abnormality in the reception processing operation in the data receiver unit 2 and an example of a switching operation in the data selection unit 9. In FIG.
At time t1, ERR_A and B are both in a normal state, and immediately before that, the A-side circuit has been selected, and the data selection unit 9 continues to select DATA_A. △
At time t2, ERR_A goes into a fault state and ERR_A
Since B is in a normal state, the data selection unit 9 switches to select DATA_B at the time of Δt2. Similarly, at the time of Δt3, ERR_B becomes a fault state and ER_B
Since R_A is in the normal state, the data selection unit 9
Switch to select A_A. Further, at the time of Δt4, since both ERR_A and ERR_B are in the failure state, the data (OUTDATA) output from the data selection unit 9 is invalid, and the failure signal (OUTERR) is output as the failure state.

Although the above embodiment has been described with reference to an example in which the CRC operation method is adopted as the data check method, an arbitrary method can be adopted as the data check method in the present invention.

FIG. 10 is a diagram showing another embodiment of the high-speed data transmission / reception system of the present invention. This shows an example in which a method of adding check data is adopted as a data check method instead of adopting a data check method of performing a CRC operation. In the present embodiment, the data transmitter 11
Check data adding unit 11 in the receiving unit of input data
A and 11B are provided, and after adding check data to the input data, 8B and 10B conversions 12A and 12B are provided.
The data is output to the data receiver 12 via the B / P / S converters 13A and 13B. In the data receiver section 12, P
10B / 8B conversion 1 via the / S conversion units 14A and 14B
Normal data is detected by checking the check data added in 5A and 15B and the data check 16A and 16B, and the data selecting unit 18 selects and outputs normal data.

[0030]

As described above, the high-speed data transmission / reception system of the present invention employs a double transmission / reception system for data transmission, and adds check data to the data to provide an error detection result. The data is transmitted and received by the normal transmission / reception system accordingly, so even if a data error occurs in one of the transmission / reception systems, the correct data can be transmitted by the other correct transmission / reception system. Can be improved.

The data check function can be enhanced by detecting the data error based on the conversion rule in the conversion / inversion of the number of bits.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a high-speed data transmission / reception system of the present invention.

FIG. 2 is a diagram showing signal processing of a data receiving unit of the embodiment shown in FIG.

FIG. 3 is a diagram illustrating signal processing of a CRC data adding unit according to the embodiment shown in FIG. 1;

FIG. 4 is a diagram illustrating signal processing of an 8B / 10B converter according to the embodiment illustrated in FIG. 1;

FIG. 5 is a diagram showing signal processing of a P / S conversion unit of the embodiment shown in FIG.

FIG. 6 is a diagram illustrating signal processing of an S / P converter according to the embodiment shown in FIG. 1;

FIG. 7 is a diagram illustrating signal processing of a 10B / 8B converter according to the embodiment illustrated in FIG. 1;

FIG. 8 is a diagram showing signal processing of a CRC check unit according to the embodiment shown in FIG.

FIG. 9 is a diagram illustrating signal processing for selecting output data in the data selection unit according to the embodiment shown in FIG. 1;

FIG. 10 is a diagram showing another embodiment of the high-speed data transmission / reception system of the present invention.

FIG. 11 is a diagram showing a conventional data transceiver.

[Explanation of symbols]

1, 11, 31 Data transmitter section 2, 12, 32 Data receiver section 1A, 1B, 41 Data receiving section 2A, 2B CRC data adding section 3A, 3B, 12A, 12B, 428B / 10B conversion section 4A, 4B , 13A, 13B, 43 P / S converter 5A, 5B, 14A, 14B, 44 S / P converter 6A, 6B, 15A, 15B, 45 10B / 8B converter 7A, 7B, CRC checker 8A, 8B, 17A, 17B OR section 9, 18 Data selection section 11A, 11B Check data addition section 16A, 16B Data check section 46 Data transmission section

Claims (6)

[Claims] 1. A data transmitter section having first and second data transmission systems for transmitting check data added to input data, and first and second data transmission systems of the data transmitter section. First and second data receiving systems for respectively receiving the transmission data, a data selecting unit for selectively switching and outputting the output data of the first and second data receiving systems, and first and second data receiving systems. A data receiving unit configured to detect an abnormality in the received data by the check data added to the data in the data receiving system and to control the data selecting unit so as to output a normal output of the receiving system as the received data. And a high-speed data transmission / reception method. 2. The first and second data transmission systems have a check data adding unit and a bit number converting unit for converting the number of bits of data connected to the check data adding unit. And the second data receiving system has a bit number inverse converter for inversely converting the number of bits, and a data check unit connected to the bit number inverse converter, and the control unit includes the bit number inverse converter. 2. The high-speed data transmission / reception system according to claim 1, wherein the data selection unit is controlled by a logical sum of a detection result of a conversion rule violation in the data check unit and a data error detection result in the data check unit. 3. The high-speed data transmission / reception system according to claim 1, wherein the check data is CRC data obtained by a CRC operation. 4. First and second data receiving systems for receiving first and second transmission data to which check data is added to the same data, respectively, and output data of the first and second receiving systems. A data selector for selectively switching and outputting the data, and detecting abnormalities in the received data based on the check data added to the data in the first and second data receiving systems, and using the normal output of the data receiving system as the received data. A control unit that controls the data selection unit to output the data. 5. A data receiving unit for receiving input data in units of a predetermined number of bits of parallel data and adding a free area in said data unit, and adding check data for checking data and adding check data to said free area. And a P / S conversion unit connected to the check data addition unit for converting the number of bits, and a P / S conversion unit connected to the bit number conversion unit for performing parallel / serial conversion of data. A data transmitter having two data transmission systems, an S / P converter for receiving outputs of the first and second data transmission systems and performing serial / parallel conversion of data, and the S / P converter. A number-of-bits inverse conversion section connected to the section for performing an inverse conversion of the number of bits; First and second data receiving systems each including a communication unit, a data selection unit for selectively outputting output data of the first and second data receiving systems, and conversion by the bit number inverse conversion unit. A data receiver unit comprising: a control unit that controls the data selection unit based on a logical sum of a rule violation detection result and a data error detection result in the data check unit to switch and output normal data. High-speed data transmission / reception method. 6. A high-speed system having first and second receiving systems for receiving check data added to the same data, performing bit number conversion and parallel / serial conversion, and receiving the transmitted first and second transmission data, respectively. An S / P converter for receiving the first and second transmission data and performing serial / parallel conversion of the data,
A first and a second bit number conversion unit connected to the S / P conversion unit and configured to perform a bit number reverse conversion, and a data check unit connected to the bit number reverse conversion unit and checking data with check data. A data reception system, a data selection unit for selectively outputting output data of the first and second data reception systems, and a detection result of a conversion rule violation in the bit number inverse conversion unit and the data check unit. And a control unit that controls the data selection unit based on the logical sum of the data error detection results and switches and outputs normal data.