JP2000082090A - Flip-flop circuit with delay function, latch circuit with delay function, designing method for sequence circuit, automatic designing device for clock signal wire of semiconductor integrated circuit, and clock signal wire of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the sequence circuit operate with a short-cycle clock signal. SOLUTION: The flip-flop circuit with a delay function is constituted by using a flip-flop circuit 10 and a delay circuit 20. An external clock signal ECLK is inputted to the delay circuit 20 from outside and an internal clock signal ICLK which is a certain delay time ΔT2 delayed behind ECLK is outputted to the flip-flop circuit 10. Consequently, the internal clock signal ICLK rises with the certain delay time ΔT2 after the external clock signal ECLK rises, so the input of a data input signal DIS to the flip-flop circuit 10 can be delayed by the delay time ΔT2. Consequently, even if the data input signal DIS arrives at the flip-flop circuit with the delay function with a delay of the delay time ΔT2, the flip-flop circuit 10 can inputs the data input signal DIS correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for designing a flip-flop circuit and a sequential circuit. The present invention also relates to an automatic clock signal wiring design apparatus and method in a semiconductor integrated circuit for automatically designing a clock signal wiring in consideration of a data path delay.

[0002]

2. Description of the Related Art FIG. 15 is a diagram showing a general sequential circuit. As can be seen from FIG. 15, the sequential circuit includes a combinational logic circuit LC and a flip-flop circuit FF. Usually, the operation speed of such a sequential circuit is
It is determined by the propagation delay time Tpd of the combinational logic circuit LC. That is, it is determined by the propagation delay time Tpd, which is the time required for a signal to propagate through the combinational logic circuit LC. The propagation delay time Tpd, the setup time Tsu of the flip-flop circuit FF, and the clock cycle T
It is a condition for the sequential circuit to operate properly that ck and the relationship of Tpd + Tsu <Tck are satisfied.

At present, the setup time Tsu of the flip-flop circuit FF is very close to zero, which is about 1 to 5% of the clock cycle Tck. Since the design is performed using only such a flip-flop circuit FF,
The operation speed of the sequential circuit is determined by the propagation delay time Tpd. That is, the operation speed of the sequential circuit is determined by the maximum propagation delay time Tpd of the combinational logic circuit LC located between the flip-flop circuits FF. That is, the critical path determines the operation speed of the sequential circuit.

FIG. 16 is a diagram showing a general sequential circuit and its timing chart. As can be seen from FIG. 16, the timing at which the flip-flop circuit FF outputs a data output signal or the timing at which the flip-flop circuit FF takes in the input data input signal in the semiconductor integrated circuit including the sequential circuit is supplied. The clock signal is synchronized with the rising (or falling) edge timing of the clock signal. In FIG. 16, there are two paths: a path from the flip-flop circuit FF (1) to the flip-flop circuit FF (2) and a path from the flip-flop circuit FF (2) to the flip-flop circuit (3). . That is, the combinational logic circuit LC
There are two paths, the path of (2) and the path of the combinational logic circuit LC (3). In these paths, the value of the propagation delay time Tpd of the combinational logic circuit LC (2) may be large and the value of the propagation delay time Tpd of the combinational logic circuit LC (3) may be small. In such a case, the maximum operating frequency of the clock signal is determined only by the value of the propagation delay time Tpd of the combinational logic circuit LC (2). In such a case, a slack value S indicating a margin for the clock signal is given.
Lack is larger in the combinational logic circuit LC (3) than in the combinational logic circuit LC (2). Therefore, the maximum operating frequency of the clock signal is determined according to the combinational logic circuit LC (2) having a small slack value Slack. Note that the slack value Slack is Slack = Tc.
It can be represented by k-Tsu-Tpd.

[0005]

Here, at the stage of designing such a sequential circuit, the design is performed using a computer or the like using RTL (register transfer level) description. In order to improve the operation speed of the sequential circuit at the stage of designing the sequential circuit, it is necessary to newly insert a separate flip-flop circuit FF into the combinational logic circuit LC corresponding to the critical path. That is, in order to divide the combinational logic circuit LC having the maximum propagation delay time Tpd, it is necessary to manually insert the flip-flop circuit FF into the combinational logic circuit LC. When the flip-flop circuit FF is inserted as described above, there is no alternative to manually correcting the RTL description.

Therefore, the present invention has been made in view of the above problems, and by incorporating a delay circuit in a flip-flop circuit, an internal clock signal is generated after a certain time has elapsed since the rise of the external clock signal. It is an object of the present invention to provide a flip-flop circuit with a delay function that can be started up. It is another object of the present invention to minimize the modification of the RTL description at the design stage of a sequential circuit by using such a flip-flop circuit with a delay function.

In the design stage, the clock signal wiring is designed by automatic wiring or manual wiring. Of these, in automatic wiring, all flip-flop circuits F
The only option is to connect the clock signal to F so that the clock signal is input simultaneously. That is, a clock signal has to be input to all the flip-flop circuits FF at the same timing. On the other hand, if manual wiring is performed, wiring of a clock signal in consideration of data path delay was also possible. That is, it was possible to supply a clock signal at a shifted timing among a plurality of flip-flop circuits FF. However, manual wiring requires a great deal of labor and time for wiring design, and there is a problem that the design efficiency is not very good.

The present invention has been made in view of the above problems, and provides an apparatus and method for automatically designing clock signal wiring in a semiconductor integrated circuit which can automatically perform clock signal wiring in consideration of data path delay. The purpose is to do.

[0009]

In order to solve the above problems, a flip-flop circuit with a delay function according to the present invention comprises:
A data input signal and an internal clock signal are input, a data holding output circuit that holds the value of the data output signal in synchronization with the internal clock signal and outputs the data output signal as a data output signal, and an external clock signal. A delay circuit that outputs an internal clock signal having a fixed delay time with respect to the input external clock signal.

Further, the data holding output circuit is constituted by a flip-flop circuit which receives and holds the data input signal when the internal clock signal rises, and outputs the data input signal as the data output signal. And

The data holding and output circuit captures the data input signal while the internal clock signal is at a high level and outputs the data input signal as the data output signal, and outputs a high level while the internal clock signal is at a low level. The latch circuit, which holds the data input signal captured during and outputs as the data output signal, is input with an internal clock signal output from the delay circuit, and is synchronized with the rise of the internal clock signal. Outputting a short pulse signal to the latch circuit, a pulse signal generation circuit,
It is characterized by comprising.

Further, a semiconductor integrated circuit device according to the present invention includes the flip-flop circuit with a delay function described above.

Further, in the semiconductor integrated circuit device, a plurality of the flip-flop circuits with a delay function are provided, and at least one of the plurality of flip-flop circuits with a delay function is another flip-flop with a delay function. A delay time different from that of the circuit.

Further, the semiconductor integrated circuit device is characterized in that it is designed by registering the above-mentioned flip-flop circuit with a delay function as a library and then performing logic synthesis.

On the other hand, the latch circuit with a delay function according to the present invention takes in a data input signal while the internal clock signal is at a high level and outputs it as a data output signal. A latch circuit that holds the data input signal captured between levels and outputs the latched data input signal as a data output signal; and an external clock signal that is input and has a fixed delay time with respect to the input external clock signal. A delay circuit that outputs the internal clock signal.

A method for designing a sequential circuit according to the present invention is a method for designing a sequential circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits connecting the combinational logic circuits. Performing logic synthesis using a library of flip-flop circuits, and performing timing analysis based on the logic synthesis, and when operating with a clock signal of a desired speed, the output signal of the combinational logic circuit is A step of obtaining a non-arrival time with respect to the signal, and replacing the library used in the logic synthesis with a library to which a flip-flop circuit having a built-in delay circuit having a delay time corresponding to the non-arrival time is added. And a step of performing the following.

Further, a library of flip-flop circuits including a plurality of delay circuits having different delay times is provided, and a flip-flop circuit at a subsequent stage of the combinational logic circuit in which the unattained time has occurred is provided with a delay circuit. When replacing with the flip-flop circuit described above, a flip-flop circuit having a delay time longer than the unreached time and having the shortest delay time is used.

According to another aspect of the present invention, there is provided an automatic clock signal wiring designing apparatus comprising: a plurality of combinational logic circuits; and a plurality of flip-flop circuits provided between the combinational logic circuits. An automatic design apparatus for signal wiring, wherein a clock signal is set at a predetermined cycle time, a path where the flip-flop circuit is a start point or an end point is analyzed for all flip-flop circuits, and each flip-flop circuit is analyzed. For obtaining the worst slack value, a path analysis means and a path having the worst slack value among all the flip-flop circuits are obtained as a worst path, and an output signal from the worst combinational logic circuit constituting the worst path is obtained. Whether the timing is in time for the timing of the clock signal in the worst path A first condition judging means for judging whether the timing of the output signal from the worst combinational logic circuit is in time for the timing of the clock signal of the worst path. The cycle time resetting means for setting the cycle time of the clock signal even shorter, and the first condition determining means, wherein the timing of the output signal from the worst combinational logic circuit is the clock of the worst path. If the timing of the signal is not in time, the supply timing of the clock signal is adjusted in at least one of the flip-flop circuit at the preceding stage and the flip-flop circuit at the subsequent stage of the worst combination logic circuit, and the worst combination logic is adjusted. The output signal from the logic circuit is in time For the,
And clock signal arrival time setting means.

In the clock signal arrival time setting means, the clock signal arrival time provided to the flip-flop circuit is not fixed and can be made earlier or later, and the clock signal arrival time is made earlier. It is characterized in that the supply timing of the clock signal is adjusted based on three attributes: a pre-fix which cannot be performed, and a post-fix which cannot delay the arrival time of the clock signal.

Further, after the arrival time of the clock signal is set, it is determined whether or not the supply timing of the clock signal can be adjusted so that the output signal from the worst combinational logic circuit can be made in time. And a cycle time resetting means for setting the cycle time of the clock signal to be longer if the supply timing cannot be adjusted.

When the supply timing of the clock signal can be adjusted by the second condition judging means, the non-fixed and the pre-fixed are applied to the flip-flop circuits before and after the worst combinational logic circuit. And the required attributes of the post-fixing are changed, and the path analyzing means is executed again.

Further, after resetting the cycle time, the currently set cycle time is compared with the previously set cycle time. If the difference is within a predetermined value, the best cycle time is set. Is further provided with an end determination unit for determining that is obtained.

According to the automatic clock signal wiring design method of the present invention, a semiconductor integrated circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits provided between the combinational logic circuits is provided. The clock signal wiring is set at a predetermined cycle time, and a path where the flip-flop circuit is a start point or an end point is analyzed with respect to all flip-flop circuits. A path analysis step of obtaining the worst slack value for each circuit, a path having the worst slack value among all flip-flop circuits is obtained as a worst path, and an output signal from a worst combinational logic circuit constituting the worst path is obtained. Whether the timing is in time for the timing of the clock signal in the worst path Determining whether the timing of the output signal from the worst combinational logic circuit is in time with the timing of the clock signal of the worst path in the first condition determining step and the first condition determining. In the cycle time resetting step of setting the cycle time of the signal even shorter, and in the first condition determination, the timing of the output signal from the worst combinational logic circuit is not in time for the timing of the clock signal of the worst path. In the case, the supply timing of the clock signal in at least one of the flip-flop circuit at the preceding stage and the flip-flop circuit at the subsequent stage of the worst combinational logic circuit is adjusted,
Setting an arrival time of a clock signal so that an output signal from the worst combinational logic circuit can be made in time.

Further, in the clock signal arrival time setting step, the clock signal arrival time applied to the flip-flop circuit is not fixed and can be advanced or delayed, and the clock signal arrival time is advanced. It is characterized in that the supply timing of the clock signal is adjusted based on three attributes: a pre-fix which cannot be performed, and a post-fix which cannot delay the arrival time of the clock signal.

Further, after the clock signal arrival time setting step, it is determined whether or not the supply timing of the clock signal has been adjusted so that the output signal from the worst combinational logic circuit can be made in time. A condition determining step is further provided, and if the supply timing cannot be adjusted, the cycle time of the clock signal is set to be longer in the cycle time resetting step.

Further, when the supply timing of the clock signal can be adjusted in the second condition judging step, the non-fixed and the pre-fixed are applied to the flip-flop circuits before and after the worst combinational logic circuit. And the required attributes of the post-fixing are changed, and the path analysis step is performed again.

After the cycle time resetting step, the currently set cycle time is compared with the previously set cycle time, and if the difference is within a predetermined value, the best cycle time is determined. The method further comprises an end determination step of determining that a time has been obtained.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] In a first embodiment of the present invention, the timing of a clock signal supplied to only a specific flip-flop circuit is changed by changing the timing of a clock signal supplied to another flip-flop circuit. By delaying the timing, the clock cycle of only a specific flip-flop circuit can be apparently lengthened. Thus, the sequential circuit can be operated with a high frequency clock signal. This will be described in more detail below.

FIG. 1 is a block diagram showing the configuration of a flip-flop circuit with a delay function according to this embodiment. As can be seen from FIG. 1, the flip-flop circuit with a delay function according to the present embodiment includes a flip-flop circuit 10 and a delay circuit 20.

An input terminal D of the flip-flop circuit 10 receives an external data input signal DIS. The internal clock signal ICLK from the delay circuit 20 is input to the clock terminal of the flip-flop circuit 10. Data output signal DOS is output to the outside from output terminal Q of flip-flop circuit 10 in synchronization with internal clock signal ICLK.

The delay circuit 20 receives an external clock signal ECLK from the outside and outputs the above-mentioned internal clock signal ICLK. This internal clock signal ICLK
Is a signal delayed by a certain time from the external clock signal ECLK.

Next, the operation of the flip-flop circuit with a delay function according to the first embodiment will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the flip-flop circuit with a delay function according to the first embodiment.

As can be seen from FIG. 2, it is assumed that external clock signal ECLK switches from low to high at time t1. However, the internal clock signal ICLK is
Due to the action of 0, it remains low at time t1. Next, it is assumed that the input data signal DIS switches from low to high at time t2. That is, since the propagation delay time Tpd of the combinational logic circuit provided in the preceding stage of the flip-flop circuit with the delay function is large, the data input signal DIS rises by ΔT1 behind the rising time t1 of the external clock signal ECLK. I do.

Subsequently, at time t3, the internal clock signal IC
LK switches from low to high. That is, due to the operation of the delay circuit 20, the external clock signal ECLK is more
The internal clock signal ICLK rises with a delay of T2. In synchronization with this internal clock signal ICLK, the flip-flop circuit 10 takes in the data input signal DIS and outputs it as a data output signal DOS. For this reason,
At time t3, the data output signal DOS switches from low to high. That is, the data input signal DIS whose arrival has been delayed by ΔT1 due to the large propagation delay time Tpd of the preceding combinational logic circuit is supplied to the flip-flop circuit 10.
And can be output as a data output signal DOS.

FIG. 3 is a diagram showing an example of a specific circuit configuration of the flip-flop circuit with a delay function according to the present embodiment.

As can be seen from FIG. 3, the delay circuit 20
Is provided with a plurality of inverters 20a connected in series. In the present embodiment, the delay circuit 20 is provided with an even number of inverters 20a. The output of the delay circuit 20 is connected to an inverter 30a, which outputs an inverted internal clock signal / ICLK. The output of inverter 30a is connected to inverter 30b, and internal clock signal ICLK is output from inverter 30b.

The flip-flop circuit 10 includes a clocked inverter 10a and an inverter 1 connected in series.
0b, transfer gate 10c and inverter 10d
And an inverter 10e. Further, the flip-flop circuit 10 includes an inverter 10
clocked inverter 10f connected in parallel with b
And a clocked inverter 10g connected in parallel with the inverter 10d. The data input signal DI is supplied to the clocked inverter 10a.
S is input, and the data output signal D is output from the inverter 10e.
The OS is output.

As described above, according to the flip-flop circuit with a delay function according to the present embodiment, the external clock signal E
Since the internal clock signal ICLK rises after a certain delay time ΔT2 after the rise of CLK, the fetch of the data input signal DIS in the flip-flop circuit 10 can be delayed by the delay time ΔT2. That is, the setup time Tsu can have an apparently negative value. Therefore, even if the data input signal DIS arrives at the delay function flip-flop circuit later by the delay time ΔT2, the flip-flop circuit 10 can correctly capture the data input signal DIS. Therefore, this flip-flop circuit with a delay function is connected to an external clock signal EC having a short cycle.
LK can be operated.

In the first embodiment, the case where the present invention is applied to the flip-flop circuit 10 has been described as an example. However, as can be seen from FIG. 4, the present invention can be applied to the latch circuit 11 which requires a clock signal, similarly to the flip-flop circuit 10. That is, the present invention can be applied to any data holding output circuit such as the flip-flop circuit 10 or the latch circuit 11 which holds the data input signal DIS in synchronization with the clock signal and outputs it as the data output signal DOS. Can be.

[Second Embodiment] In a second embodiment of the present invention, a latch circuit and a pulse signal generation circuit are provided instead of the flip-flop circuit in the first embodiment, so that the area occupied by the semiconductor integrated circuit can be reduced. It is intended.

FIG. 5 is a block diagram showing a configuration of a flip-flop circuit with a delay function according to the second embodiment.

As can be seen from FIG. 5, the flip-flop circuit with a delay function according to the second embodiment includes a latch circuit 40, a pulse generation circuit 42, and a delay circuit 20. In the present embodiment, the flip-flop operation is realized by the latch circuit 40 and the pulse generation circuit 42.

The delay circuit 20 outputs the input external clock signal ECLK as an internal clock signal ICLK after a certain delay time, as in the first embodiment. This internal clock signal ICLK is input to the pulse signal generation circuit 42.

The pulse signal generating circuit 42 generates a pulse signal PS having a short pulse width in synchronization with the rise of the internal clock signal ICLK. That is, the pulse signal PS having a short high-level time is generated. This pulse signal PS is input to the latch circuit 40.

The pulse signal PS is supplied to the latch circuit 40.
In addition, a data input signal DIS is input, and a data output signal DOS is output. This latch circuit 40
While the pulse signal PS is high, the value of the data input signal DIS is fetched and output as the data output signal DOS, and while the pulse signal PS is low, the value of the data input signal DIS at the time of falling of the pulse signal PS is held. And outputs it as a data output signal DOS.

Next, the operation of the flip-flop circuit with a delay function according to the second embodiment will be described with reference to FIG. FIG. 6 is a timing chart illustrating the operation of the flip-flop circuit with a delay function according to the second embodiment.

As can be seen from FIG. 6, it is assumed that external clock signal ECLK switches from low to high at time t1. However, the internal clock signal ICLK is
Due to the action of 0, it remains low at time t1. Therefore, the pulse signal PS also remains low at the time t1. Next, it is assumed that the input data signal DIS switches from low to high at time t2. That is, since the propagation delay time Tpd of the combinational logic circuit provided in the preceding stage of the flip-flop circuit with the delay function is large, the data input signal DIS rises by ΔT1 behind the rising time t1 of the external clock signal ECLK. I do.

Subsequently, at time t3, the internal clock signal IC
LK switches from low to high. That is, due to the operation of the delay circuit 20, the external clock signal ECLK is more
The internal clock signal ICLK rises with a delay of T2. The pulse signal PS switches from low to high in synchronization with the internal clock signal ICLK. Since the pulse signal PS becomes high, the latch circuit 40 takes in the data input signal DIS and outputs it as the data output signal DOS. Therefore, at time t3, the data output signal DOS switches from low to high. That is, the data input signal DIS whose arrival has been delayed by ΔT1 due to the large propagation delay time Tpd of the preceding combinational logic circuit can be captured by the latch circuit 40 and output as the data output signal DOS. Subsequently, at time t4, the pulse signal PS switches from high to low. That is, the pulse signal PS is provided only for a short time from time t3 to time t4.
Is output.

FIG. 7 is a diagram showing an example of a specific circuit configuration of the flip-flop circuit with a delay function according to the present embodiment.

As can be seen from FIG. 7, the delay circuit 20
Is configured by connecting an even number of inverters 20a in series, as in the first embodiment described above. The internal clock signal ICLK output from the delay circuit 20 is
Inverter 42a of pulse signal generating circuit 42 and NAND
The signal is input to the circuit 42b. An odd number of inverters 42a are provided and connected in series. The final output of the inverter 42a is also connected to the NAND circuit 42b. That is, the internal clock signal ICLK
And the final output of the inverter 42a are the NAND circuit 4
2b. NAND circuit 42b outputs inverted pulse signal / PS. This inverted pulse signal / P
S is input to the inverter 42c, and this inverter 42c
The pulse signal PS is output from c. The pulse signal PS and the inverted pulse signal / PS are input to the latch circuit 40.

The latch circuit 40 includes a clocked inverter 40a and an inverter 40b connected in series. Further, the latch circuit 40 includes a clocked inverter 40c connected in parallel with the inverter 40b. Data input signal DIS is input to clocked inverter 40a, and data output signal DOS is output from inverter 40b.

As described above, according to the flip-flop circuit with a delay function according to the present embodiment, the pulse signal generation circuit 4
Since the flip-flop operation is performed by the latch circuit 2 and the latch circuit 40, the area occupied by the semiconductor integrated circuit can be reduced. That is, as in the first embodiment described above, the delay circuit 20 and the normal flip-flop circuit 1
When 0 is combined to form a flip-flop circuit with a delay function having a negative setup time, the area and power consumption are larger than that of the normal flip-flop circuit 10 as a matter of course. In contrast, in the present embodiment,
To compensate for this drawback, the delay circuit 20, the pulse signal generation circuit 42, and the latch circuit 40 constitute a flip-flop circuit with a delay function having a negative setup time. It can be about 2/3 of the form. That is, since the normal flip-flop circuit 10 includes the master latch circuit and the slave latch circuit, the latch circuit 40 can be realized with an area that is about half the area of the flip-flop circuit 10. By placing the delay circuit 20 and the pulse signal generation circuit 42 in the reduced portion, a flip-flop circuit with a delay function can be realized with a smaller area.

[Third Embodiment] The third embodiment relates to a design method using the flip-flops with a delay function according to the above-described first and second embodiments, and includes a plurality of delay functions having greatly different setup times. This is to prepare a flip-flop circuit with a library as a design.

One sequential circuit includes a plurality of combinational logic circuits. Therefore, some of the delay times of the combinational logic circuits constituting the sequential circuit are large and others are small. In the design stage of a sequential circuit, the one having the longest delay time is generally called a critical path and determines the operation cycle of the sequential circuit. That is, the highest clock signal frequency is determined by the critical path. If the operation cycle does not reach the target value,
The combinational logic circuit in the critical path portion is forced to change. Specifically, it is necessary to insert a flip-flop circuit into the combinational logic circuit in the critical path portion to divide this combinational logic circuit. Such a change is usually dealt with by changing the RTL description.

However, by using the flip-flop circuits with delay functions according to the first and second embodiments, the operation cycle can be shortened without changing the combinational logic circuit of the critical path. That is, a flip-flop circuit with a delay function having the delay circuit 20 for the unreached time Td to be shortened among the delay times of the combinational logic circuit of the critical path may be used at the subsequent stage of the combinational logic circuit. That is, the flip-flop to which the signal of the critical path is input may be changed.

For example, the combinational logic circuit L in FIG.
Since the propagation delay time Tpd of C (2) is large, the combinational logic circuit LC (2) lags behind the clock signal by Td.
Output signal reaches the flip-flop circuit FF (2). That is, it is assumed that the unreached time is Td.
In this case, the flip-flop circuit FF (2) at the subsequent stage of the combinational logic circuit LC (2) is replaced with a flip-flop circuit with a delay function having a delay corresponding to the non-arrival time Td, so that the flip-flop circuit FF (2) Can capture the output signal of the correct combinational logic circuit.

In addition, there may be other paths of the combinational logic circuit which actually have a shorter delay time than the critical path, but do not satisfy the target value of the operation period. In order to correspond to the paths of these combinational logic circuits, it is desirable to prepare a flip-flop circuit with a delay function having a delay time shorter than the non-arrival time Td of the critical path. That is, it is desirable to prepare a plurality of flip-flop circuits with delay functions having various delay times.
In this way, the flip-flop circuits with delay functions having different delay times are registered in a library, and logic synthesis is performed again.

FIG. 8 is a flowchart showing the flow of this design. That is, first, RTL description is performed for the designed sequential circuit (S1). Subsequently, logic synthesis is performed by the logic synthesis device based on the RTL description (S2). Next, a gate level description is performed based on the result of the logic synthesis (S3). Then, a critical path analysis for detecting a critical path is performed based on the gate level description (S4). Next, a non-arrival time Td with respect to the operation cycle of the clock signal in the critical path is obtained (S5). In this case, there may be a combinational logic circuit which is delayed from the operation cycle of the clock signal other than the critical path. In such a case, the unreached time is also determined at the same time.

Next, the setup time Ts of -Td to 0
The logic synthesis is performed again using the library of the flip-flop circuit with the delay function u (S6). In other words, the flip-flop circuit at the subsequent stage of the combinational logic circuit on the critical path is replaced with a flip-flop circuit with a delay function having a delay time corresponding to the non-arrival time Td on the critical path. Further, in the combinational logic circuits in the other paths, the flip-flop circuit at the subsequent stage of the path having the non-arrival time is replaced with a flip-flop circuit with a delay function having a delay time corresponding to the non-arrival time. As a result, a gate level description that satisfies the operation cycle of the desired clock signal is obtained (S7).

When there are many paths that do not satisfy the target value of the operation period, the maximum delay time of the flip-flop circuit with a delay function to be replaced may be made longer than the non-arrival time Td of the critical path.

Further, since the flip-flop circuit with the delay function has a large positive hold time instead of having the negative setup time Tsu, a hold violation is likely to occur. FIG. 9 is a diagram for explaining a process in which the hold violation occurs. As can be seen from FIG. 9, in this example, the propagation delay time Tpd of the combinational logic circuit LC (4)
Therefore, a flip-flop circuit with a delay function having a delay time ΔT2 is used for the flip-flop circuit FF (6). Therefore, the output signal itself of the combinational logic circuit LC (4) can be received by the flip-flop circuit FF (6) even through the AND circuit 50. However, when the propagation delay time Tpd of the combinational logic circuit LC (5) is not so large, the output signal of the combinational logic circuit LC (5) becomes high before the flip-flop circuit FF (6) takes in the output signal of the AND circuit 50. It is conceivable that the clock signal changes in synchronization with the rise of the clock signal at the next timing. This is a hold violation.
Therefore, in order to prevent such a hold violation from occurring, the delay time generation circuit 52 having a small area and a large delay time is combined with the combinational logic circuit LC (5) and the AND circuit 50.
Need to be inserted between them. For this purpose, it is necessary to register the delay time generation circuit 52 in a library.

As described above, according to the method of designing a sequential circuit according to the present embodiment, even if an unreached time occurs in a combinational logic circuit, it can be dealt with without changing the RTL description. That is, a correct operation can be ensured only by replacing the flip-flop circuit in which the unreached time occurs with a flip-flop circuit with a delay function.
Therefore, there is no need to change the RTL description, and efficient design work can be performed.

Although the setup times Tsu of the flip-flop circuits registered in the library are different at present, they have other characteristics (eg, driving force).
Has occurred incidentally (as a side effect) as a result of changing. On the other hand, in the present invention, only the setup time Tsu is positively changed while maintaining characteristics other than the setup time Tsu of the flip-flop circuit, which is essentially different.

As a result, by partially using the flip-flop circuit having a negative setup time Tsu, the propagation delay time T.sub.
Even with pd, the relational expression of Tpd + Tsu <Tck can be satisfied. Negative setup time Ts is applied to the flip-flop circuit forming the critical path.
By using the flip-flop circuit with a delay function having u, the operation speed of the entire sequential circuit can be improved. This can be performed without changing the insertion position of the flip-flop circuit, and there is no need to change the RTL description. Further, since the clock signal is delayed inside the flip-flop circuit, it is not necessary to modify the clock distribution mechanism, and the delay can be accurately provided.

[Fourth Embodiment] In a fourth embodiment of the present invention, the timing of a clock signal supplied to all flip-flop circuits in a semiconductor integrated circuit forming a sequential circuit is determined by using the path of each combinational logic circuit. Thus, the maximum operating frequency is intended to be improved by performing control in consideration of the delay of the above. Then, it is an object to provide an algorithm for automatically determining the supply timing of such a clock signal and wiring the clock signal.
This will be described in more detail below.

FIG. 10 is a flow chart for explaining the automatic clock routing algorithm according to the present embodiment. Hereinafter, the algorithm will be described with reference to FIG.

<Prerequisites> First, before starting the description of the flowchart, prerequisite matters will be described.

(1) Clock of current cycle time
Time A. That is, the time of one clock cycle when the current operating frequency of the clock signal is used is defined as Clock TimeA.

(2) The previous cycle time is set to Clock.
TimeB. That is, the time of one clock cycle when the operating frequency of the previous clock signal is used is defined as Clock TimeB.

(3) Clock the new cycle time
TimeN. That is, the time of one clock cycle when the operating frequency of the new clock signal is used is defined as Clock TimeN.

(4) The minimum transition value for convergence determination is Delta
Convg. That is, the current cycle time Clock Time A and the previous cycle time Cl
The absolute value of the difference from ock TimeB is Delta C
If onvg or less, it is determined that the best cycle time has been determined.

(5) Clock A
drive Time. That is, the time at which the clock signal arrives at the flip-flop circuit is represented by Clock.
Arrival Time.

(6) As the types of start and end points, a flip-flop circuit, an input port for inputting a signal from another semiconductor chip to this sequential circuit, and a signal for outputting a signal from this sequential circuit to another semiconductor chip. And an input / output port for inputting / outputting a signal to / from another semiconductor chip are considered. The start and end points are distinguished by using three types of attributes: front fixed, rear fixed, and non-fixed. That is, the clock arrival time Clo of the flip-flop circuit or the like
If it is not possible to make the ck_Arrived_Time earlier than this, an attribute of “fixed before” is given.
Clock arrival time Clock of flip-flop circuit etc.
If the Arrival Time cannot be delayed any further, an attribute of post-fix is given. Clock arrival time Clock A of flip-flop circuit etc.
When the live Time can be advanced or delayed, an attribute of non-fixed is given. Of these, the front fixed and the rear fixed may be given to one flip-flop circuit or the like in an overlapping manner. Clock arrival time of input port Clock Arrival Time
Cannot be advanced because it is an input from another semiconductor chip. Therefore, the input port is given a pre-fixed attribute. The clock arrival time Clock Output Time of the output port cannot be delayed because it is an output to another semiconductor chip.
Therefore, a post-fixed attribute is assigned to the output port. Clock Arrival Time of Input / Output Port Clock Ar
Since the liveTime is an input / output with another semiconductor chip, it cannot be made faster or slower. Therefore, the front and rear fixed attributes are assigned to the input / output ports. Although the clock arrival time Clock Arrival Time of the flip-flop circuit can be made earlier or later at first, in this process, the clock arrival time Clock Arrival Time to another flip-flop circuit is obtained.
Can not be advanced or delayed. Therefore,
The flip-flop circuit is given an attribute of fixed before, fixed after, and not fixed. Table 1 summarizes the meanings of these pre-fixed, post-fixed, and non-fixed attributes.

[0074]

[Table 1] (7) Prepare a list of flip-flop circuits. Table 2 shows this list.

[0075]

[Table 2] The items in the list of the flip-flop circuit are (a)
(B) attribute of the target flip-flop circuit, (c) arrival time of the clock signal to the target flip-flop circuit,
(D) the name of the start point of the path that is the worst slack when the target flip-flop circuit is the end point; (e) the slack value Slack of the path; (f) the worst case when the target flip-flop circuit is the start point. (G) Slack value Sla of the path that becomes a slack
ck. Here, the target flip-flop circuit refers to a flip-flop circuit of interest in a certain path. In Table 2, it is assumed that there are three flip-flop circuits.

(8) Among the paths in the flip-flop circuit list shown in Table 2, the path having the worst slack value Slack is called the worst path. That is, the path having the smallest slack value Slack is referred to as the worst path. Further, the combinational logic circuit forming the worst path is referred to as a worst combinational logic circuit.

<Initial Setting (S11)> The initial value of the current cycle time Clock Time A and the minimum transition value D
Set the initial value of delta Convg. A feasible cycle time is set as the initial value of the current cycle time ClockTimeA. All flip-flop circuits are extracted from the nets constituting the sequential circuit, and (a) the name of the target flip-flop circuit is entered in the items of the flip-flop circuit list shown in Table 2. Initially, among the items in the flip-flop circuit list table, (b) the attributes of the target flip-flop circuit are all set to non-fixed. Among the items in the flip-flop circuit list table, (c) the arrival times of the clock signal to the target flip-flop circuit are all set to “0”. Then, Table 2 is completed.

<Path Analysis (S12)> For all flip-flop circuits, the path where the flip-flop circuit is the start point or the end point is analyzed, and the clock arrival time C
The worst slack value Slack in consideration of the lock drive time is listed for each flip-flop circuit. As a result of this path analysis, as shown in Table 3, in the list of flip-flop circuits, (d) the start point name of the path having the worst slack value Slack when the target flip-flop circuit is the end point, and (e) The slack value Slack of the path, (f) the end point name of the path having the worst slack value Slack when the target flip-flop circuit is set as the starting point, and (g) the slack value Slack of the path are filled. That is, the items (d), (e), (f), and (g) are filled.

[0079]

[Table 3] <Condition determination 1 (S13)> Slack value S of worst path
If luck is positive (Positive), it is determined that the result is OK, and if negative (Negative), NG is determined. That is, the slack value Slac of the worst path
If k is positive, the slack value Sla for all passes
ck is positive and its current Clock Time
At A, this sequential circuit operates normally. In Table 3,
The worst path is a case where the flip-flop circuit REG1 is the end point and the flip-flop circuit REG3 is the start point, and the slack value Slack is −2.4.

<Change of cycle time (S14)> If slack value Slack is positive in condition determination 1, the cycle time is changed. If this processing block is reached from the condition determination 1, Clock
Change to TimeN = (Clock TimeA) / 2. That is, the current cycle time Clock T
One half of imageA is replaced by the new cycle time Clock.
Set to TimeN.

On the other hand, when the processing block is reached from Condition Determination 2 described later, ClockTimeN = (Clo
ck TimeA + Clock TimeB) / 2. That is, a cycle time intermediate between the cycle time Clock Time B before the sequential circuit normally operates and the current cycle time Clock Time A where the sequential circuit could not normally operate is set to a new cycle time. Time Clock
Set to TimeN.

Clock TimeB = Clock TimeA regardless of whether the processing block comes from the condition judgment 1 or this processing block from the condition judgment 2.
(However, this process is not executed when the condition determination 2 is reached), Clock Time A = Clock Time
eN is executed in order to update the cycle time. That is, the current cycle time Clock Time A is
The previous cycle time Clock TimeB is set (however, this process is not executed when the condition determination 2 comes), and the new cycle time Clock TimeN
Is the current cycle time Clock TimeA. Further, the flip-flop circuit list table is reset. That is, a list of the flip-flop circuits shown in Table 2 is prepared.

<End Determination (S15)> In this end determination, it is determined whether or not the cycle time of the clock signal has converged to some extent. Specifically, condition determination 1 (S13)
Is OK and the previous cycle time Clock
TimeB and current cycle time Clock Ti
The absolute error of meA is the minimum transition value Delta Convg
If it is smaller, it is OK, otherwise it is NG. That is, the current cycle time Clock TimeA
This circuit operates normally, and the current cycle time ClockTimeA and the previous cycle time C
If the difference from the lock TimeB converges within a certain range, it is determined that the best cycle time has been obtained.

<Clock Signal Wiring Processing (S16)> Clock signal wiring processing is performed using a flip-flop circuit list table so that the clock arrival time ClockArriv Time satisfies the conditions of this list table. Specifically, among all the flip-flop circuits, the minimum clock arrival time Clock Arrive
The clock signal is wired from the flip-flop circuit having Time. The wiring of the clock signal is performed in this manner, and the clock arrival time Clock Arrive
In the case where a flip-flop circuit wired beyond the Time occurs, the excess is added to the clock arrival time Clock Arrival Time of all the flip-flop circuits, and wiring is performed again from the beginning. By repeating this process, the clock arrival time Clock
The Arrival Time relatively matches the list table.

<Setting of Arrival Time of Clock Signal (S17)
> Slack value Sl of worst path in condition determination 1 described above
If ack is negative, the process of setting the arrival time of the clock signal is performed. Here, the timing of the clock signal between the start-point flip-flop circuit and the end-point flip-flop circuit in the worst path is changed using the flip-flop circuit list table. The changing method differs depending on the type of attribute given to the flip-flop circuit at the start and end points. Specifically, there are the following three types of change methods. Note that the slack value of the worst path is Sl
ack A.

(1) When the timing of the flip-flop circuit at the start and end points can be changed The list of flip-flop circuits in this case is as shown in Table 3, and the state is shown in FIG. When the timing of the start and end points can be changed, the clock arrival time Clock A of the flip-flop circuit at the start point
drive time is increased by | Slack A / 2 |, and the clock arrival time Clock Arrival Time of the flip-flop circuit at the end point is set to | Slack.
A / 2 | For example, in the case of a list of flip-flop circuits as shown in Table 3, the worst path is from the flip-flop circuit REG3 to the flip-flop circuit RE.
It is a path to G1 and Slack A is -2.4.
The flip-flop circuit REG3, which is the start point of the worst path, is also connected to the flip-flop circuit REG1, which is the end point.
Are also non-fixed. Therefore, the clock arrival time Clock Arri of the flip-flop circuit REG1
ve Time = (1.2− (| −2.4 / 2 |)) =
0.0. That is, the clock arrival time Clock Arrive of the flip-flop circuit REG1 which is the end point
e Delay Time by 1.2. Further, the clock arrival time Clock A of the flip-flop circuit REG3
drive Time = (− 0.9+ (| −2.4 / 2)
|)) = 0.3. That is, the clock arrival time Clock A of the flip-flop circuit REG3 which is the starting point
Increase the drive time by 1.2. Thereby, the slack value Slack of the worst path of the flip-flop circuits REG3 to REG1 can be set to 0.

(2) When Only the Flip-Flop Circuit at the Start Point Can Change the Timing The list of flip-flop circuits in this case is as shown in Table 4, and the state is shown in FIG. If only the start-point flip-flop circuit can change the timing, the clock arrival time Clock Arrival Time of the start-point flip-flop circuit is set to | S
rack A | For example, in the case of a list of flip-flop circuits as shown in Table 4, the worst path is a path from the flip-flop circuit REG3 to the flip-flop circuit REG1, and the attribute of the flip-flop circuit REG1, which is the end point, is post-fixed. Therefore, the clock arrival time Cloc of the flip-flop circuit REG1
k Alive Time cannot be delayed any further. Therefore, this flip-flop circuit RE
G1 is not changed, and the clock arrival time of the flip-flop circuit REG3 is set to Clock Arrival Time =
(−0.9+ | −2.4 |) = 1.5 is changed. That is, the clock arrival time Clock Arrival Time of the flip-flop circuit REG3, which is the starting point, is set to 1.
Make it 2 faster. Thereby, the flip-flop circuit RE
The slack value Slack of the worst path of the flip-flop circuit REG1 can be set to 0 from G3.

[0088]

[Table 4] (3) When Only the Flip-Flop Circuit at the End Point Can Change the Timing In this case, the list of flip-flop circuits is as shown in Table 5, and the state is shown in FIG. When only the end-point flip-flop circuit can change the timing, the clock arrival time Clock Arrival Time of the end-point flip-flop circuit is set to | Sl.
ack A | For example, in the case of the flip-flop circuit list table as shown in Table 5, the worst path is a path from the flip-flop circuit REG3 to the flip-flop circuit REG1, and the attribute of the flip-flop circuit REG3, which is the starting point, is fixed at the front. Therefore, the clock arrival time Clock of the flip-flop circuit REG3
The Arrival Time cannot be advanced. Therefore, without changing the flip-flop circuit REG3, the clock arrival time of the flip-flop circuit REG1 is set to Clock Arrival Time = (1.2+ |
−2.4 |) = 3.6. Thereby, the slack value Slack of the worst path of the flip-flop circuits REG3 to REG1 can be set to 0.

[0089]

[Table 5] (4) In the case where the timing of both the flip-flop circuits at the start and end points cannot be changed, the list of flip-flop circuits in this case is as shown in Table 6, and the state is shown in FIG. If the timing of both the start flip-flop circuit and the end flip-flop circuit cannot be changed, nothing is performed. That is, since the flip-flop circuit REG3 as the start point is fixed at the front and the flip-flop circuit REG1 as the end point is fixed at the rear, it is no longer possible to adjust the timing of the clock signal in accordance with the worst path. In other words, the slack value Slack of the worst path cannot be set to 0.

[0090]

[Table 6] <Condition Judgment 2 (S18)> In the process of setting the arrival time of the clock signal (S17), (4) NG if both the flip-flop circuits at the start and end points cannot change the timing
Otherwise, it is OK. That is,
(4) If the timing of both the flip-flop circuits at the start and end points cannot be changed, the supply timing of the clock signal to the flip-flop circuit is set to the current cycle time C.
In lock Time A, the adjustment cannot be completed, so that the process of changing the cycle time (S14) is performed. On the other hand, (1) when the timing of the start-end flip-flop circuit can be changed, (2) when only the start-point flip-flop circuit can change the timing, and
(3) If the timing of only the end flip-flop circuit can be changed, there is a possibility that the timing of supplying the clock signal to the flip-flop circuit can be adjusted, so the current cycle time Clock Time
The process at A is continued (S19).

<Set attributes of start and end points (S19)> Here, the processing result of the above-described clock signal arrival time setting (S17) is reflected in the list of flip-flop circuits. Specifically, (2) when a process is performed in which only the flip-flop circuit at the start point can change the timing, a post-fixed attribute is set for the flip-flop circuit at the start point. That is, as can be seen from FIG. 12, the clock arrival time Cl of the flip-flop circuit REG3 which is the starting point is
Since the “Ock Arrival Time” is advanced by 2.4, the attribute of the flip-flop circuit REG3 is set to be post-fixed. Because this flip-flop circuit RE
Clock arrival time of G3
im is related to the flip-flop circuit REG1.
It cannot be delayed any more. (3)
When the processing is performed only when the timing of the flip-flop circuit at the end point can be changed, the front-fixed attribute is set for the flip-flop circuit at the end point. That is, FIG.
As can be seen from FIG.
Clock arrival time of EG1 Clock Arrive
Since Time is delayed by 2.4, the attribute of the flip-flop circuit REG1 is set to be fixed at the front. This is because the clock arrival time Clock Arrival Time of the flip-flop circuit REG1 cannot be further advanced.

(1) When the timing of the flip-flop circuit at the start and end points can be changed, the flip-flop circuit REG3 at the start point and the flip-flop circuit RE at the end point can be changed.
Since G1 can relatively adjust the timing of the clock signal, neither G1 is fixed before or after G1.

As described above, according to the present embodiment, clock signal wiring can be automatically performed in consideration of the propagation delay time Tpd of the combinational logic circuit. For this reason, the time required for wiring design can be significantly reduced. In other words, the clock signal can be automatically wired in consideration of the delay of the data path, so that the design efficiency can be improved.

[0094]

As described above, according to the flip-flop circuit with a delay function according to the present embodiment, the internal clock signal rises after a certain delay time from the rise of the external clock signal. Even if the data input signal arrives at the flip-flop circuit later by the delay time, the flip-flop circuit can correctly take in the data input signal. Therefore,
A sequential circuit using the flip-flop circuit with the delay function can be operated by an external clock signal having a short cycle.

As described above, according to the method for automatically designing clock signal wiring in a semiconductor integrated circuit according to the present invention,
Since the clock signal wiring can be automatically performed in consideration of the propagation delay time of the combinational logic circuit, the time required for designing the clock signal wiring can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a flip-flop circuit with a delay function according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the flip-flop circuit with a delay function shown in FIG. 1;

FIG. 3 is a diagram showing a specific circuit configuration of the flip-flop circuit with a delay function shown in FIG. 1;

FIG. 4 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a flip-flop circuit with a delay function according to a second embodiment of the present invention.

6 is a flowchart illustrating the operation of the flip-flop circuit with a delay function illustrated in FIG. 5;

FIG. 7 is a diagram showing a specific circuit configuration of the flip-flop circuit with a delay function shown in FIG. 5;

FIG. 8 is a view for explaining a flow in the case of designing a sequential circuit by preparing a flip-flop circuit with a delay function as a library;

FIG. 9 illustrates how a hold violation occurs.

FIG. 10 is a flowchart illustrating an algorithm for automatically designing a clock signal line in a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 11 shows a clock signal arrival time setting process.
FIG. 5 is a diagram showing a timing chart of a flip-flop circuit and a clock signal of the flip-flop circuit when the clock signal supply timing of the flip-flop circuit at the start and end points can be changed.

FIG. 12 shows a clock signal arrival time setting process.
FIG. 7 is a diagram showing a timing chart of a flip-flop circuit and its clock signal when the clock signal supply timing can be changed only for the flip-flop circuit at the start point.

FIG. 13 shows a clock signal arrival time setting process.
FIG. 9 is a diagram illustrating a timing chart of a flip-flop circuit and its clock signal in a case where the clock signal supply timing can be changed only for an end-point flip-flop circuit.

FIG. 14 shows a clock signal arrival time setting process.
The figure which shows the flip-flop circuit in the case where the change of the clock signal supply timing of the flip-flop circuit of a start and end point is impossible.

FIG. 15 is a diagram showing a general sequential circuit including a combinational logic circuit and a flip-flop circuit.

FIG. 16 is a diagram showing timing of supplying a clock signal to a flip-flop circuit in a general sequential circuit including a combinational logic circuit and a flip-flop circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 flip-flop circuit 11 latch circuit 20 delay circuit 40 latch circuit 42 pulse signal generation circuit DIS data input signal DOS data output signal ECLK external clock signal ICLK internal clock signal Clock Time A Current cycle time Clock Time B Previous cycle time Clock Time N New cycle Time Delta Convg Minimum transition value for convergence judgment Clock Arrival Time Clock arrival time Slack Slack value

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadahiro Kuroda 580-1 Horikawacho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Toshihiro Terasawa Kawasaki-shi, Kanagawa 25-1 Ekimae-Honcho, Kawasaki-ku F-term (reference) in Toshiba Microelectronics Corporation 5B046 AA08 BA03 BA06 JA07 KA06 (54) [Title of the Invention] Design method of flip-flop circuit with delay function, latch circuit with delay function, sequential circuit Patent application title: Automatic design apparatus for clock signal wiring in semiconductor integrated circuit, and automatic design method for clock signal wiring in semiconductor integrated circuit

Claims (5)

[Claims] 1. A data holding output circuit receiving a data input signal and an internal clock signal, holding a value of the data output signal in synchronization with the internal clock signal, and outputting the value as a data output signal; And a delay circuit that outputs an internal clock signal having a fixed delay time with respect to the input external clock signal. 2. A data input signal is fetched while the internal clock signal is at a high level, and output as a data output signal. When the internal clock signal is at a low level, the data input signal is fetched during a high level. A latch circuit that holds and outputs the data output signal as a data output signal; and a delay circuit that receives an external clock signal and outputs the internal clock signal having a fixed delay time with respect to the input external clock signal. A latch circuit with a delay function, comprising: 3. A method for designing a sequential circuit having a plurality of combinational logic circuits and a plurality of flip-flop circuits connecting between the combinational logic circuits, wherein a logic synthesis is performed using a library of ordinary flip-flop circuits. Performing a timing analysis based on the logic synthesis, and, when operated with a clock signal of a desired speed, determining an unreached time at which an output signal of the combinational logic circuit is delayed with respect to the clock signal. And replacing the library used at the time of logic synthesis with a library to which a flip-flop circuit having a built-in delay circuit having a delay time corresponding to the unreached time is added, and performing logic synthesis again. Design method of sequential circuit. 4. An automatic designing apparatus for clock signal wiring in a semiconductor integrated circuit, comprising: a plurality of combinational logic circuits; and a plurality of flip-flop circuits provided between the combinational logic circuits. A path analysis means for setting a predetermined cycle time, analyzing a path in which the flip-flop circuit is a start point or an end point for all flip-flop circuits, and obtaining a worst slack value for each flip-flop circuit; Of all the flip-flop circuits, the path having the worst slack value is determined as the worst path, and the timing of the output signal from the worst combinational logic circuit forming the worst path matches the timing of the clock signal in the worst path. To determine if
A first condition judging unit, wherein the timing of the output signal from the worst combinational logic circuit is in time for the timing of the clock signal of the worst path,
A cycle time resetting means for setting the cycle time of the clock signal even shorter, and wherein the timing of the output signal from the worst combinational logic circuit is the clock signal of the worst path. If the timing of the worst combinational logic circuit is not in time, the supply timing of the clock signal in at least one of the flip-flop circuit at the preceding stage and the flip-flop circuit at the subsequent stage of the worst combinational logic circuit is adjusted, and the worst combinational logic circuit is adjusted. An automatic clock signal wiring design apparatus for a semiconductor integrated circuit, comprising: clock signal arrival time setting means for making an output signal from a circuit in time. 5. A method for automatically designing clock signal wiring in a semiconductor integrated circuit, comprising: a plurality of combinational logic circuits; and a plurality of flip-flop circuits provided between the combinational logic circuits. A path analysis step of setting a predetermined cycle time, analyzing a path where the flip-flop circuit is a start point or an end point for all the flip-flop circuits, and obtaining a worst slack value for each flip-flop circuit; Among the flip-flop circuits, the path having the worst slack value is determined as the worst path, and whether the timing of the output signal from the worst combinational logic circuit forming the worst path matches the timing of the clock signal in the worst path A first condition determining step of determining the first condition If the timing of the output signal from the worst combinational logic circuit is in time with the timing of the clock signal on the worst path, the cycle time of the clock signal is set to be shorter, and a cycle time resetting step; When the timing of the output signal from the worst combinational logic circuit is not in time for the timing of the clock signal of the worst path in the condition determination of 1, the flip-flop circuit at the preceding stage and the flip-flop circuit at the subsequent stage of the worst combinational logic circuit are provided. Adjusting a clock signal supply timing in at least one flip-flop circuit of the circuits so that an output signal from the worst combinational logic circuit can be made in time. Features in semiconductor integrated circuits Clock signal wiring automatic design method.