JP2000076315A - Lsi designing method and function describing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply a delay calculation algorithm of high order which has high delay calculation precision from a stage of function design. SOLUTION: At a stage of a function level floor plan, a step 3 for selecting the driving capability of the output terminal of an undesigned function block is provided. Consequently, the input signal waveform of an inter-block wiring network can be defined and a delay calculation algorithm of high order can be applied to the delay calculation of inter-block wiring. Further, a step 7 for logically designing the undesigned function block under the restriction of the selected driving capability is provided to eliminate a timing error due to the delay calculation error of the inter-block wiring, thereby eliminating redesigning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit from a functional design to a logic design and a layout design from the top down in consideration of timing.

[0002]

2. Description of the Related Art In recent years, as is called the system-on-silicon era, semiconductor LSI chips that are highly integrated to mount a system on one chip have been developed, and the man-hours required for LSI design have increased. It's going on. Conventionally, in order to solve the problem, a design style of reducing design man-hours by computer-aided design support has been widely and generally used.

[0003] In the process of designing a semiconductor LSI chip,
There are functional design, logical design, and layout design. Functional design is the process of defining the operation to be realized by defining parts in functional units (hereinafter referred to as functional blocks), logical design is the process of converting the functional blocks into logical circuits, and layout design is the process of converting the logical circuits. This is a step of converting into a mask pattern. In addition, functional design, logical design,
A design style that proceeds in the order of layout design is called top-down design. In this top-down design, a procedure is adopted such that when no error is found in the design verification in a certain design process, the process proceeds to the next design process. If the design becomes difficult in a certain design process and a design error such as a timing error does not disappear, it is necessary to return to the previous design process and redo the design. Re-designing between design steps greatly increases design man-hours.

[0004] As a method for preventing re-design, there is a design style in which what is verified in the next step is verified in the previous step as much as possible. Since the abstraction of design information decreases in the order of functional design, logical design, and layout design, if the verification of the current process is attempted in the previous process, the verification accuracy is reduced due to the difference in the abstraction of information. Therefore,
Verification with as little accuracy as possible is an important point in designing without backtracking in top-down design.

On the other hand, due to the progress of the semiconductor LSI chip manufacturing technology, a technology called deep submicron, which is now called deep submicron.
Chips are designed with design rules of 35 microns or less. As a result, the relationship between the wiring delay Tw and the gate delay Tg occupying the signal transmission time in the circuit, that is, the signal delay time (also simply referred to as delay time) becomes Tw> Tg, and the wiring delay is taken into account in the chip design. Is an essential task. This is because the wiring delay does not become smaller than the gate delay because the wiring resistance has increased, even though the gate delay has become smaller due to miniaturization. In particular, since the effect is significant when the wiring length is long, the necessity of a design method that actively considers long wiring such as wiring between functional blocks is called for. Design element technologies in the deep submicron era include "wiring delay model and gate delay model", "wiring topology optimization", "optimizing device size and wiring width", and "optimizing clock wiring". Various studies have been made. These techniques are described in J. Cong et al., "Performance
optimization of VLSI interconnect layout ", INTEGRA
TION, the VLSI Journal, Vol. 21, 1996, pp. 1-94.

Here, attention is paid to wiring delay in the design of a semiconductor LSI chip. In the 1 micron era, little consideration was given to wiring delays because gate delays were dominant over wiring delays. In the sub-micron era, the influence of wiring resistance has appeared and wiring delay has become insignificant. Therefore, to calculate wiring delay, replace wiring with an RC network (R is wiring resistance, C is wiring capacitance), and delay It has begun to use calculation techniques. A typical calculation method is WC Elmore, "The Transien
t Response of Damped Linear Networks with Particul
ar Regard to Wideband Amplifiers ", Journal of Appl
The so-called Elmor of ied Physics, Vol. 19, 1948, pp. 55-63
e-law, J. Rubinstein, et al., "Signal Delay in RCT
ree Networks ", IEEE Transactions on Computer-Aided
The so-called RPH method of Design, Vol. CAD-2, No. 3, 1983, pp. 202-211 is a representative one. These solve the transient response on the output side when the input signal waveform of the wiring network is a step function. The delay value accuracy of these methods is calculated as a value that is almost similar to that measured by circuit simulation SPICE, which is often used as a design accuracy standard. However, if the wiring network becomes complicated or the input signal waveform of the wiring becomes dull, The error increases.

In the current era of the deep submicron, the influence of wiring resistance is further appearing, so that a more accurate delay calculation is required. As one solution, L.
T. Pillage, et al., "Asymptotic Waveform Evaluation
for Timing Analysis ", IEEETransactions on Compute
r-Aided Design, Vol.9, No.4, 1990, pp.352-366
The WE method is often used. In this method, the transient response of a linear circuit is solved using the determinant in the concept of moment. The AWE method uses a q-pole model for the transfer function of a linear system, and the number of poles (poles) q
(Higher-order) increases the accuracy. The number of commonly used poles ranges from 2-5. In order to perform higher order calculations, the input waveform of the wiring network must also be considered. Since the Elmore method is equivalent to the case where the number of poles is 1, the lower order (lower-orde
This can be said to be the delay calculation of r).

Since the wiring delay between the functional blocks occupies an important position in the operation of the semiconductor LSI chip, it is desired to calculate the delay as accurately as possible. In that sense, it is important to perform higher-order delay calculations.

A function level floor plan is one of the methods for designing in consideration of the final physical layout image when designing a function. In this method, the size of a function block is estimated from information of a function description, and functions are divided, blocks are arranged, and provisional wiring (rough wiring) between function blocks is performed. Here, the schematic wiring is
Although the relative wiring path of which functional block passes through the wiring area (wiring channel) is determined, it refers to the wiring whose absolute position is not determined. Also,
The wiring determined to the absolute position is called detailed wiring. As described above, in the function level floor plan, since the design is advanced from the functional design stage using the layout image, it can be said that this is a method of reducing the regression of the design from the logic design to the layout design. In general, the Elmore method is often used for calculating the delay of wiring between functional blocks. This is because the delay can be calculated relatively accurately with only the RC network of the wiring at high speed.

[0010]

In order to design a current semiconductor LSI chip in the deep submicron era, it is indispensable to design in consideration of wiring between functional blocks. As described above, conventionally, there is a function level floorplan method in which wiring between functional blocks is considered from the stage of functional design with a final layout image, but there is a problem in the calculation accuracy of the wiring delay in this method.

For example, since the Elmore method, which is often used, is a low-order calculation algorithm, when calculating a complicated wiring RC network extending over the entire chip, the delay calculation accuracy is low. Furthermore, since the Elmore method assumes the input signal waveform of the wiring network as a step function, the delay calculation accuracy is lower than when the calculation is performed with a certain slope like the signal waveform generated in an actual circuit. Low.

FIG. 16 is a diagram for explaining this.
A single wire can generally be represented by a ladder-type RC network. The left end point represents the input side of the wiring, and the right end point represents the output side of the wiring. The upper part of FIG. 16 is an image diagram in the case of solving by the Elmore method. The input waveform of the wiring is a step function. On the other hand, the lower part of FIG. 16 shows a case where a higher-order delay calculation algorithm is used, and the input waveform of the wiring has an arbitrary slope. As is apparent from the figure, there is a slight delay difference between the two methods. Since the signal waveform is arbitrarily inclined in the circuit in the actual semiconductor LSI chip, the lower part of FIG. 16 is a more accurate model. Particularly for long wirings, the difference further increases.

If the accuracy of the delay calculation is poor, a problem such as a timing error due to a delay calculation error of the wiring between the functional blocks occurs in a logic design or layout design, which may lead to design rework. In order to design the current semiconductor LSI chip in the deep submicron era, the possibility of causing design rework increases if delay calculation with higher accuracy is performed from the function design stage.

An object of the present invention is to provide an LSI design method capable of applying a high-order delay calculation algorithm with high delay calculation accuracy from the stage of function design, and a function description method therefor.

[0015]

In order to achieve the above object, an LSI design method according to the present invention is characterized in that an inter-block wiring network necessary for applying a higher-order delay calculation algorithm in a function design stage. Is to determine the slope of the input signal waveform. Specifically, a driving capability selection step of an output terminal is provided so that the driving capability of a transistor is defined as an attribute of an output terminal of a functional block that has not been designed in a function design stage. This makes it possible to use a higher-order delay calculation algorithm that could not be applied to wiring between functional blocks in the past, and to calculate wiring delay between blocks with higher accuracy.

The feature of the present LSI design method is that, in addition to providing the above-described step of selecting the driving capability of the output terminal, the logic design is performed while observing the defined gradient of the input signal waveform. Specifically, based on the function description information obtained at the time of function design, an initial floor plan step of generating a final layout image by dividing the function blocks into designed function blocks and undesigned function blocks for each function, and an outline between the function blocks. A wiring RC network extracting step of extracting a wiring RC network from the wiring topology, and a driving capability of an output terminal for selecting a driving capability of an output terminal of an undesigned functional block among the functional blocks arranged in the initial floor plan step Step, at least information on the transistors connected to the input / output terminals of the designed functional block, and the output terminal drive capability obtained in the output terminal drive capability selection step for the undesigned functional block, Wiring net between functional blocks using the information of the general wiring topology A delay calculation step for calculating a wiring delay time; a delay improvement step for improving the delay time obtained in the delay calculation step to be within a desired delay time; Repeating the step of selecting the drive capability of the output terminal to select the drive capability of the terminal until all the wiring nets fall within the desired delay time; and, if all the wiring nets fall within the desired delay time, An LSI design method including a constrained logic synthesis step of performing logic synthesis using information obtained in the initial floor plan step, the delay improvement step, and the drive capability selection step of the output terminal as constraints. is there.

A feature of the function description method according to the present invention resides in that the driving capability of a transistor is described as an attribute of an output terminal of a function block. Then, using the information on the driving capability, a highly accurate wiring delay between functional blocks is calculated at the time of functional design.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI design method and a function description method according to the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing an LSI design method according to the present invention. This represents a function level floor plan process of designing with a layout image at the time of function design. Here, it is assumed that a design based on a generally used function description language has been performed. More specifically, in FIG. 1, 1 is an initial floor plan step, 2 is a wiring RC network extraction step, 3 is a drive capacity selection step, 4 is a delay calculation step, 5 is a delay improvement step, and 6 is a delay improvement step. The step of selecting the driving capability of the output terminal, 7 is a constrained logic synthesis step.
The initial floor plan step 1 is subdivided into a block size estimation step 1a, a block arrangement step 1b, an external terminal arrangement step 1c, and a schematic wiring topology generation step 1d. Delay improvement step 5
Is a block arrangement step 5a, an external terminal arrangement step 5b, and a schematic wiring topology generation step 5c.
Step 5d of inserting a buffer for delay improvement, and wiring R
It is subdivided into a C network extraction step 5e and a delay calculation step 5f. The constrained logic synthesis step 7 is a logic synthesis step 7a and a logic cell replacement step 7b, or an input / output terminal initial condition addition step 7b.
c and a logic synthesis step 7d.

Hereinafter, the flow of the LSI design method of FIG. 1 will be described in detail with a specific example.

FIG. 2 shows a hierarchical structure of a circuit in a certain semiconductor LSI chip. According to FIG. 2, circuit L comprises circuits I and K, circuit I comprises circuits H, C and J, circuit K comprises circuits E and F, circuit H comprises circuits A and B, and circuit J Consists of circuits D and G. In other words, seven functional blocks of circuits A, B, C, D, E, F, and G exist in the semiconductor LSI chip including the circuit L. However, it is assumed that the circuits A to F are designed function blocks, and only the circuit G is an undesigned function block.

According to FIG. 1, first, in a block size estimation step 1a of the initial floor plan step 1, the size of each functional block, that is, each of the circuits A to G is estimated from the description of the functional block section in the functional design description. . FIG. 3 shows an estimation result of the block sizes of the circuits A to G. The estimation method is arbitrary. For example, among the functional blocks, those that have been designed in advance because they are made into a library such as a memory or the like use the information of the size, and otherwise use generally logic synthesis such as a control circuit. For the design target, the size is estimated by performing simple logic synthesis (logic synthesis without performing solution improvement processing).

Next, these functional blocks are arranged in a block arranging step 1b. FIG. 4 shows a result of arranging the functional blocks according to the circuits A to G. The circuit G
Are undesigned functional blocks, and are shown by broken lines.

Next, an external terminal arrangement step 1c is performed. At this time, the position of the external terminal is already used for the designed function block, and is used. FIG. 5 shows the circuit A
8 shows the arrangement results of external terminals related to .about.G. The output terminal Aout of the circuit A, the input terminal Bin of the circuit B, the input terminal Cin of the circuit C, the input terminal Din of the circuit D, the input terminal Ein of the circuit E, and the input terminal Fin of the circuit F in FIG. Since they are designed function blocks, they are fixed terminals. On the other hand, the circuit G has a floating terminal because it is an undesigned functional block. The input terminal Gin and the output terminal Go of the circuit G in FIG.
t is a floating terminal. Since the position of the floating terminal is not determined, the position can be arbitrarily determined. However, if the arrangement position is not considered in relation to the terminal positions of other functional blocks, the wiring length may be unnecessarily long. As a result, a timing error and an increase in chip area caused by wiring between functional blocks are caused. In general, it is known that a relatively good result can be obtained by using an algorithm having objective functions such as minimization of a chip area and minimization of a wiring length. The input terminal Gin and the output terminal Go of the circuit G
It is assumed that t is arranged as shown in FIG. 5 according to such an algorithm.

Here, since the terminal arrangement position is determined, a general wiring topology generating step 1d is performed so as to determine a general wiring path between functional blocks. FIG. 6 illustrates a result of generating a schematic wiring topology between functional blocks related to the circuits A to G. The wiring net 1 between functional blocks is {Aout, Cin, Din, Gin}, and the wiring net 2 between functional blocks is {Bin, Ein, Fin, Gout}.
Here, a net is a set of terminals to be connected to the same potential. The wiring path is required to minimize the wiring length while considering delay. Therefore, the delay must be calculated in this step, but the algorithm used here may be a lower-order algorithm. S. Prasitjut
rakul, et al., "A Timing-Driven Global Router for C
ustom ChipDesign ", Proceedings of International Co
nference on Computer-Aided Design, 1990, pp.48-51
Is a typical method.

Next, in the wiring RC network extraction step 2, the RC of the wiring net is extracted according to the schematic wiring topology between the functional blocks. R in the RC extraction is a wiring resistance, and C is a wiring capacitance. Here, a description will be given taking the net 2 in FIG. 6, that is, {Bin, Ein, Fin, Gout} as an example.

FIG. 7 shows a schematic wiring topology of the net 2.
FIG. 8 shows a wiring RC network constructed by extracting the RC therefrom. FIG. 8 shows the π-type C for each segment of the schematic wiring topology decomposed into a certain length.
The RC circuit is defined and connected. A capacitance is added to each end of the wiring in FIG. 8, which is the capacitance of each input terminal. The arrow in FIG. 8 indicates the direction in which the current flows. Here, since the schematic wiring path has already been obtained, the wiring length can be uniquely determined. The wiring resistance can be calculated by a sheet resistance value per unit length. The wiring capacitance is calculated using a capacitance value per unit length used when performing logic synthesis in a timing driven manner, for example. It is assumed that all wiring capacitances are for the LSI substrate. In order to perform the delay calculation statically, the relationship with other nets needs to be irrelevant in terms of the circuit. As one means for this, the wiring capacitance is defined on the LSI substrate.

FIG. 9 shows the response equivalent degeneration of the wired RC network of FIG. The finer the wiring RC network is, the better the analysis accuracy of the behavior due to the wiring is, but there is a disadvantage that the amount of data becomes enormous. Therefore, the original interconnect RC network may be degenerated. Although the delay calculation accuracy generally decreases when the data is degenerated, there is a calculation method in which the delay calculation accuracy does not decrease. FIG. 9 illustrates this. For example, the output terminal Gou before degeneration
This is a method of reducing the wiring RC network so that the relationship between the signal waveform at t and the signal waveform when the signal passes through the wiring and arrives at the input terminal Ein becomes the same even after the reduction. This is called response equivalent degeneration. By performing this operation, degeneration can be performed without impairing the delay calculation accuracy.

Next, in order to define the driving capability of the output terminal Gout with respect to the circuit G which is an undesigned functional block, a driving capability selection step 3 of the output terminal is executed.
FIG. 10 conceptually shows the configuration of the input / output unit of the circuit G. In FIG. 10, reference numeral 10 denotes a logic cell at the input stage.
Numeral 11 denotes the last logic cell. The driving capability of the output terminal Gout refers to the capability of the transistor of the last-stage cell 11 connected to the output terminal Gout. The performance of this transistor can be obtained from the IV characteristics between the drain and the source.

FIG. 11 shows options for the driving capability of the output terminal Gout. Generally, only a few types of driving capability are defined in one cell library. The types include a type having a very small driving capability with reduced power consumption and a type having a large driving capability for driving many cells. In FIG. 11, the IV characteristic (the vertical axis represents the current,
The horizontal axis shows the voltage respectively) There are four patterns,
The larger the amount of current, the higher the driving capability. In step 3 for selecting the driving capability of the output terminal, the minimum driving capability is selected. The reason is that the higher the driving capability, the shorter the delay can be, but the larger transistor size has the disadvantage of increasing the chip area, so select the minimum driving capability from the viewpoint of designing the smallest chip. You do it. In FIG. 11, the IV characteristic 4 corresponds thereto, and the drive type is assigned to the output terminal Gout.

Then, in a delay calculation step 4, delay calculation is performed on the net of the inter-block wiring. The delay calculation algorithm used here is a higher-order calculation algorithm with high delay calculation accuracy, for example, the above-described AWE method. In consideration of the type of the driving capability obtained in step 3 of selecting the driving capability of the output terminal, the input waveform of the wiring is defined, and the wiring delay between the functional blocks is calculated. In the net 1 in FIG. 6, since the circuit A having the output terminal Aout is a designed functional block, the drive capability is determined, so that the delay calculation can be performed.
Since the output terminal of the net 2 is Gout, the IV characteristic 4
Is defined, and delay calculation can be performed.
As described above, by providing the selection step 3 of the drive capability of the output terminal, it is possible to apply a high-order delay calculation algorithm with high calculation accuracy to the entire inter-block wiring.

Next, it is checked whether or not the calculated delay result is within a range of a desired delay value. If there is a violation even in one net, the next delay improvement step 5 is performed. The basic strategy for making improvements is to reduce interblock wiring. To do so, either move the function block itself, change the terminal positions of the input / output terminals of the undesigned function block, shorten the general wiring path, or insert a buffer for improving delay in the wiring path. Or adopt. After executing either of them, the wiring R
C network extraction is performed, and delay calculation is further performed. Therefore, the delay improvement step 5 includes a block arrangement step 5a, an external terminal arrangement step 5b, a schematic wiring topology generation step 5c, a delay improvement buffer insertion step 5d, and a wiring RC network extraction step 5e. And a delay calculation step 5f.

The block arranging step 5a and the external terminal arranging step 5b have the same functions as those in the initial floor plan step 1. The functional blocks and external terminals are moved so that the delay is improved (for example, the wiring length is shortened). FIG. 12 means that the arrangement position of the output terminal Gout in FIG. 6 has been changed by the external terminal arrangement step 5b.

Generation step 5c of schematic wiring topology
Are slightly different from those in the initial floor plan step 1. That is, in step 5c, a higher-order delay calculation algorithm can be used. This is because the input waveform of the wiring net is defined by the above-described drive capability selection step 3 of the output terminal.

Insertion of delay improvement buffer 5d
In the case of a long wiring, a buffer is inserted in the middle of the wiring to improve the inclination of the signal waveform in order to improve a phenomenon that an input waveform of the wiring may be extremely inclined, and as a result, a wiring delay may be increased. This is a step of improving the wiring delay by making an inclination. FIG. 13 shows an example in which one buffer 12 is inserted on the wiring between the output terminal Gout and the input terminal Fin.

After the improvement by the steps 5a to 5d, the wiring RC network extracting step 5e and the delay calculating step 5f are performed again.

If there is a delay value violation even at this stage, the drive capability of the output terminal in the net that has not reached the target value is increased by one type in the selection step 6. Delay improvement step 5
And the step 6 for selecting the driving capability of the output terminal are repeated until all nets do not violate the delay value.

Finally, a constrained logic synthesis step 7 is performed. This is to select the last stage logic cell so that the logic synthesis result of the undesigned function block is the output terminal drive capability type determined in the previous output terminal drive capability selection steps 3 and 6. . Specifically, a method of performing a logic synthesis step 7a and a logic cell replacement step 7b;
There is a method of performing the initial condition addition step 7c and the logic synthesis step 7d of the input / output terminal. In the former, after normal logic synthesis is performed in the logic synthesis step 7a, the type of the last-stage logic cell connected to the output terminal in the logic cell replacement step 7b is changed to the previous output terminal drive capability selection step 3 , 6 is replaced without changing the logic to the same type as the drive capability type of the output terminal. The latter is the step of selecting the driving capability of the output terminal.
The logic synthesis step 7d is executed after defining the constraints in the initial condition addition step 7c so that the drive capability type of the output terminal determined by the above is selected in the logic synthesis step 7d. The constraint referred to here is realized, for example, by giving an input signal waveform to the input terminal and giving a load capacitance value calculated from the load capacitance and resistance of the wiring between the functional blocks to the output terminal.

Thereafter, a layout design is performed based on (restraints) the result of the logic synthesis and the result of the function level floor plan.

As described above, according to the LSI design method of FIG. 1, the drive capability of the output terminal of the undesigned function block is defined at the time of the function level floor plan during the function design, so that the wiring between the function blocks is defined. A highly accurate delay calculation algorithm can be applied to the delay calculation, eliminating timing errors caused by delay calculation errors in wiring between functional blocks, realizing a design that does not return from functional design to logical design and layout design, and shortening the design period. Can be shortened. In addition, since a block arranging step, an external terminal arranging step, a schematic wiring topology generating step, and a delay improving buffer inserting step are provided for delay improvement, fine delay improvement can be performed. it can.

FIG. 14 shows a method for describing the function of a circuit according to the present invention. Here, a widely used function description language Verilog is used. In FIG. 14, "block" is defined as a module name of a functional block, and its input / output terminals include input terminals in1, in2 and output terminals out1, out2. The second to fourth lines indicated by reference numeral 13 represent a new function description method.
“VDD = 3.3” in the second row means that the power supply voltage value is 3.3 volts. "Out1 = (I
s1, Vs1) "is the driving capability of the transistor described as the attribute of the output terminal out1, and" out2 "in the fourth row.
= (Is2, Vs2) "is the driving capability of the transistor described as the attribute of the output terminal out2.

FIG. 15 shows "out1 = (Is1, Vs1)".
Represents the IV characteristics of the transistor represented by. This IV characteristic is a one-point broken line, and the voltage at the switching point between the unsaturated region and the saturated region is Vs1, and the current at this point is Is1. However, these voltage / current values are normalized by the power supply voltage value VDD. In addition, IV
The characteristic may be represented by an arbitrary line. This can be realized simply by increasing the number of polygonal points.

According to the method shown in FIG. 14, the driving capability is described as an attribute of the output terminal in the function description. Higher order algorithms can be used in wiring delay calculation, eliminating timing errors caused by error calculation errors in wiring between functional blocks, realizing a design that does not return from functional design to logic design and layout design, and the design period Can be shortened.

[0044]

As described above, according to the present invention, a higher-precision higher-order delay calculation algorithm can be obtained by determining the transistor driving capability at the output terminal of an undesigned functional block from the stage of functional design. Can be applied to the delay calculation of the wiring between the functional blocks, and the wiring delay can be estimated with high accuracy. As a result, it is possible to obtain a great effect that a timing error caused by a delay calculation error of the wiring between the functional blocks can be eliminated, and design rework can be eliminated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an LSI design method according to the present invention.

FIG. 2 is a conceptual diagram illustrating a hierarchical structure of a circuit in a certain semiconductor LSI chip.

FIG. 3 is a conceptual diagram illustrating a result of estimating a block size for circuits A to G in FIG. 2;

FIG. 4 is a conceptual diagram illustrating an arrangement result of each functional block.

FIG. 5 is a conceptual diagram illustrating an arrangement result of external terminals.

FIG. 6 is a conceptual diagram illustrating a result of generating a schematic wiring topology between functional blocks.

FIG. 7 is a conceptual diagram illustrating a schematic wiring topology of one net in FIG. 6;

8 is a circuit diagram showing a wiring RC network configured by extracting RC from the schematic wiring topology of FIG. 7;

9 is a circuit diagram showing a response equivalent degeneration of the wiring RC network of FIG. 8;

FIG. 10 is a conceptual diagram illustrating a configuration of an input / output unit of a circuit G which is an undesigned circuit block.

FIG. 11 is an IV characteristic diagram showing options of a driving capability related to an output terminal Gout.

FIG. 12 is a conceptual diagram showing that an arrangement position of an output terminal Gout in FIG. 6 has been changed to improve delay.

FIG. 13 is a conceptual diagram showing that one buffer is inserted on a wiring between an output terminal Gout and an input terminal Fin for delay improvement.

FIG. 14 is a diagram showing a circuit function description method according to the present invention.

FIG. 15 is an IV characteristic diagram showing attributes of one output terminal defined in FIG.

FIG. 16 is a diagram illustrating that a difference occurs in a result of wiring delay calculation due to a difference between a low-order delay calculation algorithm (upper part) and a higher-order delay calculation algorithm (lower part).

[Explanation of symbols]

 1 Initial Floor Plan Step 1a Block Size Estimation Step 1b Block Placement Step 1c External Terminal Placement Step 1d Schematic Routing Topology Generation Step 2 Wiring RC Network Extraction Step 3 Output Terminal Driving Capability Selection Step 4 Delay Calculation Step 5 Delay Improvement step 5a Block placement step 5b External terminal placement step 5c Schematic wiring topology generation step 5d Delay improvement buffer insertion step 5e Wiring RC network extraction step 5f Delay calculation step 6 Output terminal drive capability selection step 7 Constrained Logic synthesis step 7a Logic synthesis step 7b Logic cell replacement step 7c Input / output terminal initial condition addition step 7d Logic synthesis step

Claims (7)

[Claims] In an LSI design method employed in a function design in a semiconductor integrated circuit design process, a transistor drive capability is set as an attribute of an output terminal of a function block configured for each function based on function description information. An LSI design method comprising a step of defining. 2. A series of steps for designing a semiconductor integrated circuit from top to bottom in the order of function design, logic design, and layout design, wherein a designed function block and an undesignated function block are classified by function based on function description information obtained at the time of function design. An initial floor plan step of generating a final layout image separately from the functional blocks of the design; a wiring RC network extracting step of extracting a wiring RC network from a schematic wiring topology between the functional blocks; Selecting a drive capability of an output terminal for selecting a drive capability of an output terminal of the undesigned functional block among the functional blocks; and at least information of a transistor connected to an input / output terminal of the designed functional block. Driving the output terminal for the undesigned functional block A delay calculation step of calculating a wiring delay time of a wiring net between functional blocks using the drive capability of the output terminal obtained in the force selection step and the information of the schematic wiring topology, and a delay calculation step. A delay improvement step for improving the delay time to be within the desired delay time, and a driving ability selection step for the output terminal for again selecting the output terminal drive ability for those that have not been improved or have room. Repeatedly executing until all wiring nets fall within a desired delay time; and when all wiring nets fall within a desired delay time, the initial floor plan step, the delay improvement step, and the output terminal. And a constrained logic synthesis step of performing logic synthesis with the information obtained in the selection step of LSI design method to be. 3. The LSI design method according to claim 2, wherein the initial floor plan step includes: a step of estimating a block size for estimating a functional block size; a step of arranging a functional block; and a step of arranging a functional block. An LSI design method, comprising: a step of arranging external terminals for obtaining a position of an input / output terminal; and a step of generating a schematic wiring topology for obtaining a wiring path between functional blocks. 4. The LSI design method according to claim 2, wherein the delay improving step includes: a block arranging step for arranging a functional block; and an external terminal arranging step for finding a position of an input / output terminal of an undesigned functional block. One of: a step of generating a schematic wiring topology for obtaining a wiring path between functional blocks; and a step of inserting a buffer for delay improvement for inserting a buffer in the wiring path between blocks; An LSI design method comprising the same steps as a delay calculation step. 5. The LSI design method according to claim 2, wherein the constrained logic synthesis step includes a logic synthesis step of performing logic synthesis with a timing constraint, a power consumption minimization constraint, and the like, and a final stage of the synthesized logic circuit. A logic cell replacement step of replacing the logic cell with another logic cell without changing the logic in order to change the driving capability of the output terminal of the logic cell. 6. The LSI design method according to claim 2, wherein in the constrained logic synthesis step, an input signal waveform is given to an input terminal of a target functional block, and a load capacitance is given to an output terminal as an initial constraint condition. An LSI design method comprising: an initial condition adding step of input / output terminals; and a logic synthesis step of performing logic synthesis with a timing constraint, a power consumption minimization constraint, and the like. 7. A function description method used in a function design in a design process of a semiconductor integrated circuit, comprising a step of describing a drive capability of a transistor as an attribute of an output terminal of a function block describing a function of the circuit. A function description method characterized by the following.