JP2000076079A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transit to interrupting processing at high a speed at the time of interruption occurrence. SOLUTION: A saving register 16 to be used for holding the same data as data held in a standard register 14 is provided in addition to the standard register 12 to be used for an ALU 12 at the time of ordinary operation, data in the standard register 16 flow to the saving register 16 by a bus control circuit 18 at the time of ordinary operation, data held in the standard register 14 flow to the saving register 16 and when an interruption occurs, the flow of data from the standard register 14 to the saving register 16 is stopped. When the interruption processing is finished, the flow of data between the standard register 14 and saving register 16 is controlled so as to let the data held in the saving register 16 flow to the standard register 14 and to hold them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer, and more particularly, to a microcomputer having an interrupt function.

[0002]

2. Description of the Related Art Conventional microcomputers usually include:
As shown in FIG. 5, the ALU 2 operates while reading / writing data from / to the register 4. When an interrupt process occurs, as shown in FIG. 6, the data held in the register 22 before the interrupt process is saved in the memory area 6 secured in the RAM, and the process proceeds to the interrupt process.

When the interrupt processing is completed, the contents 8 of the register 4 before the interrupt processing saved in the memory area 6 are written back to the register 4, and the processing before the interrupt processing is continued.

In a conventional microcomputer, when an interrupt request occurs, the register 4 is controlled by software.
Is saved to the memory area 6, and after the interrupt processing is completed, the data is written back from the memory area 6 to the register.

[0005]

As described above, in the conventional microcomputer, when an interrupt occurs, the data held in the register 2 is saved by software to the memory area 6 secured in the RAM, and the interrupt processing ends. After that, the saved data was written back.

That is, in the process of saving and writing back the data held in the register by the software, the time until the transition to the interrupt process becomes long, and it is not possible to instantaneously transition to the interrupt process. In addition, since the data in the register is saved and written back by the software, the code size of the program is correspondingly increased.

To solve such a problem, Japanese Patent Laid-Open No.
Japanese Patent Application Publication No. 7642 proposes a microcomputer provided with an evacuation register having the same configuration as a register. According to this microcomputer, it is possible to shorten the time required for transition to the interrupt processing. However, in this microcomputer, the contents of the save register are further transferred to the stack of the built-in RAM. When returning from the interrupt, the data is read from the stack and written back to the general-purpose register. For this reason, this microcomputer has not been able to solve problems such as a long processing time when returning from interrupt processing and a heavy load on software at the time of writing back.

The present invention has been made in view of the above-described circumstances, and provides a microcomputer which can quickly transition to interrupt processing when an interrupt occurs and can return from the interrupt at high speed. The purpose is to:

[0009]

According to the present invention, in addition to a standard register used by an arithmetic unit during normal operation, a save register used to hold the same data as the data held in the standard register is provided. The control circuit allows the data in the standard register to flow to the save register during normal operation,
Saves the data held in the standard register to the save register, stops the flow of data from the table register to the save register when an interrupt occurs, and saves the data held in the save register when the interrupt processing ends. The data flow between the standard register and the save register is controlled so that the data is held in the save register, so that the data held in the standard register is always held in the save register. This eliminates the need to save registers at the time.

Here, it is preferable that the same number of save registers as the number of standard registers be provided, and the corresponding standard registers and save registers be connected to each other by a dedicated bus via a control circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a microcomputer 10 according to the present embodiment. FIG.
As shown in FIG.
12, a standard register 14, a save register 16, and a bus control circuit 18.

A standard register 14 used when the ALU 12 performs a normal operation is connected to the ALU 12 (arithmetic unit). The standard register 14 stores the save register 16 via the bus 20a, the bus control circuit 18, and the bus 20b.
It is connected to the. The save register 16 holds (saves) the data held in the standard register 14 obtained via the buses 20a and 20b under the control of the bus control circuit 18.
Used to

The ALU 12 is a microcomputer 12
An interrupt processing request 30 for receiving an external interrupt request is input. Further, the ALU 12 sends an interrupt signal 32 corresponding to the interrupt processing request 30 to the bus control circuit 18.
Output to

The bus control circuit 18 receives an interrupt processing end signal 34 and a count clock 36 from outside.
The bus control circuit 18 receives an external interrupt processing end signal 3
4 and the interrupt signal 32 from the ALU 12
a, 20b, that is, the data flow between the standard register 14 and the save register 16 is controlled.

The bus control circuit 18 causes the data held in the standard register 14 to flow to the save register 16 during normal operation, and makes the data held in the standard register 14 and the save register 16 the same. The flow of data from the standard register 14 to the save register 16 is stopped, and when the interrupt processing is completed, the data held by the save register 16 is flowed to the standard register 14 so as to be held therein. Control the flow of data between.

FIG. 2 shows the standard register 14 shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration showing a relationship between a save register 16 and a bus control circuit 18. As shown in FIG. 2, the standard register 14 and the save register 16 have the same configuration. Standard register 14 and save register 16
Are connected via a bus control circuit 18 for each bit constituting a register.

FIG. 3 is a block diagram showing a detailed configuration of the bus control circuit 18 shown in FIG. As shown in FIG. 3, the bus control circuit 18 includes a counter 40 and a comparator A4.
2, a comparator B44 and a signal direction changing circuit 46 are provided.

The counter 40 receives the interrupt processing request 30 and the count clock 36. In the counter 40,
The comparator A42 and the comparator B44 are connected. Comparator A4
2, the output from the counter 40 and the interrupt signal 32 are input. The output from the counter 40 and the interrupt processing request 30 are input to the comparator B44.

The signal direction changing circuit 46 is connected to each bit of the standard register 14 via the bus 20a.
It is connected to each bit of the save register 16 via b.
The signal direction changing circuit 46 includes a switch A for controlling the flow of data from the standard register 14 to the save register 16.
And a switch B for controlling a data flow from the save register 16 to the standard register 14 are connected in parallel for each signal line constituting the buses 20a and 20b. On / off of the switch A is controlled by a signal from the comparator A42. On / off of the switch B is controlled by a signal from the comparator B44.

Next, the operation of the microcomputer 10 in the present embodiment will be described. When the microcomputer 10 is performing a normal operation, the ALU 12
Operate using the standard register 14. Also,
The bus control circuit 18 turns on the switch A of the signal direction changing circuit 46 by the comparator A42, thereby enabling the flow of data from the standard register 14 to the save register 16. (Note that the switch B of the signal direction changing circuit 46 is turned off by the comparator B44). Therefore, ALU12
The data written in the standard register 14 as a result of the normal operation is immediately reflected in the save register 16 and held. That is, the data held in the standard register 14 is always saved in the save register 16.

On the other hand, the ALU 12 transmits the interrupt processing request 30
Is input from the outside, an interrupt signal 32 is output to the bus control circuit 18. The bus control circuit 18 includes a comparator A42
Input the interrupt signal 32. The comparator A42 turns off the switch A of the signal direction changing circuit 46 in response to the interrupt signal 32. That is, the flow of data from the standard register 14 to the save register 16 is stopped.

Due to the stoppage of the data flow, the data held in the standard register 14 immediately before the interrupt signal 32 is input to the bus control circuit 18, ie, before the interrupt processing is started, is held in the save register 16. Will be. Accordingly, the microcomputer 10 can immediately transition to the interrupt processing without performing the save processing for the data held in the standard register 14.

When the interrupt processing is completed, an interrupt processing end signal 34 is input to the bus control circuit 18. The bus control circuit 18 receives the interrupt processing end signal 34 from the comparator B44. The comparator B44 turns on the switch B of the signal direction changing circuit 46 according to the interrupt processing end signal 34.
That is, the flow of data from the save register 16 to the standard register 14 is enabled (the switch A remains off).

From the save register 16 to the standard register 1
By enabling the flow of data to 4, the data held in the save register 16, that is, the data saved before the interrupt processing, is written back to the standard register 14.

When the operation of writing data back to the standard register 14 is completed, the bus control circuit 18 returns to the normal operation,
The comparator A is operated so that the data written in the standard register 14 by the ALU 12 is reflected in the save register 16.
The switch A is turned on by 42 and the switch B is turned off by the comparator B44. Thus, the data held in the standard register 14 is always saved in the save register 16.

FIG. 4 is a timing chart showing the timing of each signal. Referring to FIG. 4, when an interrupt request occurs during a normal operation, an interrupt processing request 30 from the microcomputer 10 is input to the ALU 12 at T0. The ALU 12 performs an interrupt process and outputs an interrupt signal 32 to the bus control circuit 18.

The comparator A42 is turned off at the falling edge T1 of the interrupt signal 32. When the output of the comparator A42 turns off, the switch A also turns off at T2. Since T2 is off, the flow of data from the standard register 14 to the save register 16 also stops. From here, a transition is made to interrupt processing, and interrupt processing is executed.

When the interrupt processing is completed, the interrupt processing end signal 34 is output to the counter 40 of the bus control circuit 18 and the comparator B4.
4 is input. The comparator B44 is turned on at the falling T3 of the interrupt processing end signal 34. When the output of the comparator B44 is turned on, the switch B is also turned on at T4, the data flow from the save register 16 to the standard register 14 becomes valid, and the data held in the save register 16 is written back to the standard register 14. .

At T3, the counter 40 also starts a counting operation in response to the interrupt processing end signal 34. When the counter 40 counts for a time necessary for writing back from the save register 16 to the standard register 14, a counter pulse is generated and the comparator A
15 and a comparator B16.

At the falling edge of the counter pulse, the comparator A4
2 and the output of the comparator B44 are inverted. The inverted output is input to each of the switches A and B at T6, and the states of the switches A and B become the states before the interrupt processing, and the bus control circuit 18 returns to the normal operation and is written in the standard register 14. The saved data is stored in the save register 16
Is reflected (evacuated).

As described above, in the microcomputer according to the present embodiment, when a transition is made to interrupt processing, the contents of the standard register 14 are stored in the save register 16 via the bus 20a, the bus control circuit 18 and the bus 20b.
Just write it to On the other hand, when returning from the interrupt processing, the contents of the save register 16 can be written back to the standard register via the bus 20b, the bus control circuit 18 and the bus 20a.

For this reason, not only can the processing time required to transition to the interrupt processing be reduced, but also the processing time required to return from the interrupt processing can be reduced.

[0034]

As described above in detail, according to the present invention, during normal operation, the data held in the standard register used when the operation unit operates is always reflected in the save register, so that the interrupt can be performed. When a request occurs, it is possible to transition to interrupt processing without performing save processing for data held in the standard register. That is, when an interrupt processing request is generated, processing by software for saving the data of the register to the memory is not required, and the transition to the interrupt processing can be performed at high speed. Further, the code size can be reduced without the need for software to save the register.

Further, according to the present invention, the processing time when returning from an interrupt can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a microcomputer according to an embodiment.

FIG. 2 is a block diagram showing a relationship among a standard register, a save register, and a bus control circuit shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of a bus control circuit shown in FIG. 2;

FIG. 4 is a timing chart showing the timing of each signal.

FIG. 5 is a diagram for explaining the operation of the microcomputer.

FIG. 6 is a diagram illustrating a register save process when an interrupt process occurs.

[Explanation of symbols]

 Reference Signs List 10 microcomputer 12 ALU 14 standard register 16 save register 20a, 20b bus 30 interrupt processing request 32 interrupt signal 34 interrupt processing end signal 36 count clock 40 counter 42 comparator A 44 comparator B 46 signal direction changing circuit A, B switch

Claims (2)

[Claims] An arithmetic unit, a standard register used by the arithmetic unit during normal operation, a save register for storing the same data as the data held in the standard register, and a standard register during normal operation. In the save register, save the data held in the standard register to the save register, stop the flow of data from the reference register to the save register when an interrupt occurs, and execute interrupt processing. And a control circuit for controlling a data flow between the standard register and the save register so that the data held by the save register is caused to flow to the standard register when the save is completed. Microcomputer. 2. The number of the save registers is equal to the number of the standard registers, and the standard registers and the save registers are connected to each other via the control circuit by a dedicated bus. The microcomputer according to claim 1, wherein: