JP2000069406A - Image processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the image processing unit to apply recording processing to a still picture even while applying recording processing to a moving picture. SOLUTION: An image pickup element 50 outputs an image signal in response to an incident optical image to a camera processing circuit 52. The camera processing circuit 52 and a recording processing circuit 54 are connected by a bus 56, which also connects to an image memory 58. The camera processing circuit 52 and the recording processing circuit 54 are accessible to the image memory 58 via the bus 56 individually. The bus 56 has a bandwidth that is a sum of a bandwidth required for recording processing of a moving picture and a bandwidth by which recording processing of a still picture is simultaneously conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus that processes a plurality of image data substantially simultaneously.

[0002]

2. Description of the Related Art FIG. 2 shows a schematic block diagram of a conventional video camera. The image sensor 10 outputs an image signal corresponding to the optical image. The camera processing circuit 12 stores the image signal from the image sensor 10 in the camera memory 14,
Correction values such as γ correction, gain correction, and color balance correction are determined, and these corrections are executed. The correction values are converted into a luminance signal / color difference signal and applied to the recording processing circuit 16. Recording processing circuit 1
6 records (for example, compression-encodes) the image information from the camera processing circuit 12 using the recorder memory 18 and records it on the recording medium 20.

FIG. 3 is a block diagram showing a schematic configuration of the recording processing circuit 16. The control circuit 22 controls the whole. Image data from the camera processing circuit 12 is input from an input terminal 24 to a DCT circuit 28 via a bus 26. The DCT circuit 28 performs a discrete cosine transform of the input image data, and converts the resulting transform coefficient data via a bus 26 into a quantization circuit 30.
To supply. The quantization circuit 30 quantizes the input transform coefficient data, and the result is supplied to the recorder memory 18 via the bus 26 and the data input / output terminal 32 and stored.

The quantized transform coefficient data stored in the recorder memory 18 is read and applied to an error correction encoding circuit 34 via a data input / output terminal 32 and a bus 26. The error correction coding circuit 34 performs error correction coding on the input data, adds parity for error correction, and stores the input data again in the memory 18 via the bus 26 and the data input / output terminal 32. The encoded image data with parity stored in the memory 18 is read out and input to the formatter 36 via the input / output terminal 32 and the bus 26. The formatter 36 converts the input data into a data format suitable for the recording medium 20. The output of the formatter 36 is amplified by the output amplifier 38, supplied to the recording medium 20 from the output terminal 40, and recorded on the recording medium 20.

[0005]

In the prior art, while recording a moving image, other processing, for example, a still image processing could not be performed.

An object of the present invention is to provide an image processing apparatus capable of performing another still image processing even during moving image processing.

[0007]

According to the present invention, there is provided an image processing apparatus comprising: a camera processing circuit for digitally processing a captured image signal obtained from an image sensor; and a recording processing of the image signal from the camera processing circuit. An image recording circuit for recording on a recording medium; an image memory commonly used by the camera processing circuit and the image recording circuit; and a bus to which the camera processing circuit, the image recording circuit, and the image memory are connected. The bus is characterized by having a sufficient bus width to enable time-sharing of interrupt processing different from moving image processing.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. The image sensor 50 outputs an image signal corresponding to the incident optical image to the camera processing circuit 52. The functions of the camera processing circuit 52 and the recording processing circuit 54 of this embodiment are not different from those of the camera processing circuit 12 and the recording processing circuit 16 of the conventional example, respectively.

In this embodiment, the camera processing circuit 52 and the recording processing circuit 54 are connected to a bus 56, and the bus 56 is further connected to an image memory 58. That is, in this embodiment,
The camera processing circuit 52 and the recording processing circuit 54 can separately access the image memory 58 via the bus 56. In other words, the image memory 58 stores the camera processing circuit 52
And a shared memory of the recording processing circuit 54.

Further, the bus 56 has a bandwidth obtained by adding a bandwidth required for still image processing to a bandwidth necessary for moving image processing.

The camera processing circuit 52 uses the image memory 58 to perform γ correction, gain correction, color balance correction, and the like on the image signal from the image sensor 50, and converts the image signal into a luminance signal / color difference signal, and performs a recording process Supply to circuit 54. The recording processing circuit 54 processes the input image signal in the same manner as the recording processing circuit 16 using the image memory 58, and
To record.

In this embodiment, the camera processing circuit 52, the recording processing circuit 54 and the image memory 58 are operated at a sufficiently high speed and / or
Alternatively, they are connected by a wide bus 56. As a result, the time for occupying the bus 56 in data transfer can be reduced, and the recording processing circuit 54 can perform still image processing simultaneously with moving image processing in a time division manner. FIG. 4 shows the timing chart.

During the quantization of the moving image, the DC of the still image is
A T process is executed, a still image quantization process is performed during the moving image error correction coding process, and a still image error correction coding process is performed during the moving image recording process.

FIG. 4 shows the processing of each stage of a still image as if it were completed within the same time as the processing of each stage of a moving image. It is not necessary to match the time with the corresponding processing time of the moving image, and more time may be required for the processing of each stage of the still image. That is, assuming that the time required for the moving image processing is H, the processing of the still image may be completed within n × H (n is a natural number).

[0016]

As can be easily understood from the above description, according to the present invention, still image processing can be executed even during moving image processing.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional example.

FIG. 3 is a schematic configuration block diagram of a recording processing circuit 16;

FIG. 4 is a timing chart of moving image processing and still image processing according to the present embodiment.

[Explanation of symbols]

 10: Image sensor 12: Camera processing circuit 14: Camera memory 16: Recording processing circuit 18: Recorder memory 20: Recording medium 22: Control circuit 24: Input terminal 26: Bus 28: DCT circuit 30: Quantization circuit 32: Data input / output terminal 34: error correction encoding circuit 36: formatter 38: output amplifier 40: output terminal 50: imaging device 52: camera processing circuit 54: recording processing circuit 56: bus 58: image memory 60: recording medium

Claims (2)

[Claims] 1. A camera processing circuit for digitally processing a captured image signal obtained from an image sensor, an image recording circuit for recording an image signal from the camera processing circuit, and recording the image signal on a recording medium, Circuit and an image memory commonly used by the image recording circuit, and a bus to which the camera processing circuit, the image recording circuit and the image memory are connected, and the bus performs time-division interrupt processing different from moving image processing. An image processing apparatus having a sufficient bus width to allow the image processing to be performed in a timely manner. 2. The image processing apparatus according to claim 1, wherein the interrupt processing is a still image recording processing.