JP2000068974A - Ofdm receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an orthogonal frequency division multiplex(OFDM) receiver in a small circuit scale. SOLUTION: A symbol synchronization detection circuit 4 outputs a pulse ϕSP for each one symbol period based on an output signal from an A/D converter 35. An M symbol period calculation counter 5 uses a sampling clock CLK to output a pulse ϕMCP after the elapse of a period equivalent to an M symbol period after a pulse ϕSP (ST) is outputted. A comparator 6 controls a sampling frequency so that a time position of an M-th pulse ϕSP after a pulse ST is outputted is coincident with a time position of the pulse ϕMPC. Since it is not required to separately provide a synchronization purpose A/D converter different from a conventional receiver, the circuit scale is made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM receiving apparatus, and more particularly, to an OFDM receiving apparatus in which an original signal is encoded into an in-phase axis signal and a quadrature axis signal in synchronization with a clock signal of a predetermined frequency and transmitted by an OFDM method. Receive the signal,
The present invention relates to an OFDM receiver that reproduces an original signal from the OFDM signal.

[0002]

2. Description of the Related Art In recent years, OFDM has been widely used in digital audio broadcasting for mobile objects and digital terrestrial television broadcasting.
(Orthogonal Frequency Division Multiplex) transmission system has attracted attention.

In the OFDM system, digital data (original signal) to be transmitted is encoded into an in-phase axis signal (hereinafter referred to as I signal) and a quadrature axis signal (hereinafter referred to as Q signal) in synchronization with a clock signal having a predetermined frequency. After that, a large number of subcarriers (hereinafter, referred to as subcarriers) orthogonal to each other are modulated by an I signal and a Q signal, and the modulated waves are multiplexed and transmitted.

[0004] In this method, transmission data is stored in several hundreds to several hundreds.
The modulation symbol rate of each subcarrier is extremely low because the modulation is performed by dispersing the modulation into thousands of subcarriers.
The symbol period becomes extremely long. For this reason, it is less likely to be affected by multipath.

Further, as shown in FIG. 4, by setting a guard period before an effective symbol period in an OFDM modulated signal, it is possible to effectively remove the influence of multipath interference. The guard period is formed by cyclically copying the latter half of the effective symbol period. If the delay time of the multipath interference is within the guard period, by demodulating only the signal in the effective symbol period during demodulation, it is possible to prevent intersymbol interference due to delayed adjacent symbols.

FIG. 5 is a block diagram showing a configuration of a conventional OFDM receiving apparatus used in such an OFDM transmission system. Referring to FIG. 5, the OFDM modulated signal is received by antenna 31 and tuner 32 and converted to an intermediate frequency signal (hereinafter, referred to as an IF signal). IF
The signal is input to the quadrature demodulation circuit 33, where the I signal and the Q
Converted to a signal. The I signal and the Q signal are input to an A / D converter 35 via a low-pass filter (LPF) 34. The output of the A / D converter 35 is converted into digital data φD by the FFT circuit 36 and the decoding circuit 37, and is output to a signal processing unit (not shown) at the next stage.

The I signal and the Q signal are supplied to the LPF 34
Is input to another A / D converter 38 via
The output of the D converter 38 is a sampling frequency synchronizing circuit 39
Supplied to

[0008] The sampling frequency synchronization circuit 39
A sampling frequency error is detected based on the characteristics of the DM signal, and error information is supplied to a sampling clock generation circuit 45. The sampling frequency generation circuit 45 controls the sampling frequency according to the error information, and outputs the internal sampling clock NCLK to the A / D converter 38.
The internal sampling clock NCLK is frequency-divided by the frequency divider 49 to become a sampling clock CLK. The sampling clock CLK is equal to the internal sampling clock NC.
It has a frequency of 1 / N times LK (where N is an integer of 2 or more) and is provided to the A / D converter 35.

Next, the sampling frequency synchronization operation of the OFDM receiver will be described in detail. The I and Q signals A / D converted by the A / D converter 38 are input to the delay memory 40 and the correlator 41 of the sampling frequency synchronization circuit 39. In the correlator 41, the signal delayed by the effective symbol period by the delay memory 40 and the A / D
A correlation coefficient with the signal directly input from the converter 38 is calculated, and the correlation coefficient is output as a peak signal φPK.

The correlator 41 includes a complex multiplication unit 51, a moving average unit 52, and an absolute value addition unit 53, as shown in FIG. After complexly multiplying the I and Q signals of the two systems, taking a moving average with a guard period width, taking the sum of the absolute values, the peak signal φPK is output. The peak signal φPK has a peak at a symbol period interval.

That is, as shown in FIG.
In the output signal of the D converter 38, each effective symbol period S1,
Guard periods G1, G2,... Are added at the beginning of S2,. The guard periods G1, G2,... Are respectively the latter half portions G1 ′, G in the effective symbol periods S1, S2,.
2 ′,...

Therefore, when the output signal of the A / D converter 38 is delayed by the effective symbol period by the delay memory 40, as shown in FIGS. 7A and 7B, the guard period of the output signal of the delay memory 40 is reduced. ., G1 ′, G2 ′,.
G2 ',... Coincide with each other. Since Gn and Gn 'are in a copying relationship, the signal correlation during this period is high. In other periods, since the OFDM signal is a noise signal as shown in FIG. 4, the correlation is low. Therefore, as shown in FIG. 7C, the output from the correlator 41 gradually increases from the start timing of the guard periods G1, G2,... And reaches a peak at the symbol period end timing.

Returning to FIG. 5, the symbol synchronization detection circuit 42
Generates a symbol synchronization pulse φSP in synchronization with the peak signal φPK given from the correlator 41, as shown in FIGS.

The one-symbol period calculation counter 43 counts the number of pulses of the internal sampling clock NCLK. The one-symbol period calculation counter 43 sets a certain pulse in the symbol synchronization pulse φSP to the start pulse ST.
And counts the number of pulses corresponding to one predetermined symbol (the number of pulses per symbol of the clock frequency on the transmitting side by N), and then outputs the one symbol count pulse φCP.

The symbol synchronization pulse φSP and the one-symbol count pulse φCP are input to a comparator 44. The comparator 44 compares the temporal position of the next symbol synchronization pulse φSP with the temporal position of the one-symbol count pulse φCP with reference to the start pulse ST, and samples the sampling frequency error information based on the comparison result. Output to the clock generation circuit 45.

For example, as shown in FIG. 8C, a one-symbol count pulse φCP is a symbol synchronization pulse φSP
When the sampling frequency error coincides with that on the transmitting side, the sampling frequency error information has information of 0 because it is necessary to maintain the frequency.

As shown in FIG. 8D, when the one-symbol count pulse φCP is faster than the symbol synchronization pulse φSP by the period Ta, the sampling frequency is higher than that on the transmitting side, and the sampling frequency is lowered. The sampling frequency error information is -T
It has information a.

Conversely, as shown in FIG. 8 (e), when the one-symbol count pulse φCP is later than the symbol synchronization pulse φPK by the period Tb, the sampling frequency is raised lower than that of the transmitting side. Since it is necessary, the sampling frequency error information is + Ta
With the information.

The sampling frequency error information is integrated by the loop filter 46 of the sampling clock generation circuit 45. The output of the loop filter 46 is a D / A converter 47
D / A conversion and voltage controlled crystal oscillator (hereinafter VCXO)
) Of the control voltage. The VCXO 48 generates a clock NCLK having a frequency N times the sampling frequency according to the control voltage.

The internal sampling clock NCLK generated by the VCXO 48 is supplied to the A / D converter 38 as it is, and is also converted by the frequency divider 49 into a sampling clock CLK having a sampling frequency and sent to the A / D converter 35. Given. In this way, sampling frequency synchronization is achieved.

Note that the A / D converter 38 and the sampling frequency synchronizing circuit 39 use the sampling frequency N
The reason why the clock NCLK having the double frequency is used is to detect a sampling frequency error smaller than the subcarrier interval.

That is, as shown in FIGS. 9 (a) and 9 (b), when the symbol period is counted using a clock having a very high frequency, even if the error includes a sub-carrier interval or less, the symbol synchronization pulse The error can be detected with high accuracy by comparing with the one symbol count pulse φCP ″.

However, when the clock CLK having the same frequency as the sampling frequency is used, the symbol synchronization pulse φSP 'and the one-symbol count pulse φCP' are generated as shown in FIG.
As shown in (c) and (d), the comparator 44 determines that there is no error, and a malfunction occurs.

On the other hand, by using a clock NCLK having a frequency N times the sampling frequency, the accuracy of symbol synchronization pulse generation and 1-symbol count pulse generation is improved, and as shown in FIGS. An error smaller than the subcarrier interval can be detected.

[0025]

However, the conventional OFD
In the M receiving device, there are two types of clocks CLK and NCLK, and two A / D converters 35 and 38 are used. Therefore, there is a problem that the circuit scale of the OFDM receiving device becomes large.

Therefore, a main object of the present invention is to provide an OFDM receiver having a small circuit size.

[0027]

The invention according to claim 1 is
OFDM receiver for receiving an OFDM signal in which an original signal is encoded into an in-phase axis signal and a quadrature axis signal in synchronization with a clock signal of a predetermined frequency and transmitted by the OFDM method, and reproducing the original signal from the OFDM signal And a demodulating unit, a clock generating unit, an A / D converter, a decoding unit, a first symbol period detecting unit, a second symbol period detecting unit, and a control unit. The demodulation means receives the received O
The FDM signal is demodulated into an in-phase axis signal and a quadrature axis signal.
The clock generating means is provided for generating a sampling clock signal having the same frequency as the clock signal, and its oscillation frequency is controllable. The A / D converter is
The output signal of the demodulation unit is converted into a digital signal in synchronization with the sampling clock signal generated by the clock generation unit. The decoding means decodes the output signal of the A / D converter to reproduce the original signal. The first symbol period detecting means includes:
One symbol period of the OFDM signal is detected based on the output signal of the A / D converter. The second symbol period detection unit detects a period corresponding to M symbol periods (where M is an integer of 2 or more) based on the sampling clock signal generated by the clock generation unit. The control unit is configured to control the one detected by the first symbol period detection unit.
The oscillation frequency of the clock generator is controlled so that the period corresponding to the M symbol period detected by the second symbol period detector matches the period obtained by multiplying the symbol period by M.

According to the second aspect of the present invention, in one symbol period of the OFDM signal according to the first aspect of the present invention, the effective symbol period and the waveform of the latter half of the effective symbol period are copied before the effective symbol period. And a formed guard period. A first symbol period detecting means for delaying an output signal of the A / D converter by an effective symbol period;
A correlator for obtaining a correlation coefficient between the output signal of the / D converter and the output signal of the delay means, and a pulse generating means for outputting a pulse signal in synchronization with a peak value of the correlation coefficient obtained by the correlator. . The second symbol period detecting means is activated in response to the output of a certain pulse signal from the pulse generating means, and counts the number of pulses of the sampling clock signal generated by the clock generating means to the M of the transmitting side clock signal.
It includes a counter that counts the number of pulses per symbol period and outputs a count-up pulse signal. The control means controls the oscillation frequency of the clock generation means so that the time position of the count-up pulse signal of the counter coincides with the time position of the M-th output pulse signal after the pulse signal is output from the pulse generation means. Control.

[0029]

FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of an OFDM receiver according to the first embodiment, and is a diagram compared with FIG.

Referring to FIG. 1, an OFDM modulated signal is received by antenna 31 and tuner 32 and
Converted to a signal. The IF signal is input to the quadrature demodulation circuit 33 and is converted into an I signal and a Q signal. The I signal and the Q signal are input to the A / D converter 35 via the LPF 34. The output of the A / D converter 35 is decoded into digital data φD by the FFT circuit 36 and the decoding circuit 37, and is output to a signal processing unit (not shown) at the next stage.

The output of the A / D converter 35 is also supplied to the sampling frequency synchronization circuit 1. In the present invention, there is one A / D converter 35, and the clock for operating the sampling frequency synchronization circuit 1 is the same clock as the sampling clock CLK. The sampling frequency synchronizing circuit 1 detects a sampling frequency error based on the characteristics of the OFDM signal and provides error information to a sampling clock generating circuit 7. The sampling frequency generation circuit 7 controls the sampling frequency according to the error information, and outputs a sampling clock CLK to the A / D converter 35.

Next, the sampling frequency synchronization operation of the OFDM receiver will be described in detail. The I and Q signals A / D converted by the A / D converter 35 are input to the delay memory 2 and the correlator 3 of the sampling frequency synchronization circuit 1. In the present invention, the memory capacity of the delay memory 2 may be 1 / N as compared with the related art. That is, since the operating clock frequency is 1 / N as compared with the related art, the memory capacity required to delay the same effective symbol period is 1 / N. The correlator 3 outputs the signal delayed by the effective symbol period by the delay memory 2 and the A / D converter 3
5 to calculate the correlation coefficient of the signal directly input and output the correlation coefficient as a peak signal φPK.

In the symbol synchronization detection circuit 4, FIG.
As shown in (b), a symbol synchronization pulse φSP is generated based on the peak signal φPK provided from the correlator 4.

The M symbol period calculation counter 5 counts the number of pulses of the sampling clock CLK. The M symbol period calculation counter 5 outputs the symbol synchronization pulse φS
Counting is started with a certain pulse of P as a start pulse ST, and after counting a predetermined number of pulses corresponding to M symbols (the number of pulses per M symbol period of the clock signal on the transmission side), an M symbol count pulse φ
Output MCP.

The symbol synchronization pulse φSP and the M symbol count pulse φMCP are input to the comparator 6. In the comparator 6, the start pulse ST is used as a reference.
Comparing the temporal position of the th symbol synchronization pulse φSP with the temporal position of the M symbol count pulse φMCP,
The sampling frequency error information is given to the sampling clock generation circuit 7 based on the comparison result.

For example, as shown in FIG. 2C, M symbol count pulse φMCP is a symbol synchronization pulse φS
If the value matches P, the sampling frequency matches that of the transmitting side, and it is necessary to keep the sampling frequency. Therefore, the sampling frequency error information has information of 0.

As shown in FIG. 2D, the M symbol count pulse φMCP is changed to the symbol synchronization pulse φSP.
If the sampling frequency is faster than the transmission side by the period Ta, the sampling frequency needs to be higher than that of the transmitting side and the sampling frequency needs to be lowered.
It has information a.

Conversely, as shown in FIG. 2E, the M symbol count pulse φMCP is changed to the symbol synchronization pulse φSP.
If the sampling frequency is later than the transmission side by a period Ta, the sampling frequency must be lower than that of the transmitting side and the sampling frequency needs to be increased.
It has information a.

In the present invention, as shown in FIGS. 3 (a) to 3 (d), by using the M symbol period for comparison, the same clock as the sampling clock CLK can be used to perform sampling at subcarrier intervals or less. It is possible to detect a frequency error. That is, if the operation clock is the same as the sampling clock CLK, the detection accuracy is low, so that the error cannot be detected in one symbol period. However, by making the comparison period longer than the M symbol period, the error can be detected.

The sampling frequency error information is integrated by the loop filter 8 of the sampling clock generation circuit 7. The output of the loop filter 8 is D / A converted by a D / A converter 9.
It is converted to a control voltage of the VCXO 10. VCXO1
0 generates a clock CLK having a sampling frequency according to the control voltage, and outputs the clock CLK to the A / D converter 3.
5 as it is. In this way, sampling frequency synchronization is achieved.

In this embodiment, the M symbol period detected from the output signal of the A / D converter 35 for decoding and the period corresponding to the M symbol period detected by counting the number of pulses of the sampling clock CLK are defined. To compare,
Conventionally, a clock N having a frequency N times the sampling frequency is used.
A relatively small frequency error that could not be detected without using CLK can be detected using sampling clock CLK as it is. Therefore, there is no need to provide two A / D converters 35 and 38 for synchronization and decoding as in the related art, and only one A / D converter 35 is required. Further, since the clock frequency of the sampling frequency synchronization circuit 1 becomes 1 / N of the conventional one, the memory capacity of the delay memory 2 constituting the sampling frequency synchronization circuit 1 becomes 1 / N of the conventional one.
No problem. Therefore, an OFDM receiver having a small circuit scale is realized.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0043]

As described above, according to the first aspect of the present invention, the A / D converter converts the I signal and the Q signal into digital signals in synchronization with the sampling clock signal and supplies the digital signals to the decoding means.
A converter, first symbol period detecting means for detecting one symbol period based on the output signal of the A / D converter, and second symbol detecting a period corresponding to the M symbol period based on the sampling clock signal A period detecting means, and M detected during a period obtained by multiplying the detected one symbol period by M.
And control means for controlling the sampling frequency so that the periods corresponding to the symbol periods coincide. Therefore, since only one A / D converter is required, the circuit scale can be smaller than in the conventional case where two A / D converters for decoding and synchronization are required.

According to the invention of claim 2, one symbol period of the OFDM signal of the invention of claim 1 includes an effective symbol period and a guard period. The first symbol period detection means obtains a correlation coefficient between the output signal of the A / D converter and a signal obtained by delaying the output signal by an effective symbol period, and outputs a pulse signal in synchronization with the peak value of the correlation coefficient. I do. The second symbol period detection means is activated in response to a certain pulse signal, counts the number of pulses of the sampling clock signal by the number of pulses per M symbol periods of the clock signal on the transmission side, and outputs a count-up pulse signal. I do. The control means controls the sampling frequency such that the time position of the count-up pulse signal coincides with the time position of the Mth output pulse signal after the output of a certain pulse signal. Thus, detection of one symbol period, detection of a period corresponding to M symbol periods, and control of sampling frequency can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an OFDM receiver according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of the OFDM receiver shown in FIG.

FIG. 3 is another time chart showing the operation of the OFDM receiver shown in FIG.

FIG. 4 is a waveform chart showing an OFDM modulation signal.

FIG. 5 is a block diagram illustrating a configuration of a conventional OFDM receiver.

FIG. 6 is a block diagram showing a configuration of the correlator shown in FIG.

FIG. 7 is a time chart illustrating an operation of the correlator illustrated in FIG. 6;

FIG. 8 is a time chart illustrating an operation of the OFDM receiver illustrated in FIG. 5;

9 is another time chart showing the operation of the OFDM receiver shown in FIG.

[Explanation of symbols]

 1,39 Sampling frequency synchronization circuit 2,40 Delay memory 3,41 Correlator 4,42 Symbol synchronization detection circuit 5,43 1 Symbol period calculation counter 6,44 Comparator 7,45 Sampling clock generation circuit 8,46 Loop filter 9 , 47 D / A converter 10, 48 VCXO 33 Quadrature demodulation circuit 35, 38 A / D converter 37 Decoding circuit

Claims (2)

[Claims] 1. An OFDM signal, in which an original signal is encoded into an in-phase axis signal and a quadrature axis signal in synchronization with a clock signal of a predetermined frequency, and the OFDM signal is transmitted by an OFDM method,
An OFDM receiving apparatus for reproducing an original signal from the OFDM signal, a demodulating means for demodulating the received OFDM signal into an in-phase axis signal and a quadrature axis signal, and an oscillation for generating a sampling clock signal having the same frequency as the clock signal. A clock generation unit capable of controlling frequency, an A / D converter for converting an output signal of the demodulation unit into a digital signal in synchronization with a sampling clock signal generated by the clock generation unit, Decoding means for decoding an output signal to reproduce an original signal; first symbol period detecting means for detecting one symbol period of an OFDM signal based on an output signal of the A / D converter; A period corresponding to M symbol periods (where M is an integer of 2 or more) is determined based on the sampling clock signal obtained. The second symbol period detecting means for output, detected by said first symbol period detecting means 1
An OFDM receiving apparatus comprising: control means for controlling an oscillation frequency of the clock generation means so that a period corresponding to the M symbol period detected by the second symbol period detection unit coincides with a period obtained by multiplying a symbol period by M. . 2. One symbol period of the OFDM signal is:
An effective symbol period; and a guard period formed by copying a waveform of a latter half of the effective symbol period before the effective symbol period. Delay means for delaying an output signal by the effective symbol period, a correlator for obtaining a correlation coefficient between an output signal of the A / D converter and an output signal of the delay means, and a correlation coefficient obtained by the correlator And a pulse generating means for outputting a pulse signal in synchronization with the peak value of the clock signal. The second symbol period detecting means is activated in response to a pulse signal being output from the pulse generating means, and The number of pulses of the sampling clock signal generated by the generating means is counted by the number of pulses per M symbol periods of the clock signal on the transmitting side, and a count-up pulse signal is generated. A counter that outputs a signal, and the control unit controls the time of the count-up pulse signal of the counter at the time position of the Mth output pulse signal after the certain pulse signal is output from the pulse generation unit. 2. The OFDM receiving apparatus according to claim 1, wherein the oscillation frequency of said clock generating means is controlled so that the positions coincide.