JP2000067573A - Memory provided with arithmetic function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory provided with arithmetic functions in which a layout area is not increased remarkably even when the functions are increased and moreover, which is capable of calculating data whose length is one word or more. SOLUTION: This memory is provided with memory blocks 1, 2, 3,... whose each memory block has word blocks WBA, WBB whose each word block includes word parts WPs capable of being connected each other and capable of reading and writing data among them and the outside respectively and an arithmetic circuit 1b which performs plural kinds of operations by reading data from the word blocks WBA, WBB and which writes these results in either of word blocks WBA, WBB and a control part 110 which makes arithmetic circuits 1b select and execute either of plural kinds of operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory with an arithmetic function applied to, for example, the field of image processing.

[0002]

2. Description of the Related Art A functional memory is an architecture in which a memory and a logic circuit for processing data stored in the memory are integrated. The logic circuit includes a plurality of circuits that perform simple data processing for every several words of the memory, and processes a large amount of data in parallel by operating the plurality of circuits simultaneously. As described above, since the functional memory processes a large amount of data in parallel, there is an advantage that the processing speed is improved as a whole as compared with the configuration in which the memory chip and the processor chip are wired.

The functional memory includes, for example, an associative memory and a memory with an arithmetic function. An associative memory is a memory having a logic circuit that performs a matching operation between data stored in the memory and an external input. Examples of the memory with an arithmetic function include an addition function memory having a logic circuit for adding data between two words of the memory.

[0004] A conventional memory with an arithmetic function will be described below.

<Function of Conventional Memory with Arithmetic Function> A memory with an arithmetic function is a functional memory having a memory block to which an arithmetic circuit is added for every two words of the memory as a basic constituent circuit. This function can be roughly classified into a memory-related function and an arithmetic-related function.

[0006] The memory-related functions are basically the same as those of a normal RAM when viewed from the outside. That is, data is accessed in word units, addresses of all words can be specified, and reading / writing between data of one word stored at the specified address and the outside is possible.
The bit width of one word is, for example, 9 bits, of which one bit indicates positive or negative sign data.

The operation-related function is a function for performing an operation on data stored in the memory.

The operation of the memory with an arithmetic function includes a word mode shown in FIG. 5 and a memory block mode shown in FIG.

FIG. 5 shows the concept of the word mode, in which word portions WPa for storing one word of data are arranged with word numbers. In the word mode, the memory with the arithmetic function is the same as a normal RAM, data is accessed in word units, parallel data cannot be read / written from / to the outside, and only the memory-related functions described above are realized. You.

FIG. 6 shows a memory block mode when one memory block is constituted by two word parts WPa and one arithmetic circuit 1a. Memory block numbers are sequentially assigned to the memory blocks. In the memory block mode, both the memory-related functions and the arithmetic-related functions are realized.

Two word parts WPa of a memory block
Are one for W words and the other for Q words. W
The word is a word that can only read data from the arithmetic circuit 1a. The Q word allows data to be read from and written to the arithmetic circuit 1a.

In one memory block, the arithmetic circuit 1a
Is the data of the W word and the Q word respectively on the data line ML.
1, via ML2. Then, the arithmetic circuit 1a performs an operation (for example, addition) between these data, and writes the operation result to the Q word via the data line ML3.

[0013] By giving one instruction to a plurality of memory blocks at the same time, arithmetic operations on a plurality of memory blocks can be performed in parallel. In other words, SIMD (Single Instruction Stream, Multiple
Data streams).

The arithmetic functions performed by the conventional memory with an arithmetic function include, in addition to the above-described addition function of the W word and Q word data, a subtraction function using a two's complement, and a 2 word complement of the Q word data. Computation function that performs complementation (absolute value calculation function)
was there.

The operation of a conventional memory with an operation function is performed by a hardware circuit, and is performed by sequentially processing data one bit at a time. This is a so-called binary serial addition / subtraction. Hereinafter, the internal configuration and operation of a conventional memory with an arithmetic function will be described.

<Internal Configuration and Operation of Conventional Memory with Operation Function> FIG. 7 is a conceptual diagram showing the entire configuration of a memory with an operation function. The chip 100 is a memory with an arithmetic function. The chip 100 includes a control unit 11, a memory array 12,
The peripheral circuit 13 is included. The peripheral circuit 13 includes an address decoder, a buffer, a sense amplifier, an input / output circuit, a timing control circuit, and the like, which are the same as a normal RAM.
The control unit 11 generates a control signal (arithmetic control signal) for performing parallel control by SIMD on memory blocks (not shown) arranged in an array in the memory array 12. Hereinafter, the internal configuration of the memory block will be described for W words, Q words, and the arithmetic circuit 1a.

<W Word (FIG. 8)> FIG. 8 is a circuit diagram showing the structure of the W word. One W word includes the memory cell circuits MCa1 to MCa9 and the read circuits RC1 and RC2.
And a write circuit WC1.

The memory cell circuits MCa1 to MCa9 have L
They are arranged in order from SB to MSB. In FIG. 8, LS
A memory cell circuit MCa1 of B and a memory cell circuit MCa9 of MSB are shown, and the space between them is omitted. The memory cell circuit MCa9 stores the code data.

Each of memory cell circuits MCa1 to MCa9 includes a cell MC and a transistor MT2. Cell MC
Can be applied to ordinary DRAM cells and SRAM cells. FIG. 8 shows a case where the cell MC is a DRAM cell.
In the DRAM cell, the capacitor C and the transistor MT1
And a so-called one transistor and one capacitor. Therefore, the memory cell circuits MCa1 to MCa1
It can be said that each of a9 is composed of two transistors and one capacitor.

The gate electrode of each transistor MT1 of the memory cell circuits MCa1 to MCa9 is connected to the word line WL.
Are connected in common. Also, the memory cell circuit MCa
1 to MCa9, the capacitor C is connected to the data lines DL1 to DL9 via the transistor MT1.
, While being commonly connected to a common read / write line RL1 via a transistor MT2. Each transistor MT2 of the memory cell circuits MCa1 to MCa9
Are connected to bit lines BL1 to BL9, respectively.

The read circuit RC1 has a common read / write line R
It is connected between L1 and data line ML1 and performs an amplifying function.

The write circuit WC1 has a common read / write line R
It is a transistor connected between L1 and the data line ML1. The gate electrode of the write circuit WC1 has a control signal M
Receive S1.

The read circuit RC2 is composed of an inverter and a transistor connected in series. Readout circuit RC
One end of 2 is connected to a common read / write line RL1, and the other end outputs a code data signal CS. The gate electrode of the read circuit RC2 receives the control signal MS2.

Next, the operation of the W word will be described. The cell MC of the DRAM cells of the memory cell circuits MCa1 to MCa9 operates exactly the same as a normal DRAM. That is, when an address is specified and the word line WL becomes "1" (high potential), the transistors MT1 of the memory cell circuits MCa1 to MCa9 are turned on all at once. Thereby, the memory cell circuits MCa1 to MCa9 are connected to the data lines DL1 to DL
Data can be read from and written to the outside via L9.

On the other hand, the transistor MT2 plays a role of exchanging data between the memory cell circuit MC and the common read / write line RL1. For example, when the bit line BL1 becomes “1”, the transistor MT2 of the memory cell circuit MCa1
Turns on. Thus, data can be read and written between the capacitor C of the memory cell circuit MCa1 and the common read / write line RL1.

However, "1" is sequentially applied to the bit lines BL1 to BL9. Thereby, the memory cell circuit MC
a1 to MCa9 are bit-serial, that is, the common read / write line RL1 and the read circuit RC are sequentially bit by bit.
1 to the data line ML1. In this manner, the data of the W word is read out bit-serial.

Each time data of the memory cell circuits MCa1 to MCa9 is read one bit at a time, the write circuit WC
1 is given a control signal MS1 of "1". When receiving the control signal MS1 of "1", the write circuit WC1 outputs the signal of the data line ML1 to the common read / write line RL1.
Thereby, the data read from the memory cell circuits MCa1 to MCa9 to the data line ML1 is written into the memory cell circuits MCa1 to MCa9 again.

As described above, the W word has a function of amplifying and reading data and a function of rewriting data.

As described above, the memory cell circuit M
Ca9 stores code data. Memory cell circuit MCa
9 to read the code data from the bit line BL9
And a control signal MS2 of "1" is supplied to the read circuit RC2. As a result, the code data is transferred to the read circuit RC without passing through the read circuit RC1.
2, the code data can be read directly to the arithmetic circuit 1a.

<Q Word (FIG. 10)> FIG. 10 is a circuit diagram showing the structure of the Q word. The structure and operation of the Q word are mainly the same as those of the W word. The difference is that the data line ML1 is connected to ML2 and the write circuit WC1
To WC2.

The operation result propagates from the operation circuit 1a to the data line ML3. The result of this operation is W word, Q
Words are sequentially transmitted one bit at a time to the data lines ML1,
The data is sent one bit at a time in synchronization with the reading of data to the arithmetic circuit 1a via the ML2. Each time the operation result is transmitted one bit at a time, a control signal MS3 of "1" is supplied to the write circuit WC2. The write circuit WC2 is
When the control signal MS3 becomes "1", the signal on the data line ML3 is output to the common read / write line RL1. by this,
The operation result from the operation circuit 1a is stored in the memory cell circuit MCa
1 to MCa9.

<Arithmetic Circuit (FIG. 11)> FIG. 11 is a circuit diagram showing a configuration of the arithmetic circuit 1a. It should be noted that the W cell and the Q cell are also illustrated for easy understanding. The W cell is a W word memory cell circuit MCa1 to MCa1.
MCa9. The Q cell is any of the Q word memory cell circuits MCa1 to MCa9.

The basic operation circuit 1a is a 1-bit addition circuit. The arithmetic circuit 1a includes arithmetic function circuits 10, 20,
Includes multiplexer MPX1. A is data transmitted to the data line ML2, and B is output data of the multiplexer MPX1. The arithmetic function circuit 10 receives the data A, B to be operated and the carry data C− and outputs the data A, B, C
-Addition of each other. The operation function circuit 20 stores the operation result of the operation function circuit 10. Multiplexer MPX1
Selects any one of the data of the data line ML1 and the fixed value “0” as the data B.

The arithmetic function circuit 10 includes a multiplexer MP
X2, MPX3, an exclusive OR gate G1, and inverter gates G2 to G5. One input terminal of gate G1 receives data B. The other input terminal of gate G1 receives data C- from arithmetic function circuit 20. The output terminal of the gate G1 is connected to one input terminal of the multiplexer MPX2 and the other input terminal of the multiplexer MPX2 via the gate G2. The output data of the gate G1 is BC.

The output terminal of the multiplexer MPX2 is connected to the control terminal of the multiplexer MPX3 via the gate G3. The control terminal of multiplexer MPX2 receives control signal C0.

One input terminal of the multiplexer MPX3 receives the data A. The other input terminal of multiplexer MPX3 receives data A via gate G4. The output terminal of the multiplexer MPX3 is connected to the data line ML3 via the gate G5. The data transmitted to the data line ML3 is D.

The arithmetic function circuit 20 includes a flip-flop F
F1, inverter gate G6, transistors T1 to T
3 inclusive. The input terminal of the flip-flop FF1 is connected to the data line ML3 via the transistor T2, the gate G6, and the transistor T1, and receives the control signal CS0 via the transistor T3. Flip-flop FF1
Is output data C-. The gate terminal of transistor T1 receives data BC. The gate terminal of transistor T2 receives control signal S2. Transistor T3
Receives the control signal S1. C + is data written to the flip-flop FF1.

One input terminal of the multiplexer MPX1 is connected to the data line ML1. Multiplexer M
The other input terminal of PX1 receives a fixed value "0". The control terminal of multiplexer MPX1 receives control signal P1.

Next, the operation of the arithmetic circuit 1a will be described. First, data A to be operated is data read from the Q cell. On the other hand, data B is
PX1 is data obtained by selecting one of the data of the W cell and the fixed value “0” according to the control signal P1.

In the drawing, "0" and "1" are drawn in the multiplexer. This indicates the signal level applied to the control terminal of the multiplexer. For example, in the multiplexer MPX1, the control signal P1 is "
When "1", data from the W cell is selected, and when "0", a fixed value "0" is selected.

Next, the arithmetic functions performed by the arithmetic circuit 1a include:
As described above, an addition function, a subtraction function, and an absolute value calculation function can be performed. Hereinafter, the operation will be described for each function.

<Addition Function> In the addition function, the control signal P
1, the control signal C0 is set to "1". Since the control signal P1 is "1", the data B is the data of the W cell.

Immediately after the start of the addition function, "0" is written as the initial value of the data C- of the flip-flop FF1. To write the initial value, set the control signal S1 to "1".
To turn on the transistor T3, and the control signal C of "0"
This is done by giving S0. Also, with the addition function,
The control signal CS0 is obtained, for example, by reading code data from a Q word and a W word, and obtaining an exclusive OR of both.

In the addition function, data A and B and carry data C- are added. The calculation result is sum data D and carry data C +. The data D is the arithmetic function circuit 10
And the data C + is generated in the arithmetic function circuit 20. Data D and data C + are written to Q cell and flip-flop FF1, respectively.

In the arithmetic function circuit 10, the gate G1 performs an exclusive OR operation on the data B and the data C-. Since the control signal C0 is "1", the output data of the gate G2 is selected. The output data BC from the gate G1 is
The signal propagates to the control terminal of the multiplexer MPX3 via the multiplexer MPX2 and the gate G3. That is, in the addition function, the output data of the gate G3 has the same value as the data BC.

The multiplexer MPX3 outputs the data BC
One of the data A and the inversion of the data A is selected according to “1” and “0” of the data. Multiplexer MPX3
Is inverted by the gate G5 to become data D. Data D is written to Q cell via data line ML3. When the data BC is “1”, the data D is the inverse of the data A, and when the data BC is “0”, the data D is the data A.

Next, in the arithmetic function circuit 20, when the data BC is "1", the transistor T1 is turned on, and the multiplexer MPX3, the gate G5, the transistor T1,
Data A is written to flip-flop FF1 via gate G6 and transistor T2. Therefore, the data BC
Is “1”, data C + is data A.

When the data BC is "0", the transistor T1 turns off and the output potential of the gate G6 maintains the same level. Thus, when the data BC is "0", the data C + has the same value as the data C-.

Table 1 summarizes the above logic.
Are shown in Table 2.

[0050]

[Table 1]

[0051]

[Table 2]

As described above, the arithmetic circuit calculates the 1-bit data from the W cell, the 1-bit data from the Q cell, and the data C written in the flip-flop FF1.
−, And sum D and carry C + are Q cells,
Write to flip-flop FF1. This process is performed every time data is read out one bit at a time from the W word and the Q word. As a result, the Q word is overwritten with a combination of the data of the Q word and the data of the W word.

<Subtraction Function (BA)> The subtraction function is performed by addition to which a two's complement is applied. That is, in the addition function, the initial value of the data C− is changed to “1” and the control signal C−
0 may be changed to “0”. As a result, the value obtained by subtracting the data of the Q word from the data of the W word is overwritten on the Q word.

By changing the control signal C0 to "0",
The output data of the gate G3 is the inverse of the data BC,
The logic changes from Table 2 to Table 3.

[0055]

[Table 3]

<Absolute Value Calculation Function> The absolute value calculation function is a special case of the subtraction function. That is, the control signal P1 may be changed to “0” in the subtraction function. Since the control signal P1 is "0", the data B has a fixed value "0". As a result, 0-A is performed, and the two-complement complement of data A is overwritten on the Q word.

[0057]

As described above, the conventional memory with an arithmetic function basically has only an addition function, so that its use is limited.

For example, there is an image processing field as an application of the memory with an arithmetic function. Various operations are required in this field. For example, calculation between pixel data and external common data (external common input data), accumulation required to obtain an average of the calculation results, and matching search required to obtain the same pixel distribution , Size comparison and accumulation necessary for obtaining a histogram. Therefore, a conventional memory with an arithmetic function having only an addition function cannot sufficiently cope with the image field. Particularly, in the accumulation, since the operation result becomes large, it is not possible to sufficiently cope with the case where the length of one word is, for example, 9 bits.

Then, it is conceivable that the arithmetic circuit 1a may be provided with more arithmetic functions other than the addition function, and one word may be made 10 bits or more. However, there is a problem that the layout area is significantly increased.

The present invention has been made to solve the above-described problems. Even if the number of functions is increased, the layout area does not increase significantly, and the operation of data having a length of one word or more can be performed. It is an object of the present invention to obtain a memory with an arithmetic function that can be performed.

[0061]

According to a first aspect of the present invention, there is provided a data processing apparatus comprising: a plurality of word portions each including a plurality of word portions which can be connected to each other and which can read and write data with the outside; A memory block, each of which has an operation unit that reads the data from the plurality of word blocks, performs a plurality of operations, and writes the result in any one of the plurality of word blocks; Any one of the above-mentioned types of operations for the operation unit
And a control unit for selecting and executing one.

[0062] In the means for solving problems according to claim 2 of the present invention, the arithmetic unit is configured to select one of data written in the plurality of word blocks and data directly input from the outside to itself. Is included.

In the means for solving problems according to claim 3 of the present invention, a plurality of the memory blocks are provided, and an operation result in one of the memory blocks is determined by one of the one of the memory blocks and the other of the memory blocks. Selected and written.

A switch according to claim 4 of the present invention, wherein a switch for separating one of the plurality of word sections from one of the plurality of word blocks from the word block, and the one of the plurality of word sections are provided. And a common read / write line for connecting to the other word blocks.

[0065] In the means for solving problems according to claim 5 of the present invention, the operation section executes the operation on the data of the word block one bit at a time in order, and executes the specific operation during the execution of the operation. If the result is obtained, the apparatus further includes an operation result storage unit for holding the operation result until the operation is completed.

[0066] In the means for solving problems according to claim 6 of the present invention, the operation section executes the operation on the data of the word block one bit at a time in order, and executes the specific operation during execution of the operation. If a result is obtained, a first flip-flop for holding the operation result until the operation is completed, and if the specific operation result is obtained during execution of the operation, the first flip-flop is read out to the operation unit. An operation result storage unit including a second flip-flop for holding the specific data of the data until the operation is completed is further included.

[0067] In the means for solving problems according to claim 7 of the present invention, the operation result storage section constitutes an SRAM.

[0068]

Next, a memory with an arithmetic function according to an embodiment of the present invention will be described.

<Function of Memory with Arithmetic Function of Embodiment> A memory with an arithmetic function of the embodiment of the present invention is a functional memory having a memory block to which an arithmetic circuit is added for every four words as a basic configuration circuit. The functions of the memory with an arithmetic function are roughly classified into a memory-related function and an arithmetic-related function.

The memory-related functions of the memory with an arithmetic function according to the embodiment are obtained by adding the following contents to the conventional one. First, it is possible to connect two words in one memory block. The case where two words are connected is called a double length operation mode, and the case where they are not connected is called a single length operation mode.
For example, it is possible to selectively switch between a single-length operation mode of a total of 9 bits including a code of 1 bit and a double-length operation mode of a total of 17 bits including only a code of 1 bit. This switching is specified, for example, when the operation of the memory with the arithmetic function is started.

The calculation-related functions of the embodiment are different from those of the related art in that various calculation functions that can sufficiently cope with image processing are added.

The memory with an arithmetic function according to the embodiment has a word mode and a memory block mode. The word mode is the same as the conventional one, and the memory-related functions can be realized, as shown in FIG. On the other hand, in the memory block mode, both the memory-related function and the arithmetic-related function can be realized, as shown in FIG. The memory block mode includes the double-length operation mode and the single-length operation mode described above.

In FIG. 1, WP is a word section of the embodiment, 1b is an arithmetic circuit (arithmetic section) of the embodiment, and 110 is a control section of the embodiment. The overall configuration of the memory with an arithmetic function is as shown in FIG. 7, and the control unit 110 corresponds to the control unit 11 in FIG. 7, and the memory blocks arranged in an array in the memory array 12 are different from those in the related art.

The word part WP is the same as the word part WP of the prior art.
As in a, data can be read from and written to the outside. The word part WP is composed of the word parts QA1, QA2, QB
1 and QB2.

The word sections QA1 and QA2 are connected to each other via a common read / write line RL1a. The common read / write line RL1a is connected to the arithmetic circuit 1b via a read / write circuit RWCa (write unit). The word parts QA1, QA2 and the read / write circuit RWCa constitute a word block WBA.

The word parts QB1 and QB2 are connected to each other via a common read / write line RL1b. The common read / write line RL1b is connected to the arithmetic circuit 1b via a read / write circuit RWCb (write unit). The word sections QB1 and QB2 and the read / write circuit RWCb form a word block WBB.

The left side of FIG. 1 shows the memory block numbers sequentially assigned to the memory blocks. One memory block includes one word block WBA, one word block WBB, and one arithmetic circuit 1b.

The read / write circuits RWCa, RWCb are:
The word part QA1, QA2, QB1, QB2 is processed by the arithmetic circuit 1
b enables reading and writing of data. Therefore, it can be said that the word portions QA1, QA2, QB1, and QB2 are all Q words.

The control unit 110 generates a control signal S for performing SIMD parallel control on all memory blocks. The control signal S is a general term for a control signal described later. Then, the control unit 110 outputs the control signal S to all the memory blocks.

As described above, the arithmetic circuit 1b includes a plurality of types of arithmetic functions to be performed on the data A and B to be operated in order to sufficiently cope with the image processing field. For example, in addition to the conventional addition function, subtraction function (BA) and absolute value calculation function, there are subtraction function (AB), logical operation of A and B, 1-bit shift, match search, and magnitude comparison. The logical operation is, for example, a logical product (AND) of A and B, a logical sum (OR), an exclusive logical sum (EXOR), an exclusive negative logical sum (EXNOR), an inversion of A and B (NOT), A, B B itself (Through).

The operation circuit 1b calculates the data A and B to be operated.
To any one of the plurality of arithmetic functions
The control result is selected and executed by the control of 0, and the operation result is output to one of the word blocks WBA and WBB.

In addition to the operation function of the operation circuit 1b, the following <selection function of data A and B to be operated>, <movement function between word blocks>, <selection switching between double length operation mode and single length operation mode> Function, <1 memory block shift function>, <1 word data shift function>. This makes it possible to cope with various fields.

First, the outline of these functions will be described, and then the configuration for realizing these functions will be described.

<Selection Function of Data A and B to be Operated> The operation circuit 1b is provided with the data from the word part WP and the word part W
Any one of data (external common input data X) and a fixed value directly input from outside without passing through P can be selected as data A or B.

The function of selecting an operation object will be described in more detail. Table 4 shows the calculation according to the combination of the calculation targets. Since the fixed value can be considered in the same manner as the external common input data X, it is omitted in Table 4.

[0086]

[Table 4]

According to the function of selecting the data A and B, each operation function of the operation circuit 1b is roughly divided into two types of operation modes of internal operation and external operation. The internal operation is a case where the operation target is all word parts. The operation result is overwritten on any one of the word parts WP subjected to the operation. The external operation is a case where a part of the operation target is the external common input data X.

In the case of the internal operation, the operation result is overwritten on one of the word parts WP subjected to the operation.
For example, in the combination of QA1-QB1, the operation result is written to one of word parts QA1 and QB1.

On the other hand, in the case of an external operation, one of the word portion WP subjected to the operation and the word portion WP having the same number as the word portion WP is overwritten. For example, in the combination of external operations QA2-X,
The operation result is written into one of the word parts QA2 and QB2.

<Move Function Between Word Blocks> A switch SW is provided on each of the common read / write lines RL1a and RL1b, the two switches SW open the common read / write line, and the word part QB1 and the memory block WB are opened.
A read / write circuit RWCa and common read / write line RL
1c, QB1-QB
Two combinations can be included.

<Selection Switching Function between Double Length Operation Mode and Single Length Operation Mode> The single length operation mode and the double length operation mode described above can be selectively switched.

In the single-length operation mode, data to be operated is data from one word part WP. Alternatively, one is data from one word portion WP and the other is external common input data X. The operation result is written into one word part WP. For example, in the case of QA1-QB2 in Table 4, the data from the word part QA1 and the word part QB2
Are the data to be operated, and the operation result is written into one of the word parts QA1 and QB2.

On the other hand, in the double length operation mode, the word portion QA
1 and QA2 are connected to each other to form word portions QB1 and QB2.
Are connected to each other. The data DA to be operated is data from the word parts QA1 and QA2 connected to each other,
Further, the data DB to be operated is data from the word parts QB1 and QB2 connected to each other. Alternatively, data DA is data from word parts QA1 and QA2 connected to each other, and data DB is external common input data X. Alternatively, data DA is external common input data X, and data DB is data from word parts QB1 and QB2 connected to each other. The operation result is
Word parts QA1, QA2 connected to each other, or
Data is written to one of the word parts QB1 and QB2 connected to each other.

The single-length operation mode can be any of the combinations of the operation objects in Table 4. Double length operation mode is Q
Combination of A1, QB1, QA2, QB2, Q
Combination of A1, QA2, X, QB1, QB
Any combination of 2 and X is possible. In the case of QA1-QB2 and QA2-QB1 in Table 4, for example, if each of the word portions QA1 and QB1 includes code data, data from Q cells including code data and data from Q cells not including code data Therefore, the double length calculation mode is not performed. Also, QB1-
In the case of QB2, since the word parts QB1 and QB2 are included in the same word block, the double length calculation mode is not performed.

<1 Memory Block Shift Function> The word portions QB1 and QB2 of the next lower memory block (lower adjacent block) having the smaller memory block number can be used as its own word portions QB1 and QB2 (adjacent block). Reading function). Further, the operation result can be written in the word portions QA1 and QA2 of the memory block (upper adjacent block) adjacent to the memory block number which is larger by one (adjacent block write function). Adjacent block read function,
The adjacent block writing function is performed by the control unit 110 on all memory blocks in parallel. As a result, the same result as shifting data by one memory block is obtained.

<One Word Data Shift Function> Arithmetic Circuit 1
b, which is a kind of arithmetic function.
Shift by a bit. The bit shift includes a left shift and a right shift. The left shift is shifted by one bit from the MSB. The right shift is shifted by one bit from the LSB. The shift is performed in units of one word of the word part QA1 or QA2, or in units of two words of the word parts QA1 and QA2 connected to each other.

Next, the internal structure of a word block will be described with reference to FIG. FIG. 1 shows the word block WBA or W
BB is shown. Q1, Q2, WRC and RL1 are each Q
A1, QA2, WRCa, RL1a, or QB
1, QB2, WRCb, and RL1b.

The read / write circuit RWC of FIG. 2 includes read circuits RC1 and RC2 and write circuits WC1 to WC3.

As the read circuits RC1 and RC2 and the write circuits WC1 and WC2, those described in the related art can be used, and the description is omitted.

The write circuit WC3 has a common read / write line R
This is a transistor connected between L1 and the data line ML4. The gate electrode of the write circuit WC3 has a control signal M
Receive S6. Data line ML4 is a word block WBB
And the lower adjacent block. The operation result of the operation circuit 1b propagates to the data line ML4. This operation result is sent one bit at a time in synchronization with the word blocks WBA and WBB reading data to the operation circuit 1b via the data lines ML1 and ML2 one bit at a time. Each time the operation result is sent one bit at a time, a control signal MS6 of "1" is given to the write circuit WC3. The write circuit WC3 outputs the control signal MS6 "
When the signal becomes "1", the signal on the data line ML4 is output to the common read / write line RL1.
Can write data of the data line ML4 to the common read / write line RL1.

As described above, the read / write circuit RWC
Are controlled by the control unit 110 so that the data lines ML1 and M
The data propagating to any one of L3 and ML4 is selected and written to word portions Q1 and Q2.

Further, an example of the read circuit RC1 will be described with reference to FIG. The read circuit RC1 includes transistors R1 to R4 and a gate RG1. The transistors R1 to R3 are connected in series in this order between a high potential and a ground potential. Common read / write line RL2
Is connected to the point where the transistors R1 and R2 are connected. The transistor R4 is connected between the ground potential and the common read / write line RL1. The gate RG1 is connected between the read line RL2 and the data line ML1.

Before data is read out to the common read / write line RL1, the control signals MS4 and MS5 are set to "
1 "and" 0 ", whereby the transistor R4
Is on, and the transistor R3 is off. Since the transistor R4 is on, the common read / write line RL1 is precharged to the ground potential. Common read / write line RL
2 is precharged to "1".

Next, while reading data from the word portion Q1 or Q2 to the common read / write line RL1, the control signal M
S4 and MS5 are set to "0" and "1", respectively. As a result, the transistors R1, R4, and R3 are turned off, off, and on, respectively. The transistor R2 is turned on or off depending on the potential of the common read / write line RL1. The read line RL2 precharged in advance may or may not be discharged according to the ON or OFF state of the transistor R2. Since the potential of the read line RL2 is the inverse of the data of the common read / write line RL1, the gate RG1 is connected to the common read / write line RL1.
Is inverted and output to the data line ML1.

FIG. 3 shows an example of the internal configuration related to the word parts Q1 and Q2. WL1 and WL2 are adjacent word lines. The data lines DL1 to DL9 are connected to the word parts Q1,
Commonly connected to Q2. The read lines RL1 of the word parts Q1 and Q2 are connected to each other at a connection point Z. The bit lines BL1 of the word portions Q1 and Q2 are connected to each other. The same applies to bit lines BL2 to BL9. The word selection lines WBL1 of the word section Q1 are commonly connected to each other. The word selection lines WBL2 of the word section Q2 are commonly connected to each other.

The word sections Q1 and Q2 include memory cell circuits MC1 to MC9, respectively. The memory cell circuits MC1 to MC9 of the word sections Q1 and Q2 are arranged in order from LSB to MSB. FIG. 3 shows the memory cell circuit MC1 of the LSB and the memory cell circuit MC9 of the MSB, and a part between them is omitted. In single length mode,
The memory cell circuit MC9 of each of the word parts Q1 and Q2 stores code data. In the case of the double-length mode, for example, only the memory cell circuit MC9 of the word section Q1 stores code data.

Each of memory cell circuits MC1 to MC9 has
It includes a cell MC and transistors MT2 and MT3. As the cell MC, a normal DRAM cell, SRAM cell, or the like can be applied. FIG. 3 shows a case where the cell MC is a DRAM cell. In a DRAM cell, a capacitor C and a transistor M
T1 and one capacitor including one transistor. Therefore, the memory cell circuits MC1 to MC
It can be said that each of C9 is constituted by three transistors and one capacitor.

Memory cell circuits MC1-M of word section Q1
The gate electrodes of the transistors MT1 of C9 are commonly connected to the word line WL1. The gate electrodes of the transistors MT1 of the memory cell circuits MC1 to MC9 of the word section Q2 are commonly connected to a word line WL2.

The memory cell circuits M of the word sections Q1 and Q2
In each of C1 to MC9, the capacitor C is connected to the data line DL1 to DL9 via the transistor MT1.
, While being commonly connected to a common read / write line RL1 via transistors MT2 and MT3.

Memory cell circuit M of word parts Q1 and Q2
The gate electrodes of the transistors MT2 of C1 to MC9 are connected to the bit lines BL1 to BL9, respectively.

Memory cell circuits MC1 to MC of word section Q1
The gate electrode of each transistor MT3 of C9 is
Commonly connected to word select line WBL1. The gate electrode of each transistor MT3 of the memory cell circuits MC1 to MC9 of the word part Q2 is connected to the word selection line WBL.
2 are connected in common.

Next, the operation of word sections Q1 and Q2 will be described. Memory cell circuit MC1 of word parts Q1 and Q2
Cell MC of the DRAM cells of MC9 to MC9 is a normal DRAM
Works exactly the same as. That is, when an address is specified and the word line WL1 becomes "1", the transistors MT1 of the memory cell circuits MC1 to MC9 of the word section Q1 are turned on all at once. As a result, the memory cell circuits MC1 to MC9 of the word section Q1 can read and write data between the data lines DL1 to DL9 and the outside. On the other hand, when an address is specified and the word line WL2 becomes "1", the transistors MT1 of the memory cell circuits MC1 to MC9 in the word section Q2 are turned on all at once. by this,
The memory cell circuits MC1 to MC9 of the word part Q2 can read and write data between the memory cells via data lines DL1 to DL9 and the outside.

The transistor MT2 is connected to the memory cell circuit MC
And the transistor MT3. For example, when the bit line BL1 becomes "1",
The transistor MT2 of the memory cell circuit MC1 of each of the word parts Q1 and Q2 is turned on. Thereby, data can be read and written between the capacitor C of the memory cell circuit MC1 of each of the word parts Q1 and Q2 and the transistor MT3.

The transistor MT3 is connected to the transistor MT2
And the common read / write line RL1. When the word selection line WBL1 becomes "1",
The transistors MT3 of the memory cell circuits MC1 to MC9 in the word section Q1 are turned on all at once. Thus, data can be read and written between the transistor MT2 of each of the memory cell circuits MC1 to MC9 of the word part Q1 and the common read / write line RL1.

Next, for example, consider a case where data is read from the capacitor C of the memory cell circuit MC of the word section Q1 to the common read / write line RL1. Bit lines BL1 to BL9
Among them, only BL9 is set to "1". Word select line WB
Of L1 and WBL2, only WBL1 is set to "1".
As a result, the transistors MT2 and MT3 of the memory cell circuit MC1 in the word section Q1 are both turned on. Thereby, the memory cell circuit MC of the word portion Q1
1 to the common read / write line RL1.

The word parts QA1, QA2, QB1,
QB2 can be arbitrarily selected independently of each other by a word selection line.

As described above, one of the memory cell circuits MC1 to MC9 in the word section WP is selected by the bit line, and the word sections QA1, QA2, Q2 are selected by the word selection line.
By selecting one of B1 and QB2, data can be read from a desired Q cell to the common read / write line RL1 separately from the data lines DL1 to DL9.

As described above, the switches SW,
By providing the common read / write line RL1c, a combination of QB1 and QB2 can be included in the internal operation. That is, the switch SW is turned off, and the word part QB1 is separated from the word block WBB. The separated word part QB1 is connected to the word block WBA via the common read / write line RL1c,
A will be included. In this state, the word sections QB1 and QB2 are selected by the word selection line and the word sections QA1 and QA2 are not selected, so that the data of the word sections QB1 and QB2 are read and written by the read / write circuit R
The data is read out to the arithmetic circuit 1b via WCa and RWCb. As a result, the arithmetic circuit 1b can perform an operation between the word parts QB1 and QB2 in the same word block WBB.

In the case of the double-length operation mode, for example, the word sections QA1 and QB1 are selected by a word selection line, and the memory cell circuits MC1 to MC9 of the word sections QA1 and QB1 are changed from LSB to MSB by bit lines. select. Next, a word section QA2 is connected by a word selection line.
QB2 is selected, and the word section QA2,
Each of the memory cell circuits MC1 to MC9 of QB2 is set to L
Select from SB to MSB. This makes it possible to perform an operation on double-length data.

Next, the case of performing accumulation will be described. In this case, the operation is performed in the double length calculation mode. For example, the result of the accumulation is stored in the word parts QA1 and QA2, that is, the word block WB.
Suppose to write to A. The number to be added is externally written to QB1 and QB2, that is, the word block WBB via a word line. The arithmetic circuit 1b includes word blocks WBA, WB
The data of B are added to each other, and the result is written to the word block WBA. In this way, the number given from the outside can be accumulated and written into the word block. Since the accumulation is performed in the double length operation mode, for example, when the length of one word is 9 bits, the operation result can correspond to 17 bits.

FIG. 4 shows the internal configuration of the arithmetic circuit 1b according to the embodiment. In addition, in order to make the explanation easy to understand, QA
Also shown are cells (Q cells of word block WBA) and QB cells (Q cells of word block WBB). The arithmetic circuit 1b is obtained by adding an arithmetic function circuit 30 for logical operation, an arithmetic function circuit 40 for matching search, and an arithmetic function circuit 50 for magnitude comparison to the conventional arithmetic circuit 1a.

First, the configuration of the arithmetic function circuit 30 will be described. One input terminal of the OR gate G7 is connected to the output terminal of the multiplexer MPX2. The other input terminal of the gate G7 is connected to the output terminal of the multiplexer MPX3. The transistor T4 is connected between the output terminal of the gate G7 and the data line ML3. The gate electrode of transistor T4 receives control signal C1. One input terminal of the AND gate G8 is connected to the output terminal of the gate G3. The other input terminal of the gate G8 is connected to the output terminal of the multiplexer MPX3. The transistor T5 is connected between the output terminal of the gate G8 and the data line ML3. The gate electrode of transistor T5 receives control signal C2. The transistor T6 is connected between the output terminal of the gate G5 and the data line ML3.
Is connected between. The gate electrode of transistor T6 receives control signal C3. The transistor T7 is connected between the output terminal of the multiplexer MPX3 and the data line ML3. The gate electrode of transistor T7 receives control signal C4.

Next, the configuration of the arithmetic function circuit 40 will be described. The transistor T8 is connected in parallel with the transistor T1. The gate electrode of transistor T8 receives control signal C6. One input terminal of the multiplexer MPX6 is connected to the output terminal of the gate G6. The other input terminal of the multiplexer MPX6 is connected to the input terminal of the gate G6. One input terminal of the NAND gate G9 is connected to the output terminal of the flip-flop FF1. The other input terminal of the gate G9 is connected to a control signal C8.
Receive. One input terminal of the AND gate G10 is connected to the output terminal of the gate G9. The other input terminal of gate G10 receives control signal S2. The transistor T9 is connected to the output terminal of the flip-flop FF1 and the data line M
L5. The gate electrode of transistor T9 receives control signal S4.

Next, the configuration of the arithmetic function circuit 50 will be described. The transistor T10 is connected between the data line ML3 and the input terminal of the flip-flop FF2. The gate electrode of the transistor T10 is connected to the output terminal of the gate G10. The transistor T11 is connected between the output terminal of the flip-flop FF2 and the data line ML6. The gate electrode of transistor T11 receives control signal S4.

The flip-flops FF1 and FF2 constitute an operation result storage unit.

The arithmetic circuit 1b includes a three-input multiplexer MPX5 (selection unit). Multiplexer MP
The three inputs X5 are the external common input data X, the data of the QA cell in the same memory block, and the fixed value "0". The multiplexer MPX5 supplies one of the three inputs to the control signal P
3 and P4 and output as data A.

The multiplexer MPX1 of the arithmetic circuit 1b
The (selection unit) has four inputs. The four inputs of the multiplexer MPX1 are external common input data X, QB cell data from the upper adjacent block, QB cell data in the same memory block, and a fixed value “0”. Multiplexer MPX
1 selects one of the four inputs according to the control signals P1 and P2 and outputs it as data B.

Next, the operation of the arithmetic circuit 1b will be described. First, the multiplexer MPX1 selects one of the four inputs as data B according to the control signals P1 and P2. The multiplexer MPX5 supplies one of the three inputs to the control signal P3.
Select as data A according to P4. Table 5 shows combinations of data selected in the embodiment. In addition,
In Table 5, * indicates that it is optional.

[0129]

[Table 5]

The operation circuit 1b performs an operation on the data A and B, and outputs the QA cell, the QB cell and the Q of the upper adjacent block.
Data D is output to the A cell. The QA + in FIG.
Is the QA cell of the upper adjacent block, and QA- is the QA cell of the lower adjacent block.

The write circuit of the QA cell, QB cell, and QA + cell operates so that data D is written to one of the QA cell, QB cell, and QA + cell.

As shown in Table 6, the types of arithmetic functions performed on data A and B include addition, subtraction (BA),
Subtraction (AB), logical operation (AND, OR, EXOR,
EXNOR, NOT, Through), bit match search, and magnitude comparison. The calculation function of the calculation circuit 1b is selected by the control signals C0 to C8.

[0133]

[Table 6]

The operation will be described below for each operation function. Note that the combination of the control signals C0 to C8 shown in Table 6 is an example, and the condition described in each operation may be satisfied.

<Addition> Control signals C0, C3, C5, C7
Is set to “1”, and the control signals C1, C2, C4, C6,
Set C8 to "0". Also, flip-flop FF
"1" is written into "1" as an initial value. In this case, the operation is the same as the conventional addition.

<Subtraction (BA)> Control signals C3, C5,
C7 is set to "1" and control signals C0, C1, C2, C
4, C6 and C8 are set to "0". Further, "1" is written into the flip-flop FF1 as an initial value. In this case, the operation is similar to that of the conventional subtraction (BA).

<Subtraction (AB)> Control signals C0, C3,
C5 is set to "1" and the control signals C1, C2, C4, C
6, C7 and C8 are set to "0". Also, "0" is written into the flip-flop FF1 as an initial value. The logic in this case is as shown in Table 7, and the subtraction of AB can be performed.

[0138]

[Table 7]

<Logical operation> In the logical operation, since the carry is not relevant, the control signal C5 is set to "0". As a result, the output data of the gate G1 becomes the data B. Less than,
The description will be given for each type of logical operation.

Logical operation: AND. Control signals C0, C2
Is set to “1”, and the control signals C1, C3, C4 are set to “0”.
Should be set to.

Logical operation: OR. What is necessary is just to set the control signal C1 to "1" and set the control signals C0, C2, C3, C4 to "0".

Logical operation: EXOR. Control signal C4
1 may be set and the control signals C0 to C3 may be set to "0".

Logical operation: EXNOR. Control signals C0, C
4 may be set to "1" and the control signals C1 to C3 may be set to "0".

Logical operation: NOT. In NOT, data D is obtained by inverting data A. The control signal C3 is set to "1", the control signals C0 to C2 and C4 are set to "0", and the data B is set to a fixed value "0", that is, the control signals P1 and P2 are set to "1" and "0", respectively. "

Logic operation: Through Through In data through, data A is changed to data D. The control signal C4 is set to "1", and the control signals C0 to C3 are set to "1".
0 ", and the control signals P1 and P2 are set to"
What is necessary is just to set it to 1 "," 0 ".

<Match Search> In the match search, EXOR is used to determine whether all bits match or not by using the flip-flop FF1.
To save. Therefore, the control signals C4 and C8 may be set to "1", and the control signals C0 to C3 and C5 may be set to "0". Also, "0" is written into the flip-flop FF1 as an initial value.

If data A and data B match,
The data D is "0", and the value stored in the flip-flop FF1 remains the initial value "0". Data A
If data and data B do not match, data D is "1" and "1" is written to flip-flop FF1. When "1" is written to the flip-flop FF1,
The data C- becomes "1", the output data of the gate G10 becomes "0", and the transistor T2 turns off. When the transistor T2 is turned off, data writing to the flip-flop FF1 is prohibited thereafter. That is, if the presence or absence of a match (specific operation result) is obtained during execution of the operation, the flip-flop FF1 holds the operation result until the selection operation ends. Therefore, at the time when the match search is completed, the presence or absence of a match is stored in the flip-flop FF1. Control signal S4
If it is set to “1”, the presence or absence of a match can be seen from the data line ML5.
See which bits are mismatched.

<Size comparison> Size comparison is an operation for comparing the sizes of data A and B. In the magnitude comparison, the initial value “0” is written to the flip-flop FF1, and the control signal C
8, S2 is set to "1" to turn on the transistors T2 and T10. In this state, the phases 1 and 2 are continuously performed for each bit to be operated. In Phase 1, Throu
gh, and writes the data A into the flip-flop FF2. In phase 2, a match search is performed.

For example, consider a case where the data of the word part QA1 to be operated on is "+00001000" and the data of the QB1 to be operated is "+00000001". In this case, the arithmetic circuit 1b is converted from the word blocks WBA and WBB.
, Data is sequentially read from the MSB one bit at a time.
When the data A and B are both "0", the flip-flop FF1 remains at the initial value. However, data A,
When B is “1” and “0”, respectively, “1” is written in the flip-flop FF1, and the flip-flop FF1 is written.
Writing of data to the memory is prohibited thereafter. At the same time, the transistor T10 is also turned off, so that data writing to the flip-flop FF2 is prohibited thereafter. That is, the flip-flop FF2 holds “1” of the data A until the operation is completed. Word part QA1, QB1
After reading all the bits from the control signal S of "1"
4 to turn on the transistors T9 and T11, and from the data lines ML5 and ML6,
1. Look at the data written to FF2. By knowing that "1" is written in both flip-flops FF1 and FF2, (data A of word part QA1)> (data B of word part QB1) is known. Also,
"1" and "1" are applied to the flip-flops FF1 and FF2, respectively.
If “0” is written, A <B, and if “0” is written to flip-flop FF1, A = B
It is.

According to the above-described embodiment, arithmetic circuit 1b is simply provided with two word sections WPa as in the prior art.
Is not connected to the word block WBA,
Connected to WBB. Since each word block has two word portions, the arithmetic circuit 1b is provided every four words.
Is provided, and the number of arithmetic circuits 1b is reduced as compared with the conventional case. Since one word block includes a plurality of word parts, data in word block units is twice as long as data in word part units. Therefore, even if the arithmetic functions of the arithmetic circuit 1b and the functions such as the above-mentioned <function of selecting data A and B to be operated> are increased, the number of arithmetic circuits 1b is reduced, and the layout area is greatly increased. It is also possible to perform double-length data calculations without using them.

The arithmetic function of the arithmetic circuit 1b includes a logical operation and an addition, so that, for example, the image processing can be applied to an image processing field in which pixel data is processed in parallel. The memory with an arithmetic function according to the embodiment is effective in the field of processing such data in parallel.

The arithmetic circuit 1b is connected to the word block WB
A, multiplexer MPX for selecting any one of data written to A, WBB and external common input data X
1 and MPX5, it is possible to perform an arithmetic operation by combining the external common input data and the data of the word blocks WBA and WBB.

Further, for example, the operation result of the memory block having the number 1 is determined by the memory block itself and the data line ML.
4 is written to one of the memory blocks having the number 2. As a result, the operation result can be shifted between the memory blocks.

Further, flip-flops FF1 and FF2
Constitute an SRAM, the operation results of all the memory blocks can be stored in the SRAM.

[0155]

According to the first aspect of the present invention, the operation unit is connected to a plurality of word blocks instead of being simply connected to two word units as in the related art. That is, (the number of word blocks connected to the operation unit) ×
Since an arithmetic unit is provided for each (number of word parts in one word block), the number of arithmetic units is reduced as compared with the conventional case. Therefore, even if the number of arithmetic functions is increased, the number of arithmetic units is reduced, so that the layout area does not significantly increase. Further, since one word block includes a plurality of word parts that can be connected to each other, data of a digit number larger than one word length can be handled in one word block. Therefore, even if the operation result of the data to be operated becomes longer than the word length, it can be stored.

According to the second aspect of the present invention, it is possible to perform an arithmetic operation by combining data directly input from the outside to the arithmetic unit with data of a word block.

According to the third aspect of the present invention, the operation result can be shifted between the memory blocks.

According to the fourth aspect of the present invention, it is possible to perform an operation between word parts in the same word block.

According to the fifth aspect of the present invention, for example, an operation of a match search can be realized.

According to the sixth aspect of the present invention, for example, a magnitude comparison operation can be realized.

According to the seventh aspect of the present invention, the operation results of all the memory blocks can be stored in the SRAM.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an example of a memory with an arithmetic function (block mode) according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a word block according to the embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a word section according to the embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an example of an arithmetic circuit according to the embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a word mode.

FIG. 6 is a conceptual diagram showing a conventional memory with an arithmetic function (block mode).

FIG. 7 is a conceptual diagram showing a configuration of a functional memory.

FIG. 8 is a circuit diagram showing a conventional W word.

FIG. 9 is a circuit diagram illustrating an example of a read circuit (sense amplifier).

FIG. 10 is a circuit diagram showing a conventional Q word.

FIG. 11 is a circuit diagram showing a conventional arithmetic circuit.

[Explanation of symbols]

WP word section, RL1a, RL1b, RL1c common read / write line, RC1 read circuit, WC1-WC3 write circuit, 10-50 arithmetic function circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/34 371H F-term (Reference) 5B015 HH01 HH03 JJ37 KB91 PP01 5B024 AA07 BA29 CA07 CA15 CA16 5B057 CH04 CH11 5B060 CB00 MM20

Claims (7)

[Claims] 1. A plurality of word blocks, each including a plurality of word portions that are connectable to each other and are each capable of reading and writing data to and from the outside, and a plurality of word blocks read from the plurality of word blocks. A memory block, each of which has an operation unit for performing a type of operation and writing the result to one of the plurality of word blocks; and selecting one of the plurality of types of operation for the operation unit A memory with an arithmetic function, comprising: 2. The operation unit according to claim 1, wherein the operation unit includes a selection unit that selects one of data written in the plurality of word blocks and data directly input from the outside to itself. A memory with an arithmetic function as described. 3. The memory block according to claim 1, wherein a plurality of the memory blocks are provided, and an operation result in one of the memory blocks is written by selecting one of the one of the memory blocks and the other of the memory blocks. A memory with an arithmetic function as described. 4. A switch for disconnecting one of the plurality of word portions from one of the plurality of word blocks, and connecting the one of the plurality of word portions to another of the plurality of word blocks. The memory with an arithmetic function according to any one of claims 1 to 3, further comprising a common read / write line. 5. The operation unit executes the operation on the data of the word block one bit at a time in order. If the specific operation result is obtained during the execution of the operation,
5. The apparatus according to claim 1, further comprising an operation result storage unit for holding the operation result until the operation is completed.
A memory with an arithmetic function described in (1). 6. The operation unit executes the operation on the data of the word block one bit at a time in order. If the specific operation result is obtained during the execution of the operation,
A first flip-flop for holding the operation result until the operation is completed; a first flip-flop for obtaining the specific operation result during execution of the operation; The memory with an arithmetic function according to any one of claims 1 to 4, further comprising an arithmetic result storage unit including a second flip-flop for holding said data until said arithmetic operation is completed. 7. The memory with an arithmetic function according to claim 5, wherein said arithmetic result storage unit comprises an SRAM.