JP2000057711A - Error correction decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction decoding device capable of reducing an access number to a memory having a relatively large storage capacity and reducing power consumption. SOLUTION: An internal code correction circuit 41 of this error correction decoding device performs an error correction decoding operation by an internal code and writes the processed data onto an external memory 42. When reading data stored in the external memory 42, an external code correction circuit 43 copies in an internal memory 45, only the data to which a disappearance flag is simultaneously added. A syndrome is then generated by using the read data, and an error correction operation is performed, based on the generated syndrome, for the data stored in the internal memory 45. The data for which the error correction has been performed is written at an address of the corresponding data in the external memory 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an error correction decoding device for performing error correction decoding of digital data which has been error correction coded by a product code of an outer code and an inner code.

[0002]

2. Description of the Related Art Digital VTR (video tape recorder) for recording digital data error-corrected by a product code of an outer code and an inner code on a magnetic tape and reproducing the recorded data to perform error correction decoding. Are already on the market, and the DV standard (or DVC standard) is known as such a digital VTR standard (for example, HD-Digital VCR Conference: Speech).
cification of Digtal VCR for Consumer-use (Jul. 199
3)). The outline of the DV standard will be described below.

An image signal is composed of a luminance signal Y and a color difference signal Cr,
And 525 lines such as NTSC /
In the 60-field method, the number of effective pixels in the horizontal direction of the luminance signal Y is 720 pixels, the number of effective lines in the vertical direction is 480, and the color difference signals Cr and Cb are sampled at (4: 1: 1).
The number of effective pixels in the horizontal direction is 180 pixels, and the number of effective lines in the vertical direction is 480. Also P
In a so-called 625 line / 50 field system such as AL, the number of effective pixels in the horizontal direction of the luminance signal Y is 720, the number of effective lines in the vertical direction is 576, and the color difference signal is sampled at (4: 2: 0). For Cr and Cb, the number of effective pixels in the horizontal direction is 360 pixels, and the number of effective lines in the vertical direction is 288.

Image data is compressed by performing a DCT (Discrete Cosine Transform) operation by blocking these effective pixel data. A block for the DCT operation (hereinafter, referred to as a “DCT block”) is specifically configured such that each of the luminance signal Y and the color difference signals Cr and Cb is divided into eight horizontal pixels × eight vertical pixels for one frame pixel. Is done. Then, as shown in FIGS. 3A and 3B,
D of the luminance signal Y corresponding to the same area at the same position on the screen
A 6 DCT block including four CT blocks and one DCT block for each of the color difference signals Cb and Cr is called a “macro block”. Further, as shown in FIG. 4, a screen of one frame is divided into 27 macroblock units to form a super block. Then, one superblock is selected from each column in FIG. 4, one macroblock is extracted from each superblock, and one video segment is constituted by five macroblocks. At the time of image information compression processing, control is performed such that the data amount is within a predetermined amount in video segment units. Further, the video segment containing the data amount in this way is again divided into macroblock units and arranged back to the original screen position, and when recording on a magnetic tape, the screen of one frame is divided into ten bands, The one data is recorded on one track.

The DCT operation includes a mode in which 8 × 8 DCT is performed with 8 horizontal pixels × 8 vertical pixels in frame units (hereinafter referred to as “still mode”), and a horizontal 8 pixels in field units.
There is provided a mode (hereinafter referred to as “motion mode”) for performing 8 × 4 DCT by 4 pixels × vertical pixels and calculating the sum and difference of DCT coefficients of two fields, and is adaptively switched at the time of encoding. It is possible. That is, if the movement between two fields is small, the former is selected, and if the movement is large, the latter is selected. The DCT coefficient obtained by the DCT operation is selected by selecting a quantization table so that the data amount after the quantization and the variable length coding is equal to or less than a predetermined value and the value closest to the predetermined value. Be transformed into

[0006] The variable length coding is performed on the AC component of the DCT coefficient, and the AC component is sequentially read from the low frequency component.
Two-dimensional Huffman coding is performed based on two pieces of information including a continuous number of 0s and non-zero values appearing after 0s. The data after the variable length coding is formatted as shown in FIG. 5, and a sync block to which a sync word, an ID code and an inner parity (inner code) for error correction are added as shown in FIG. The data is recorded on a magnetic tape in sync block units.

In FIG. 5, in the data area of each sync block, data necessary for decoding together with data after variable length coding (Qn which is the number of the selected quantization table,
o, STA as error and concealment information, a class number taking a value according to the situation of the DCT block, and a DCT mode flag indicating which of the stationary mode and the motion mode is selected). . Here, concealing refers to replacing data using data of a previous frame or the like when an uncorrectable error occurs.

[0008] Information of one video segment is stored in five sync blocks. As described above, since one video segment is composed of five macroblocks, one sync block substantially corresponds to one macroblock. Since one macroblock is composed of four DCT blocks of the luminance signal Y and one DCT block of the color difference signals Cb and Cr, each DC component (DC) is stored in the DC area of FIG. AC) is, in principle, sequentially stored in an AC area corresponding to the same DCT block in the same sync block as the DC component.

[0009] The error correction coding is performed by using 1/1 of 270 video segments constituting one frame of video data.
0, ie, 138 sync blocks obtained by adding 3 sync blocks of video AUX (auxiliary information) to 135 sync blocks, and this is virtually 2
First, error correction coding such as Reed-Solomon coding (error correction coding using an outer code) is performed in the column direction, and 11 bytes of outer parity (outer code) are added. When all error correction coding in the column direction is completed,
Outer parity sync blocks are 11 sync blocks. Video segment and video AUX 1
Error correction coding (error correction coding by inner coding) is performed in the row direction of 149 sync blocks to which 38 sync blocks have been added, and 8 bytes of inner parity (inner code) are added. Thus, video data for one track is configured (see FIG. 7A).

Next, an error correction process during reproduction in a conventional VTR will be described with reference to FIG. A 149 sync block is extracted from one track of reproduced data, and error correction decoding is first performed using the 149 sync block as a unit using an inner code (inner parity) of each sync block. When the number of error symbols is determined to be within the correction capability of the inner code, correction is performed. When the number of error symbols exceeds the correction capability, an erasure flag indicating that fact is added to each sync block (see FIG. 7B). X ").

Next, error correction decoding using the outer code is performed using the outer code and the erasure flag. That is, first, error correction is attempted using only the outer code without referring to the erasure flag, and if the error cannot be corrected, error correction (erasure correction) is performed by regarding the position of the erasure flag as an error position. If the number of erasure flags is within the correctable range of the outer code but the error cannot be corrected by the outer code, it means that an erroneous correction has occurred in the inner code correction, and the error position cannot be specified. Is concealed and replaced with data of the same track in the previous frame. If the outer code cannot be corrected by error correction without referring to the erasure flag and the number of erasure flags is out of the correctable range of the outer code, the outer code cannot be corrected. An error is determined based on the lost flag. That is, the sync block to which the erasure flag is not added is made valid, and the sync block to which the erasure flag is added is concealed to be replaced with the sync block at the same position in the previous frame. For example, in FIG. 7B, the sync block to which the erasure flag is added is replaced with the corresponding sync block of the previous frame, and the sync block to which the erasure flag is not added is made valid. As described above, error correction and concealment using the inner code and the outer code are performed.

[0012]

In the case where error correction decoding is performed using a product code of an inner code and an outer code, the amount of error required when performing correction using an outer code is an error amount. It is necessary to read the symbols. Therefore, if only a relatively large-capacity memory that stores all data (units of 149 sync blocks in the above-described conventional example) serving as a unit to be corrected when performing correction using an outer code is used, access to the memory becomes difficult. There is a problem that the number of times increases and power consumption increases.

The present invention has been made in view of this point, and an object of the present invention is to provide an error correction decoding device capable of reducing the number of accesses to a memory having a relatively large storage capacity and reducing power consumption. Aim.

[0014]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an error correction decoding apparatus for decoding digital data error-corrected by a product code of an outer code and an inner code. An inner code correcting means for performing a correction decoding process, a first storage means for storing data output from the inner code correcting means, and a second storing means for storing only data which cannot be corrected by the inner code correcting means. Calculating a syndrome from the storage means and the data stored in the first storage means, and executing a correction process based on the syndrome on the data stored in the second storage means; Outer code correcting means for storing the data at the storage location of the corresponding data stored in the first storage means, and data stored in the first storage means When the correction processing with is finished, characterized in that it comprises an output control means for outputting the data stored in the first storage means.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of a digital image signal recording / reproducing apparatus including an error correction decoding apparatus according to an embodiment of the present invention. This apparatus is a VTR conforming to the DV standard described above. is there.

In FIG. 1, the recording system includes a blocking / shuffling unit 11, a compression processing unit 12, an error correction encoding unit 13, a sync block synthesis recording modulation unit 14, a recording amplifier 15, a recording head 16 Are the main components, and perform the recording signal processing conforming to the DV standard. The blocking / shuffling unit 11 receives input raster scan image data (a luminance signal Y and two color difference signals Cb and Cb).
r), a block of 8 pixels vertically × 8 pixels horizontally (hereinafter referred to as “DCT block”) is composed of macro blocks (4 blocks of Y signal, 1 block of Cb signal, 1 block of Cr signal). ) Output in units. The compression processing unit 12 performs DCT (Discrete Cosine Transform) operation, quantization and variable length coding on the input data, and the error correction coding unit 13 performs error correction coding and performs outer parity (outer code) and Add inner parity (inner code). The sync block synthesizing recording and modulating unit 14 synthesizes sync blocks constituting a small unit to be recorded on the magnetic tape, and performs modulation for recording on the magnetic tape.
The output data of No. 4 is amplified by the recording amplifier 15 and recorded on the magnetic tape 30 as a recording medium by the magnetic head 16.

The reproduction system includes a reproduction head 21, a reproduction amplifier 22, a SYNC detection reproduction demodulation unit 23, an error correction decoding unit 24, a decompression processing unit 25, and a pixel rearrangement unit 2.
6 and are the main constituent elements. The reproducing head 21
May be the same as the recording head 16. Data reproduced from the magnetic tape 30 by the reproduction head 21 is amplified by the reproduction amplifier 22 and input to the SYNC detection / reproduction demodulation block 23. The SYNC detection / reproduction / demodulation block 23 detects a SYNC word from the reproduction data and performs demodulation corresponding to the modulation at the time of recording. The error correction decoding unit 24 performs an error detection / correction process using the inner code and the outer code, and the decompression processing unit 25 performs processing reverse to that at the time of recording, that is, variable length decoding, inverse quantization, and inverse DCT operation. Are sequentially performed. The pixel rearranging unit 26 performs processing reverse to shuffling at the time of recording to restore the pixel arrangement to the original, and outputs image data (the luminance signal Y and the color difference signals Cb and Cr).

As shown in FIG. 2, an error correction decoding unit 24 corresponding to the error correction decoding apparatus of the present invention includes an inner code correction circuit 41 for performing error correction decoding using an inner code and an inner code correction circuit 41. An external memory 42 as first storage means for storing output data, an outer code correction circuit 43 for performing error correction decoding using an outer code in units of 149 sync block data stored in the external memory 42,
Writing data to the external memory 42 and the external memory 4
An address generation circuit 44 for generating an address for reading data from the memory 2 and an internal memory 45 as second storage means for storing only data that cannot be corrected by the inner code correction circuit 41. . In this embodiment, the internal memory 45 has a data capacity of 11 sync blocks because the range that can be corrected by the outer code is 11 symbols at maximum. That is, the internal memory 45
May be set so that data corresponding to the maximum number of symbols that can be corrected by the outer code can be stored.

The inner code correction circuit 41 takes out 149 sync blocks, and performs error correction decoding using the inner code of each sync block in units of this. That is, when the number of error symbols is determined to be within the correction capability of the inner code, correction is performed, and when the number exceeds the correction capability, an erasure flag indicating that fact is added to each sync block (FIG. 7).
(B)). The data after the correction decoding process is stored in the external memory 42 using the address of the address generation circuit 44.
Write to.

The outer code correction circuit 43 1) reads the data at the address generated by the address generation circuit 44 and copies only the data of the sync block to which the erasure flag is added to the internal memory 45, and 2) 4
2) a syndrome is generated from the data stored in 2); 3) when the erasure correction due to the generated syndrome occurs, a correction process is performed by rewriting the data in the internal memory 45; Only the written data is written back to the corresponding address in the external memory 42. If the number of the erasure flags exceeds the correction capability of the outer code and all the data to which the erasure flags are added cannot be copied to the internal memory 45, the correction processing for the data that cannot be copied to the internal memory 45 is performed. Is performed by accessing an address of the external memory 42 generated by the address generation circuit 44.

Here, the “syndrome” includes an outer code (outer parity) generated by the same arithmetic processing as that at the time of recording (at the time of error correction encoding) using the data to be corrected, and the reproduced outer code. This is information indicating the result of comparison with a code (external code stored in the external memory 42) (indicating whether the code matches or differs in bit units).

In this embodiment, the outer code correction circuit 43 also has a function as an output control means. When the correction processing for one correction unit (149 sync blocks) is completed, the data in the external memory 42 is deleted. The processing for supplying the data to the decompression processing unit 25 is performed.

As described above, in the present embodiment, the internal memory 45 having a capacity (for 11 sync blocks) corresponding to the correction capability of the outer code is provided, and the error correction processing is performed on the data stored in the internal memory 45. Therefore, the number of accesses to the large-capacity external memory 42 can be reduced, and power consumption can be reduced.

The present invention is not limited to the embodiment described above, and various modifications are possible. For example, an output control circuit having a function as output control means is provided separately from the outer code correction circuit 43, and the output control circuit
A process may be performed in which the data is read from the second device 2 and the read data is supplied to the decompression processing unit 25.

[0025]

As described in detail above, an inner code correction means for performing error correction decoding processing using an inner code, a first storage means for storing data output from the inner code correction means,
A second storage unit that stores only data that cannot be corrected by the inner code correction unit, a syndrome is obtained from data stored in the first storage unit,
A correction process based on the syndrome is performed on data stored in the second storage unit, and the data after the correction process is stored in a storage location of corresponding data stored in the first storage unit. And an output control means for outputting the data stored in the first storage means when the correction processing on the data stored in the first storage means is completed. Therefore, when performing correction by an outer code, a large-capacity first
The number of accesses to the storage means can be reduced, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital image signal recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an error correction decoding unit in FIG. 1;

FIG. 3 is a diagram for explaining a macroblock.

FIG. 4 is a diagram for explaining a relationship among a macro block, a super block, and a video segment.

FIG. 5 is a diagram showing a format when recording encoded data.

FIG. 6 is a diagram illustrating a configuration of a sync block.

FIG. 7 is a diagram for explaining an error correction decoding process.

[Explanation of symbols]

24 error correction decoder (error correction decoder) 41 inner code correction circuit (inner code correction means) 42 external memory (first storage means) 43 outer code correction circuit (outer code correction means, output control means) 44 address Generation circuit 45 Internal memory (second storage means)

Claims (1)

[Claims] 1. An error correction decoding device for decoding digital data error-corrected by a product code of an outer code and an inner code, wherein the inner code correcting means performs an error correction decoding process using the inner code. A first memory for storing data output from the inner code correcting means;
A second storage unit that stores only data that cannot be corrected by the inner code correction unit; a syndrome based on the data stored in the first storage unit; and a correction based on the syndrome. Outer code correcting means for executing processing on data stored in the second storage means and storing the corrected data in a storage location of corresponding data stored in the first storage means And an output control means for outputting the data stored in the first storage means when the correction processing for the data stored in the first storage means is completed. Correction decoding device.