JP2000049666A - Equalizer and equalizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To follow up variation of a line by maintaining a converging speed by increasing the precision of the tap coefficient of the equalizer and suppressing an increase in the operation quantity of tap coefficient update. SOLUTION: A decision unit 116 decides the large/small relation between an error signal and a threshold t1. An AND unit 117 controls a connection switch 114 and a changeover switch 118 and inputs the error signal and a tap coefficient stored in a memory 120 to a coefficient update unit 119 only when the error signal is larger than the threshold t1 in a message period to perform operation for tap coefficient update by the coefficient updating unit 119.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an equalizer and an equalization method used in a digital mobile communication system.

[0002]

2. Description of the Related Art In a radio communication system, a signal transmitted from a transmitter is received by a receiver as a composite wave of waves repeatedly reflected and scattered. Since the arrival time of each wave differs depending on the length of the propagation path, the signals interfere with each other in the wireless transmission path.

In digital mobile communication that performs high-speed digital transmission, if signals interfere with each other, it becomes difficult to determine a signal in a decoding process on the receiving side, and the data error rate increases significantly. For this reason, on the receiving side, the waveform of the received signal is shaped by the equalizer to reduce the influence of inter-signal interference.

[0004] The configuration and operation of a conventional equalizer will be described below by taking a decision feedback equalizer as an example. FIG. 11 is a block diagram showing a configuration of a conventional equalizer.

[0005] The input signal of the equalizer shown in FIG. 11 is delayed by one sampling period by passing through the delay unit 1, the delay unit 2, and the delay unit 3, respectively.

[0006] The input signal is multiplied by a tap coefficient signal k 1 in a digital multiplier 4. Similarly, the input signal delayed by one sampling period is input to the digital multiplier 5
, The input signal delayed by two sampling periods is multiplied by the tap coefficient signal k3 in the digital multiplier 6, and the input signal delayed by three sampling periods is converted by the digital multiplier 7. , And the tap coefficient signal k4.

Each signal multiplied by the tap coefficient signal is added by a digital adder 8, and the added signal (hereinafter referred to as “addition signal”) is output to a decision unit 9 and a digital subtractor 13. . Then, the signal transmitted from the transmitter is estimated by the determiner 9 based on the power value of the added signal. Estimated signal (hereinafter referred to as "estimated signal")
Is output to another device, passed through the delay unit 10 and delayed by one sampling period, and then multiplied by the tap coefficient signal k5 in the digital multiplier 11,
It is input to the digital adder 8.

Here, in general, a transmitter for mobile communication comprises:
A known training signal sequence is inserted before the message of the transmission signal. On the other hand, the equalizer in the receiver stores the same training reference signal sequence as the training signal sequence in order to adapt to the transmission path characteristics, and uses the training reference signal sequence while receiving the training signal sequence. Performs equalization processing. Hereinafter, a period during which a training signal sequence is received is referred to as a training period, and a period during which a message is received is referred to as a message period.

By controlling the changeover switch 12 with the control signal c1, the reference signal for training is input to the digital subtractor 13 during the training period, and the estimated signal is input to the digital subtractor 13 during the message period. Is done.

The digital subtracter 13 subtracts the training reference signal or the estimated signal from the added signal to indicate a decision error (hereinafter referred to as an "error signal").
Is calculated and output to the coefficient updating unit 14.

[0011] Then, the coefficient updating section 14 executes RLS (Re
Using a predetermined algorithm such as a cursive Least Square algorithm, a tap coefficient signal is calculated for each symbol from the input signal, the error signal, and the tap coefficient one symbol period earlier stored in the memory 15, and the updated tap coefficient is calculated. The signals k1 to k5 are output to each multiplier and the memory 15.

As described above, the conventional equalizer performs the equalization process by following the fluctuation of the line by adaptively updating the tap coefficient for each symbol during the training period and the message period.

[0013]

However, since the conventional equalizer updates the tap coefficients for each symbol, if the accuracy of the tap coefficients is increased, the amount of calculation for updating the tap coefficients increases, so that the convergence speed is increased. Becomes slow and cannot follow the fluctuation of the line.

In particular, in the RLS algorithm having excellent tap coefficient accuracy and convergence speed, about 3/4 of the total operation amount is a tap coefficient update operation, and the convergence speed sharply increases as the operation amount of the tap coefficient update increases. Become slow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to improve the accuracy of tap coefficients, suppress an increase in the amount of operation for updating tap coefficients, maintain a convergence speed, and follow line fluctuations. An object of the present invention is to provide an equalizer and an equalization method that can be used.

[0016]

Means for Solving the Problems In order to solve the above problems, the present invention has taken the following means. According to the invention relating to the equalizer according to claim 1, coefficient updating means for performing an operation by a predetermined algorithm to update tap coefficients, determining means for determining whether or not tap coefficients need to be updated, A period in which the determination result of the means is referred to is set, and a calculation execution control means for causing the coefficient updating means to perform a calculation only when the tap coefficient needs to be updated during this period is adopted.

According to a second aspect of the present invention, in the equalizer according to the first aspect, the arithmetic execution control means causes the coefficient updating means to perform an arithmetic operation for each symbol during a period in which the determination result of the determining means is not referred to. Take.

According to a third aspect of the present invention, in the equalizer according to the first or second aspect, the determining means determines that the tap coefficient needs to be updated when the error signal exceeds the first threshold value. It adopts the configuration to do.

[0019] In the invention relating to the equalization method according to claim 16, it is determined whether or not the tap coefficient needs to be updated,
A method of setting a period for referring to this determination result and updating the tap coefficient by performing a calculation by a predetermined algorithm only when the tap coefficient needs to be updated during this period is adopted.

According to a seventeenth aspect of the present invention, in the equalization method according to the sixteenth aspect, a method of updating a tap coefficient for each symbol during a period in which a determination result is not referred to is adopted.

The invention according to claim 18 employs a method according to claim 16 or claim 17, wherein it is determined that the tap coefficient needs to be updated when the error signal exceeds the first threshold value. .

With these configurations, the interval at which the tap coefficient update operation is performed during the message period can be controlled, and the operation can be performed only when the tap coefficient needs to be updated. The convergence speed can be maintained by suppressing an increase in the amount.

According to a fourth aspect of the present invention, in the equalizer according to the first or second aspect, the equalizer includes a first counter for adding the number of times the error signal has exceeded the second threshold value, and the determination means includes:
A configuration is adopted in which it is determined that the tap coefficient needs to be updated when the number of times the first counter has added is greater than the first threshold.

According to a nineteenth aspect of the present invention, in the equalization method according to the sixteenth or seventeenth aspect, the number of times the error signal exceeds the second threshold is added, and the number of additions is larger than the first threshold. To determine that the tap coefficient needs to be updated.

With these configurations, it is possible to determine whether or not it is necessary to update the tap coefficient based on the number of times the error signal has exceeded the threshold value. Therefore, the accuracy of the tap coefficient is increased, and the increase in the amount of calculation is suppressed. Thus, the convergence speed can be maintained.

According to a fifth aspect of the present invention, in the equalizer according to the first or second aspect, there is provided a first integrating means for integrating the error signal, and the determining means determines that the integrated value of the error signal is the first value.
A configuration is adopted in which it is determined that the tap coefficient needs to be updated when the threshold value is exceeded.

According to a twentieth aspect of the present invention, in the equalization method of the sixteenth or seventeenth aspect, the error signal is integrated, and the tap coefficient is updated when the integrated value of the error signal exceeds the first threshold value. Use a method to determine that it is necessary.

With these configurations, it is possible to determine whether or not it is necessary to update the tap coefficient based on the integrated value of the error signal. Therefore, the accuracy of the tap coefficient can be increased, and the convergence speed can be reduced while suppressing an increase in the amount of calculation. Can be kept.

According to a sixth aspect of the present invention, in the equalizer according to any one of the first to fifth aspects, the determining means comprises:
A configuration is adopted in which the previous error signal is used as the first threshold.

According to a seventh aspect of the present invention, in the equalizer according to any one of the first to fifth aspects, a second integrating means for integrating the error signal is provided, and the determining means includes a second integrating means for integrating the error signal. A configuration is adopted in which the first threshold is selected from a plurality of thresholds depending on whether the value exceeds the third threshold.

According to an eighth aspect of the present invention, in the equalizer according to any one of the first to fifth aspects, the determining means comprises:
A configuration is adopted in which a different first threshold is selected from a plurality of thresholds during the training period and the message period.

According to a twenty-first aspect of the present invention, in the equalization method according to any one of the sixteenth to twentieth aspects, a method is employed in which a previous error signal is used as a first threshold value.

According to a twenty-second aspect of the present invention, in the equalization method according to any one of the sixteenth to twentieth aspects, the error signal is integrated, and whether the integrated value of the error signal exceeds a third threshold value is determined. A method of selecting a first threshold from a plurality of thresholds is adopted.

According to a twenty-third aspect of the present invention, in the equalization method according to any one of the sixteenth to twentieth aspects, there is provided a method for selecting a different first threshold from a plurality of thresholds in a training period and a message period. take.

With these configurations, it is possible to finely switch the threshold value as a criterion for determining whether or not the tap coefficient needs to be updated.
Moreover, the convergence speed can be maintained while suppressing an increase in the amount of calculation.

According to a ninth aspect of the present invention, in the equalizer according to any one of the first to eighth aspects, the arithmetic execution control means uses a period for referring to the determination result of the determination means as a message period. Take.

According to a twenty-fourth aspect of the present invention, in the equalization method according to any one of the sixteenth to twenty-third aspects, a method is adopted in which a period for referring to the determination result is a message period.

With these configurations, the switching between the training period and the message period and the switching between the period in which the determination result is referred to and the period in which the determination result is not referred can be controlled by one control signal, so that the apparatus can be simplified. Can be planned.

According to a tenth aspect of the present invention, there is provided the equalizer according to any one of the first to eighth aspects, further comprising a second counter for adding the number of times the error signal exceeds a fourth threshold value, and The execution control means employs a configuration in which a period in which the determination result of the determination unit is referred to is a period in which the number of times that the second counter has added exceeds the fifth threshold value.

According to an eleventh aspect of the present invention, in the equalizer according to any one of the first to eighth aspects, a third integrator for integrating the error signal is provided, and the arithmetic execution control means includes a determination means. Is set as a period in which the integrated value of the error signal exceeds the fifth threshold value.

According to a twenty-fifth aspect of the present invention, in the equalization method according to any one of the sixteenth to twenty-third aspects, the number of times that the error signal exceeds the fourth threshold value is added, and a period for referring to the determination result is set. A method is adopted in which the number of times of the addition exceeds the fifth threshold value.

According to a twenty-sixth aspect of the present invention, in the equalization method according to any one of the sixteenth to twenty-third aspects, the error signal is integrated, and a period in which the determination result is referred to is a fifth value. A method is adopted in which the period exceeds the threshold.

With these configurations, the period for referencing the determination result can be adaptively changed according to the line condition, so that the accuracy of the tap coefficient is further increased, and the convergence speed is maintained while suppressing the increase in the amount of calculation. Can be.

According to a twelfth aspect of the present invention, in the equalizer according to any one of the first to eighth aspects, the arithmetic execution control means employs a configuration in which the operation execution control means refers to the determination result of the determination means in all periods. .

According to a twenty-seventh aspect of the present invention, in the equalization method according to any one of the sixteenth to twenty-third aspects, a method is employed in which a determination result is referred to in all periods.

With these configurations, it is possible to simplify the configuration of the apparatus, and it is possible to control the interval of the operation for updating the tap coefficients effectively even when the training signal period cannot be sufficiently secured.

According to a thirteenth aspect of the present invention, there is provided a communication terminal apparatus comprising the equalizer according to any one of the first to twelfth aspects, wherein the equalizer is used to shape a waveform of a received signal. Take.

According to a fourteenth aspect of the present invention, there is provided a base station apparatus comprising the equalizer according to any one of the first to twelfth aspects, and shaping a waveform of a received signal using the equalizer. Take.

According to a fifteenth aspect of the invention relating to a wireless communication system, the equalizer according to any one of the first to twelfth aspects is mounted on at least one of a mobile station apparatus and a base station apparatus to perform wireless communication. Take the configuration.

[0050]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the following description, a decision feedback equalizer is used as an equalizer.

In the following description, an RLS algorithm is used as a coefficient updating algorithm. The update tap coefficient W (n) in the RLS algorithm is calculated based on the input signal X
(n), the error signal e (n), the forgetting coefficient λ, and the natural number n are obtained by the following equation (1).

W (n) = W (n−1) + K (n) e (n) K (n) = T (n) / {1 + X (n) T (n)} T (n) = P (n -1) X (n) / [lambda] P (n) = P (n-1) / [lambda] -K (n) T (n) (1) In addition, each control signal and each threshold in the following description may be a user or the like. Is set in advance, and is output to the equalizer from a control unit not shown in each figure.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of an equalizer according to Embodiment 1 of the present invention.

In the equalizer shown in FIG.
1. The delay unit 102 and the delay unit 103 delay the input signal by one sample period. The digital multiplier 104 multiplies the input signal by the tap coefficient signal k1. The digital multiplier 105 multiplies the input signal delayed by one sample period by the tap coefficient signal k2. The digital multiplier 106
The input signal delayed by two sample periods is multiplied by the tap coefficient signal k3. The digital multiplier 107 multiplies the input signal delayed by three sample periods by the tap coefficient signal k4.

The digital adder 108 adds a plurality of signals multiplied by each tap coefficient signal (hereinafter referred to as a signal).
"Addition signal").

The decision unit 109 estimates the signal transmitted from the transmitter based on the power value of the added signal and the like, and outputs the estimated signal (hereinafter, referred to as “estimated signal”).

The delay unit 110 delays the estimated signal by one sample period, and the digital multiplier 111 multiplies the estimated signal delayed by one sample period by the tap coefficient signal k5 and outputs the result to the adder.

The change-over switch 112 selects a training reference signal during a training period and an estimated signal during a message period according to the control signal c1,
The selected signal is output to the digital subtractor 113.

The digital subtractor 113 subtracts the training reference signal or the estimated signal from the added signal, calculates a signal representing a determination error (hereinafter, referred to as an “error signal”), and supplies the signal to the connection switch 114 and the digital subtractor 115. Output.

Digital subtracter 115 outputs a signal obtained by subtracting threshold value t1 from the error signal to determiner 116. The determiner 116 determines that the update of the tap coefficient is necessary when the error signal is higher than the threshold value t1, and otherwise determines that the update of the tap coefficient is not necessary. Then, the determiner 116 outputs a control signal based on the determination result (hereinafter, referred to as a “determination control signal”) to the ANDer 117. Note that the error signal and the threshold value t1 may be input to the determiner 116 without using the digital subtractor 115, and the determiner 116 may determine the magnitude of the error signal and the threshold value t1.

When the tap coefficient needs to be updated during the training period or the message period by the control signal c1 and the judgment control signal,
The connection switch 114 is connected, and the changeover switch 118 is controlled to connect the coefficient updater 119 and the memory 120.
If it is not necessary to update the tap coefficients during the message period, the connection switch 114 is disconnected, and the changeover switch 118 is controlled to output the tap coefficient signals k1 to k5 stored in the memory 120 to the respective multipliers.

The coefficient updating section 119 receives the input signal, the error signal, and the tap coefficient of one symbol period before, calculates the tap coefficient by the RLS algorithm, and generates the tap coefficient signal k.
1 to k5 are output to each multiplier and the memory 120.

The memory 120 stores the input tap coefficient signals k1 to k5, and outputs the stored tap coefficient signals to the switch 118 after one symbol period has elapsed.

Next, the equalization processing of the equalizer in the first embodiment will be described. The input signal input to the equalizer is delayed by one sampling period by passing through each of the delay unit 101, the delay unit 102, and the delay unit 103.

The input signal is supplied to the digital multiplier 10
At 4, the tap coefficient signal k1 is multiplied. Similarly, 1
The input signal delayed by the sampling period is multiplied by the tap coefficient signal k2 in the digital multiplier 105, and the input signal delayed by two sampling periods is converted by the digital multiplier 1
At 06, the input signal multiplied by the tap coefficient signal k3 and delayed by three sampling cycles is applied to the digital multiplier 107.
Is multiplied by the tap coefficient signal k4.

Each signal multiplied by the tap coefficient signal is added by a digital adder 108, and the added signal is output to a decision unit 109 and a digital subtractor 113.

Then, the decision unit 109 estimates the signal transmitted from the transmitter based on the power value of the added signal, outputs the estimated signal to another device, and sets the delay unit 110
, And is delayed by one sampling period, multiplied by the tap coefficient signal k5 in the digital multiplier 111, and output to the digital adder.

The changeover switch 11 is controlled by the control signal c1.
2 so that the training reference signal is supplied to the digital subtractor 113 during the training period.
, And the estimation signal is output to the digital subtractor 113 during the message period. Then, the digital subtractor 113 subtracts the training reference signal or the estimated signal from the added signal to calculate an error signal, and outputs the error signal to the connection switch 114 and the digital subtractor 115.

The error signal input to the digital subtractor 115 is subtracted from the threshold value t1 and output to the decision unit 116. Then, the determiner 116 determines whether or not the error signal is higher than the threshold value t1, that is, whether or not the tap coefficient needs to be updated, and outputs a determination control signal based on the determination result to the ANDer 117. .

When the connection switch 114 and the changeover switch 118 are controlled by the logical product 117 by the control signal c1 and the judgment control signal, the tap coefficient is updated during the training period or the message period. Only the error signal and the tap coefficient one symbol period earlier are input to the coefficient updater 119. Then, in the coefficient update unit 119, the tap coefficient is calculated by the RLS algorithm using the input signal, the error signal, and the correction coefficient, and the updated tap coefficient signals k1 to k5 are output to the multipliers and the memory 120. .

When it is not necessary to update the tap coefficients during the message period, tap coefficient signals k1 to k5 stored in memory 120 are output to the respective multipliers.

As described above, the interval at which the tap coefficient update calculation is performed in the message period is controlled, and the calculation is performed only when the tap coefficient needs to be updated, thereby improving the accuracy of the tap coefficient and increasing the amount of calculation. The convergence speed can be maintained by suppressing the increase.

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of an equalizer according to Embodiment 2. In the equalizer shown in FIG. 2, portions common to those in the equalizer shown in FIG.

The equalizer shown in FIG. 2 is the same as the equalizer shown in FIG.
3 is added.

The digital subtractor 113 outputs an error signal to the connection switch 114 and the digital subtracter 121. The digital subtractor 121 calculates a threshold value t2 from the error signal.
Is output to the decision unit 122. Judge 12
2 determines whether the error signal is smaller than a threshold value t2,
The counter 123 counts the number of times that the error signal is smaller than the threshold value t2.

The digital subtractor 115 has a counter 12
The signal obtained by subtracting the threshold value t1 from the count number 3
16 is output. When the count number of the counter 123 exceeds the threshold value t1, the determiner 116 determines that the tap coefficient needs to be updated, and outputs a determination control signal to the ANDer 117.

As described above, whether or not the tap coefficients need to be updated is determined based on the number of times that the error signal is determined to be larger than the threshold value, so that the equalizer shown in FIG. And the convergence speed can be increased, and the error rate characteristics can be improved.

(Embodiment 3) FIG.3 is a block diagram showing a configuration of an equalizer according to Embodiment 3. Note that, in the equalizer shown in FIG. 3, portions common to those in the equalizer shown in FIG.

The equalizer shown in FIG. 3 employs a configuration in which an integrator 131 is added to the equalizer shown in FIG. Digital subtractor 11
Reference numeral 3 denotes a connection switch 114 and an integrator 131
Output to The integrator 131 integrates the error signal and outputs the integrated value to the digital subtractor 115. The digital subtractor 115 outputs a signal obtained by subtracting the threshold value t1 from the integrated value of the error signal to the determiner 116. Judge 116
Determines that the tap coefficient needs to be updated when the integrated value of the error signal exceeds the threshold value t1, and outputs a determination control signal to the logical AND unit 117.

As described above, by determining whether or not the tap coefficients need to be updated based on the integrated value of the error signal, the tap coefficient accuracy can be improved and the convergence speed can be improved compared to the equalizer shown in FIG. Higher speed can be achieved, and error rate characteristics can be improved.

Embodiment 4 FIG. 4 is a block diagram showing a configuration of an equalizer according to Embodiment 4. Note that, in the equalizer shown in FIG. 4, portions common to those in the equalizer shown in FIG.

The equalizer shown in FIG. 4 employs a configuration in which a connection switch 141 and a memory 142 are added to the equalizer shown in FIG. The digital subtractor 113 outputs the error signal to the connection switch 114, the digital subtractor 115, and the connection switch 1.
41. The connection switch 141 is connected to the determiner 116
The error signal is output to the memory 142 by the determination control signal output from the memory device 142, and is disconnected when one burst period elapses after the connection. The memory 142 temporarily stores the input error signal, and outputs a stored previous error signal to the digital subtractor 115 when a new error signal is input. The digital subtractor 115 outputs a signal obtained by subtracting the previous error signal from the error signal to the determiner 116. The determiner 116 determines whether or not the tap coefficient needs to be updated using the previous error signal as a threshold, and outputs a determination control signal to the logical AND unit 117 and the connection switch 141.

As described above, by determining whether or not the tap coefficients need to be updated using the previous error signal as a threshold value, the tap coefficient accuracy can be improved and the convergence speed can be improved as compared with the equalizer shown in FIG. And the error rate characteristics can be improved.

(Embodiment 5) FIG.5 is a block diagram showing a configuration of an equalizer according to Embodiment 5. In the equalizer shown in FIG. 5, the same reference numerals as those in FIG. 1 denote the same parts as those in FIG. 1, and a description thereof will be omitted.

The equalizer shown in FIG. 5 differs from the equalizer shown in FIG. 1 in that an integrator 151, a digital subtractor 152, and a decision unit 153.
And a changeover switch 154 is added. The digital subtractor 113 outputs the error signal to the connection switch 114,
Output to the digital subtractor 115 and the integrator 151.
Integrator 151 integrates the error signal, and outputs the integrated value to digital subtractor 152. Digital subtractor 15
2 outputs a signal obtained by subtracting the threshold value t3 from the integrated value of the error signal to the determiner 153. The decision unit 153 determines whether or not the integrated value of the error signal exceeds the threshold value t3.
4 is selected, and either the threshold value t1-1 or the threshold value t1-2 is selected and input to the digital subtractor 115.

The digital subtracter 115 outputs a signal obtained by subtracting the selected threshold value from the error signal to the decision unit 116. The determiner 116 determines whether or not the tap coefficient needs to be updated using the selected threshold, and outputs a determination control signal to the logical product 117.

As described above, by selecting the threshold value as a criterion for determining whether or not the tap coefficient needs to be updated based on the integrated value of the error signal, the tap coefficient can be determined by the equalizer shown in FIG. The accuracy and the convergence speed can be improved, and the error rate characteristics can be improved.

(Embodiment 6) FIG.6 is a block diagram showing a configuration of an equalizer according to Embodiment 6. In the equalizer shown in FIG. 6, the same reference numerals as those in FIG. 1 denote the same parts as those in FIG. 1, and a description thereof will be omitted.

The equalizer shown in FIG. 6 includes a digital subtractor 161, a decision unit 162, and a counter 16
3, a digital subtractor 164, and a decision unit 165 are added.

The digital subtractor 113 outputs an error signal to the connection switch 114, the digital subtractor 115, and the digital subtracter 161. Digital subtractor 161
Is a signal obtained by subtracting the threshold value t4 from the error signal.
Output to 2. The determiner 162 determines whether the error signal is smaller than the threshold value t4, and the counter 163 counts the number of times the error signal is smaller than the threshold value t4.

The digital subtractor 164 includes a counter 16
The signal obtained by subtracting the threshold value t5 from the count number 3
65. When the count number of the counter 123 exceeds the threshold value t5, the determiner 165 determines that it is necessary to control the interval of the tap coefficient update operation, and outputs a determination control signal to the logical ANDer 117.

As described above, by changing the period for controlling the interval of the tap coefficient update operation based on the number of times the error signal is determined to be larger than the threshold value t4, the equalizer shown in FIG. The accuracy and the convergence speed can be improved, and the error rate characteristics can be improved.

(Embodiment 7) FIG. 7 is a block diagram showing a configuration of an equalizer according to Embodiment 7. In the equalizer shown in FIG. 7, the same reference numerals as in FIG. 1 denote the same parts as in FIG. 1, and a description thereof will be omitted.

The equalizer shown in FIG. 7 is different from the equalizer shown in FIG. 1 in that an integrator 171, a digital subtractor 172, and a decision unit 173.
And a configuration in which is added. The digital subtractor 113
The error signal is connected to the connection switch 114, the digital subtractor 11
5 and to the integrator 171. Integrator 171 integrates the error signal and outputs the integrated value to digital subtractor 172. The digital subtractor 172 outputs a signal obtained by subtracting the threshold value t5 from the integrated value of the error signal to the determiner 173. When the integrated value of the error signal exceeds the threshold value t5, the determiner 173 determines that it is necessary to control the interval of the tap coefficient update calculation, and outputs a determination control signal to the logical product 117.

As described above, by changing the period for controlling the interval of the tap coefficient update operation based on the integrated value of the error signal, the tap coefficient accuracy can be improved and the convergence speed can be improved compared to the equalizer shown in FIG. Higher speed can be achieved, and error rate characteristics can be improved.

(Eighth Embodiment) FIG. 8 is a block diagram showing a configuration of an equalizer according to an eighth embodiment. The configuration of the equalizer shown in FIG. 8 is the same as that of the equalizer shown in FIG. 1, except that the control signal c1 and another control signal c2 are input to the logical product 117.

As described above, by separating the control signal for controlling the period for controlling the interval of the tap coefficient update operation from the control signal for controlling switching between the training period and the message period, the equalizer shown in FIG. In addition, it is possible to improve tap coefficient accuracy and increase the convergence speed, thereby improving the error rate characteristics.

(Embodiment 9) FIG.9 is a block diagram showing a configuration of an equalizer according to Embodiment 9 of the present invention. Note that the configuration of the equalizer shown in FIG. 9 employs a configuration in which the logical product 117 is removed from the equalizer shown in FIG.

As described above, the apparatus can be simplified by controlling the connection switch 114 and the changeover switch 120 using only the determination control signal. The equalizer according to the ninth embodiment is effective when a training signal period cannot be sufficiently secured.

(Embodiment 10) FIG.10 is a block diagram showing a configuration of an equalizer according to Embodiment 10. In the equalizer shown in FIG. 10, the same parts as those in the equalizer shown in FIG. 9 are denoted by the same reference numerals as those in FIG.

The equalizer shown in FIG. 10 employs a configuration in which a changeover switch 201 is added to the equalizer shown in FIG. Control signal c1
Controls the switch 201 to select the threshold t1-1 in the training period and the threshold t1-2 in the message period. Here, in the case of Embodiment 10,
In the first half of the training period when the tap coefficients are converging, the threshold value t1-1 needs to be set sufficiently small so as not to control the interval of the tap coefficient update calculation.

The digital subtractor 115 outputs a signal obtained by subtracting the selected threshold value from the error signal to the determiner 116. The determiner 116 determines whether the tap coefficient needs to be updated using the selected threshold value, and
14 and the changeover switch 120 are controlled.

As described above, the threshold value used as a criterion for determining whether or not the tap coefficients need to be updated is switched between the training period and the message period by the control signal, whereby the equalizer shown in FIG. In addition, it is possible to improve tap coefficient accuracy and increase the convergence speed, thereby improving the error rate characteristics.

Although the above embodiments have been described using a decision feedback equalizer as an equalizer, the present invention is not limited to this, and a maximum likelihood sequence estimation type equalizer is used. Can obtain the same effect.

In the present invention, an equalizer can be configured by appropriately combining the embodiments, and an equalizer can be configured by changing the number of delay units and multipliers. It is.

In each of the above embodiments,
Although the description has been made using the RLS algorithm as the coefficient updating algorithm, the present invention is not limited to this.
The same effect can be obtained by using another algorithm such as the S algorithm. Further, in multiplying the correction coefficient, a bit shift circuit can be used instead of the multiplier.

[0107]

As described above, according to the equalizer and the equalizing method of the present invention, the accuracy of the tap coefficient is improved, and the convergence speed is maintained by suppressing an increase in the amount of operation for updating the tap coefficient. And the error rate characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an equalizer according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an equalizer according to a second embodiment.

FIG. 3 is a block diagram illustrating a configuration of an equalizer according to a third embodiment.

FIG. 4 is a block diagram showing a configuration of an equalizer according to a fourth embodiment.

FIG. 5 is a block diagram showing a configuration of an equalizer according to a fifth embodiment.

FIG. 6 is a block diagram illustrating a configuration of an equalizer according to a sixth embodiment.

FIG. 7 is a block diagram showing a configuration of an equalizer according to a seventh embodiment.

FIG. 8 is a block diagram illustrating a configuration of an equalizer according to an eighth embodiment.

FIG. 9 is a block diagram showing a configuration of an equalizer according to a ninth embodiment.

FIG. 10 is a block diagram illustrating a configuration of an equalizer according to Embodiment 10.

FIG. 11 is a block diagram showing a configuration of a conventional equalizer.

[Explanation of symbols]

101, 102, 103, 110 Delay unit 104, 105, 106, 107, 111 Digital multiplier 108 Digital adder 109 Judgment unit 112 Changeover switch 113 Digital subtractor 114 Connection switch 115 Digital subtractor 116 Judgment unit 117 Logical product 118 Changeover switch 119 Coefficient updater 120 Memory 121 Digital subtractor 122 Judge 123 Counter 131 Integrator 141 Connection switch 142 Memory 151 Integrator 152 Digital subtracter 153 Judge 161 Digital subtracter 162 Judge 163 Counter 164 Digital subtracter 165 Judge 171 Integrator 172 Digital subtractor 173 Judgment device 201 Changeover switch

Claims (27)

[Claims] 1. A coefficient updating means for performing an operation according to a predetermined algorithm to update a tap coefficient, a judging means for judging whether or not the tap coefficient needs to be updated, and referring to a judgment result of the judging means. An equalizer comprising: a period setting unit; and a calculation execution control unit that causes the coefficient updating unit to perform a calculation only when a tap coefficient needs to be updated during this period. 2. The equalizer according to claim 1, wherein the calculation execution control means causes the coefficient updating means to perform the calculation for each symbol during a period in which the determination result of the determination means is not referred to. 3. The equalizer according to claim 1, wherein the judging means judges that the tap coefficient needs to be updated when the error signal exceeds the first threshold value. 4. A first counter for adding the number of times the error signal exceeds a second threshold value, wherein the determination means updates the tap coefficient when the number of times the first counter adds is larger than the first threshold value. 3. The equalizer according to claim 1, wherein it is determined that it is necessary. 5. A method according to claim 1, further comprising a first integrating means for integrating the error signal, wherein the determining means determines that the tap coefficient needs to be updated when the integrated value of the error signal exceeds a first threshold. The equalizer according to claim 1 or 2, wherein 6. The equalizer according to claim 1, wherein said determination means sets a previous error signal as a first threshold value. 7. A method according to claim 6, further comprising a second integrating means for integrating the error signal, wherein the determining means selects the first threshold from a plurality of thresholds depending on whether the integrated value of the error signal exceeds a third threshold. The equalizer according to any one of claims 1 to 5, wherein 8. The equalizer according to claim 1, wherein the determining means selects a first threshold different from a plurality of thresholds in the training period and the message period. 9. The equalizer according to claim 1, wherein the arithmetic execution control unit sets a period for referring to the determination result of the determination unit as a message period. 10. A second counter for adding the number of times the error signal has exceeded a fourth threshold value, wherein the arithmetic execution control means determines that the number of times the second counter has added a period for referring to the determination result of the determination means. 9. The equalizer according to claim 1, wherein the period is longer than a fifth threshold. 11. A third integrator for accumulating an error signal, wherein the arithmetic execution control means sets a period in which the judgment result of the judging means is referred to as a period in which the integrated value of the error signal exceeds a fifth threshold value. The equalizer according to any one of claims 1 to 8, wherein: 12. The equalizer according to claim 1, wherein the arithmetic execution control unit refers to a determination result of the determination unit in all periods. 13. A communication terminal device equipped with the equalizer according to claim 1 and shaping a waveform of a received signal using the equalizer. 14. A base station apparatus equipped with the equalizer according to claim 1 and shaping a waveform of a received signal using the equalizer. 15. A wireless communication system, comprising: the at least one of a mobile station apparatus and a base station apparatus, wherein the equalizer according to claim 1 is mounted to perform wireless communication. 16. It is determined whether or not a tap coefficient needs to be updated, a period for referring to the result of the determination is set, and in this period, only when the tap coefficient needs to be updated, a predetermined algorithm is used. An equalization method comprising performing an operation to update a tap coefficient. 17. In a period in which the judgment result is not referred to,
17. The equalization method according to claim 16, wherein an operation of updating a tap coefficient is performed for each symbol. 18. The equalization method according to claim 16, wherein it is determined that the tap coefficient needs to be updated when the error signal exceeds the first threshold value. 19. The method according to claim 16, further comprising: adding the number of times the error signal exceeds a second threshold, and determining that the tap coefficient needs to be updated when the number of additions is larger than the first threshold. Or the equalization method according to claim 17. 20. The method according to claim 16, wherein the error signal is integrated, and when the integrated value of the error signal exceeds the first threshold, it is determined that the tap coefficient needs to be updated. Equalization method. 21. The equalization method according to claim 16, wherein a previous error signal is used as a first threshold value. 22. The method according to claim 16, wherein the error signal is integrated, and a first threshold is selected from a plurality of thresholds depending on whether or not the integrated value of the error signal exceeds a third threshold.
0. The equalization method according to any one of 0. 23. The equalization method according to claim 16, wherein a different first threshold value is selected from a plurality of threshold values in the training period and the message period. 24. The message period according to claim 16, wherein a period for referring to the determination result is a message period.
The equalization method according to any one of the above. 25. The method according to claim 16, wherein the number of times the error signal exceeds a fourth threshold value is added, and a period for referring to the determination result is a period during which the added number exceeds the fifth threshold value. The equalization method according to claim 23. 26. The method according to claim 16, wherein the period in which the error signal is integrated and the determination result is referred to is a period in which the integrated value of the error signal exceeds the fifth threshold value. The described equalization method. 27. The equalization method according to claim 16, wherein the determination result is referred to in all periods.