JP2000044135A - Speed control device in elevator and recording medium for recording speed detection program of elevator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a highly precise speed detection even when a reverse rotation occurs in starting by performing a control for switching the set value of a motor rotating pulse counter from an integral multiple of 4 to an integral multiple of 1 when zero speed is detected, and switching the set value to the integral multiple of 4 at the 5th pulse. SOLUTION: When the detected speed by a speed detecting circuit is 0 (S101), detection 4F mode is set, and the set value of an angle measuring counter is switched from an integral multiple of 4 to an integral multiple of 1 to perform the speed detection (S102). In case of detected speed ≠ 0 whether the pulse is the 5th or following pulse is judged. In case of judgment of the 5th or following pulse, detection 1F mode is set, and the set value of the angle measuring counter is switched from an integral multiple of 1 to an integral multiple of 4 to perform the speed detection, whereby an elevator is controlled (S103). By changing the set value on the basis of the detection of zero speed and the judgment of the 5th and following pulse, the speed detection can be precisely performed even if the motor is reversely rotated in starting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed control device for an elevator and a recording medium storing an elevator speed detection program.

[0002]

2. Description of the Related Art A vector control device as shown in FIG. 3 is used for an elevator speed control device. In the figure, 1 is an elevator motor, 2 is the speed pulse detector attached to a portion that operates the car same speed of the shaft or the elevator motor 1, 3 speed detection circuit for detecting a motor speed omega _n from this rate pulse 4 is the speed command N and the speed detection value ω _n
Speed control amplifier that calculates the deviation from PI.

[0003] 5 is torque current command value I _t from the amplifier 4
Primary current arithmetic circuit by the excitation current setting value I ₀ obtains a primary current value I ₁ of the motor and, 6 phase calculating unit for obtaining the phase angle φ of I _t and I _0, 7 is I _t and I ₀ and the circuit 11 slip frequency calculation unit for obtaining the slip frequency omega _s of the secondary time constant determined in 13, an adder for outputting the angular frequency omega ₀ by adding omega _s and omega _n is 8.

[0004] 9 I _1, phi, primary current command value I _a from omega ₀ motor 1, I _b, the primary current calculation unit for obtaining the I _c, 10 is a primary current to the motor by receiving the primary current instruction value An inverter for outputting, 11 is a current detector, 12 is an A / D converter, and 13 is a secondary time constant calculation unit.

[0005] As shown in FIG. 4, the speed detection circuit 3 includes a motor rotation pulse counter 15 and a clock counter 16, a counter synchronization controller 17 for controlling synchronization of the motor rotation pulse counter 15, and the counter 15 or 16.
And a counter stop output unit 19 that receives a signal from the OR circuit 18 and outputs a counter stop signal to the counter synchronization control unit 17.

The motor rotation pulse counter 15 outputs a signal FP4 obtained by quadrupling the output frequency of the speed detector 2 (FIG. 3).
(FIG. 5), and the clock counter 16
High-speed clock signals such as clocks (several MHz to tens of MH
z) is counted.

In FIG. 4, an initial value can be written in the motor rotation pulse counter 15 and a counter reset signal can be input to the clock counter 16 so that the state of the counter can be returned to the initial value. I have to.

Therefore, the operation of the clock counter 16 is started by using the signal FP4 obtained by quadrupling the signal from the speed pulse detector 2 (FIG. 3) as a trigger, and when the motor rotation pulse counter 15 overflows, the counter of this counter is started. A CY (carry) signal is output, and a counter stop signal is output from the counter stop output unit 19 to the counter synchronization control unit 17 via the logical sum circuit 18 to output the clock counter 1
6 is stopped.

Thus, the time during which the set number of pulses of the signal FP4 obtained by quadrupling the signal from the speed pulse detector 2 is generated can be known from the value of the clock counter 16. By detecting and calculating this time, the speed of the elevator is detected.

The equation for calculating the motor rotation speed is shown by the following equation (1).

[0011]

(Equation 1)

The set value of the count value RNCT to be set in the motor rotation pulse counter 15 for the next detection is determined by calculation according to the following equation (2).

[0013]

(Equation 2)

According to Equation 2, when the clock counter 16 counts many times, the value RNCT set in the motor rotation pulse counter 15 for the next detection is set to a small value. Actually, the speed detection is performed by selecting the RNCT so that the time interval is shorter than the speed control cycle of the control device, that is, the value of the RMCT.

The value RNCT set in the motor rotation pulse counter 15 is usually set to a multiple of four.
That is, the minimum value is 4, and as the speed increases, 8, 12,
16 ... is performed.

At the start of the operation of the elevator, the control device cannot recognize that the elevator has operated unless four or more pulses from the speed pulse detector come, so that a time delay occurs in the speed detection at the start of operation. This causes a car vibration (start shock).

Therefore, when the current speed detection value (motor rotation speed) DSP is equal to or less than a predetermined value (for example, 2% or less) with respect to the rated speed, the value RNCT set in the motor rotation pulse counter 15 is changed. What is normally controlled as 4 is controlled as 1 (FIG. 7).

By changing the operation mode of the speed detection circuit, when the operation of the elevator is started, if the number of pulses from the speed pulse detector 2 does not reach four or more, it cannot be recognized that the elevator has started operation. Since it can be recognized by one, the fluctuation of the output of the speed control amplifier 4 (FIG. 3) can be suppressed at an early stage, and the start shock can be suppressed. (Japanese Patent Application No. 9-17274) In a speed detection device, there is a speed detection device that uses a latch that holds the occurrence time of each edge of a detection pulse of a speed pulse detector, and calculates a speed using the latch information. (JP-A-6-118090). This speed calculation circuit is shown in FIG.

In FIG. 8, reference numeral 21 denotes a latch signal generation unit to which two-phase signals (A phase and B phase) are supplied from an encoder (speed pulse detector). The latch signal generation unit 21 has a waveform shaping circuit. It has been incorporated. Latch signal generator 2
When a two-phase (A, B phase) signal (FIGS. 5 and 6) from the encoder is input to 1, a pulse edge is first detected from the signal, and a normal rotation edge / reverse rotation edge is detected based on the pulse change. , UP / DOWN signals. In addition, each edge change is determined by a phase angle of a physical rotating slit or the like.
Edge selection signals EDO to E as data latch enable signals to the corresponding data latch units described later.
D3 is output. Note that the edge selection signals ED0 to ED3
Operates only once per edge out of four.

9A and 9B show UP / DOW from the encoder.
6 is an operation timing chart for obtaining an N signal and an operation timing chart for obtaining edge selection signals ED0 to ED3.

Reference numeral 22 denotes an angle measurement counter (angle detection counter) to which the quadruple frequency signal 4F and the UP / DOWN signal of the output signal from the latch signal generator 21 are supplied. Both signals are obtained by the angle measurement counter 22 as shown in FIG.
Measurement is performed as shown in the timing chart shown in FIG. 0, and the rotation angle of the encoder is obtained as the output as the counter data.

Reference numeral 23 denotes a time measurement counter (time detection counter). The counter 23 measures the measurement reference clock CLK and the cycle set value, and obtains a calculation cycle count value and a timing output (cycle signal) SMPL as outputs. FIG. 11 shows the timing chart.

The counter 23 measures a reference time which is the time at which the 4F signal is generated, and the effective bit length of the counter need only be equal to or longer than the speed calculation period. Here, a case is shown in which the counter 23 is used as a speed calculation cycle generator, and the counter 23 is shown as an example of a DOWN counter.

.., 24-4 are first data latch units (angle data latches). The first data latch units 24-1, 24-2,. (Count output) is supplied.
The latch units 24-1 to 24-4 are supplied with edge selection signals ED0 to ED3 as enable signals. This latches the angle of each edge. The first data latch unit 24-1 is composed of D-type flip-flops, and these flip-flops
And the same number of bits. The first data latch units 24-2 to 24-4 have the same configuration.

25-4 are second data latch units. The configuration of these latch units 25-1 to 25-4 is the same as that of the first data latch units 24-1 to 24-4. . The second data latch units 25-1 to 25-4 are supplied with the count value output TCN of the time measurement counter 23.

Reference numeral 26 denotes an edge detection and holding unit to which the edge selection signals ED0 to ED3 sent from the latch signal generation unit 21 are supplied. The edge detection and holding unit 26 is formed of a JK flip-flop and operates during the speed detection period. ED0-E
The presence or absence of the change detection of each edge of D3 is detected and held. If there is a corresponding edge change even once, set “1”,
If no occurrence has occurred, “0” is held. This held data is reset to "0" every time data is transferred from the first data latch units 24-1 to 24-4 to the second data latch units 25-1 to 25-4.

Reference numeral 32 denotes a third data latch unit, which is composed of the following three circuits. First, 27-1... 27-4 are angle data latches. The latch outputs a speed calculation cycle signal SMPL for the latch data of the first data latch units 24-1. Latches the data at the specified time. The CPU 30 sends the angle data latch 27
Angle information is read through -1... 27-4. As described above, since the configuration of the data latch unit is duplicated,
First data latch unit 2 during read operation from PU 30
4-1... 24-4 have an advantage that measurement and data can be changed.

28-4 are time data latches of the third data latch section 32.
.., 28-4 transfer / hold the data of the second data latch units 25-1 to 25-4 at the timing of the speed calculation cycle signal SMPL. The time data latches 28-1 ... 28
-4 can also be read from the CPU 30.

Reference numeral 29 denotes an edge detection section of the third data latch section 32. This detection section 29 also performs a latch operation at the timing of the SMPL signal. The edge detection unit 29 receives data from the edge detection and holding unit 26, is configured by 1 bit, and is readable by the CPU 30.

Reference numeral 31 denotes a controller for outputting a speed calculation period signal SMPL. The controller 31 sends the SMPL signal to the controller 31 based on a timing output from the time measurement counter 23, a latch signal from the CPU 30, a latch signal from an external terminal, and the like. This signal becomes the enable signal EN for the third data latch unit and the edge detection holding unit 26.

The speed detection calculation has the following two means.

(1) When one or more edge detections exist during the SMPL cycle, and (2) When there is no edge detection during the SMPL cycle.

First, the case (1) will be described.
As shown in FIG. 12, the encoder pulse period is long at a low speed (A
Phase, B-phase), even if there are no four types of quadrupled signals during the speed calculation period T _S , if the current detection time is T ₁ , at least between T ₂ → T ₁ When there is one pulse change (t _d and t _e are T ₂ → T _{1 in the} figure)
The speed is calculated using the newer data (the smaller count value) (here, t _e ). The phase is to compute in one period of the pulse, using data time of the corresponding edge a and the value t _a which was detected last CPU.

The difference in phase angle can be calculated by Δθ = θ _e -θ _a. However, for the time, T ₂ → T _e = (T _s −T _e ) T ₃ → T ₂ = T _s T _a → T _d = T _a The sum of the periods over three sample periods: ΔT =
A _{(T s -T e) + T} s + T a.

The speed ω is calculated by the equation ω = Δθ / ΔT. Fast, when the signal of quadruple the sample period each occurs all four types, absent data between the above _{T 3 → T 2, T a} ... T OLD, T e = T New and general form After all,
ω can be calculated by the following equation.

Ω = (θ _New −θ _OLD ) / ｛(T _S −T _New ) + T _{OLD 場合} FIG. 15 shows a case where there is no pulse between T _{3 and} T ₂ as described above. It may be added to the sample period T _S content to a value of T _a, as, if realized added by software, quadrupled signal is not inputted only one pulse in one sample period, the time difference of one period of the previous pulse Exceeds the time measurement counter 23,
The time of the time measurement counter 23 or more can be accurately measured for an integral multiple of the cycle. In addition, if all the quadrupled edge data is stored, no matter which edge occurs at the time of sampling, a cycle of an integral multiple of one cycle of an arbitrary edge can be obtained.

Here, a case where no pulse is generated, such as T _S + T _a , is described. If no corresponding edge is generated by the flags F (0) to F (3), T
If to sum only _S, over what period, without coming edges, the previous value of T _a may be maintained accurately. This may be determined and added for each edge.

Next, a case where there is no edge detection during the SMPL cycle of (2) will be described. FIG. 14A is a timing chart, and FIG. 14B is an explanatory diagram showing the transition of the previous value time data immediately after the SMPL interrupt. ΔT = ZT (0) to
The oldest value (large value) of ZT (3) (FIG. 1)
4B, t _a + 2T _s ), Δθ = 1 (one cycle of encoder)
When the speed estimated value assuming that the edge of the data of the oldest value immediately after a sample of T ₁ is generated is given by the following equation.

Ω = Δθ / ΔT = (1 / ΔT) × Sgn (ω ′) Sgn (ω ′) is the rotation direction polarity of the previous detected speed value.

[0040] If the encoder pulse does not occur until the time of the next sample T _0, ZT ₍₀₎ ~ZT
(3) is added after the speed estimated by T _s, ΔT = t _a
Speed can be estimated at ΔT longer by T _s than last time, such as 3T _s , and even when the pulse input is stopped as shown in FIG. A so-called taumatic operation is performed.

FIG. 16 is a flowchart of the above-described speed detection calculation operation.

According to the speed calculation circuit shown in FIG. 8, the measured values are individually latched for the four types of edges.
Switching of speed calculation can be arbitrarily selected after measurement by a signal (measured between the same edges) or a 4F signal (measured between adjacent edges).

The principle of speed detection using the above-described detection circuit is described in Denki Kagaku D, Vol. 115, No. 11, 1995
Monthly, "Proposal of Overlap Speed Detection Method and Improvement of Characteristics of Speed Observer", Yamamoto, et al.

[0044]

At present, the elevator control device (FIG. 3) uses the speed detection circuit shown in FIG. 8 for speed detection, but has the following problems.

At the start of the operation of the elevator, the control device cannot recognize that the elevator has operated unless four or more pulses from the speed pulse detector come. That is, a time delay occurs in the speed detection at the start of the operation, and the vibration of the car occurs.

Therefore, the mode of the speed detection circuit is switched using the speed detection control flow shown in FIG. 7 so that the speed can be detected when one pulse from the speed pulse detector comes.

At the start of the elevator operation, the detection is performed in the pulse detection section AB in FIG. 6, the speed is detected for each pulse (4F mode) up to the pulse position D, and the pulse position E, that is, 5 is detected. From the first pulse, between A and E,
Subsequently, the time between B and F is measured at the pulse position F (1F
Mode), the speed is detected. This makes it possible to perform speed detection with high detection accuracy.

Here, the reason why the above-mentioned elevator operates and the speed is detected in the 4F mode until the fifth pulse comes, and thereafter the speed is detected in the 1F mode is that the output of the speed pulse detector is Because the phase error between the phases is large,
In the detection in the 4F mode, a pulse signal cannot be obtained for each speed calculation cycle in a low speed range, so that a delay occurs in speed detection or a detection error is small. Therefore, switching to the 4F mode at a low speed and switching to the 1F mode at a high speed has been performed.

However, the elevator may operate in the opposite direction at the start of operation, depending on the weight of the car and the balancing overlap. That is, the elevator moves in the forward direction after passing the zero speed (stop state).

In this case, when the mode of the speed detection circuit is switched from the fifth pulse, when the reverse operation occurs, the operation of the elevator is recognized unless four or more pulses have passed after the zero speed has elapsed. I can no longer do it.

That is, even if the speed detection circuit and the mode switching method with high detection accuracy shown in FIG. 8 are employed, in the actual use of the elevator, the detection accuracy deteriorates due to the occurrence of the reverse operation.

The present invention has been made in view of the above problems, and has as its object to control the elevator by detecting the speed with high accuracy even when reverse rotation occurs at the time of starting the elevator. An object of the present invention is to provide an elevator speed control device and a recording medium on which an elevator speed detection program is recorded.

[0053]

According to the present invention, there is provided an elevator speed control apparatus comprising: a speed pulse detector attached to a motor; and a signal obtained by quadrupling the signal from the detector by a motor rotation pulse counter. During the counting, the clock counter counts the clock, and calculates a deviation between the speed command value and the speed detection value by detecting a speed of the elevator from the set count value of the motor rotation pulse counter and the count value of the clock counter. In an elevator speed control device provided with a speed control amplifier,
When the zero speed is detected, control is performed to switch the set value of the motor rotation pulse counter from an integral multiple of 4 to an integral multiple of 1, and the set value of the counter is set to 4 by the fifth pulse.
It is characterized by switching to an integral multiple of.

A computer-readable recording medium on which an elevator speed detection program according to the present invention is recorded can be used for controlling an inverter for driving an elevator motor by a computer to operate the elevator.
A recording medium on which a detection control program for detecting a signal from a speed pulse detector attached to the motor and detecting a rotation speed of the motor is recorded, wherein an interval of an edge occurrence time of a signal from the speed pulse detector is determined. The processing is performed to detect the rotation speed, and the measurement interval of the edge generation is switched between the zero speed and the generation of the fifth pulse.

[0055]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In the conventional elevator control device shown in FIG. 3, the circuit shown in FIG. This speed detection circuit is a time measurement counter while the angle measurement counter 22 counts the number of sets of a signal 4F obtained by quadrupling the pulse signal from the speed pulse detector (encoder) 2 (FIG. 3) by the latch signal generation unit 21. Reference numeral 23 counts the clock, and detects the speed of the elevator from the set count value of the angle measurement counter 22 and the count value of the time measurement counter.

In the first embodiment, in the elevator speed control device (FIG. 3) using the speed detection circuit shown in FIG. 8, according to the flow of FIG. Control for switching from an integer multiple to an integer multiple of 1 is performed, and the set number of the counter is switched to an integer multiple of 4 at the fifth pulse.

That is, in step 101 of FIG. 1, it is determined whether or not the detection speed = 0, and in the case of yes,
In step 102, the detection 4F mode set is set, control is performed to switch the set value of the angle measurement counter 22 from an integer multiple of 4 to an integer multiple of 1, and speed detection is performed with the set value of the angle measurement counter 22 set to an integer multiple of 1. To control the elevator.

If the determination of the detection speed = 0 is NO, it is determined in step 103 whether or not the fifth pulse or later is present.
If the answer is yes, the detection 1F mode set is set, and control is performed to switch the set value of the angle measurement counter 22 from an integer multiple of 1 to an integer multiple of 4;
Is set to an integral multiple of 4 to perform speed detection and perform elevator control.

As described above, the determination of the detection speed = 0 and the determination of whether or not the pulse is the fifth or subsequent pulse are performed, and the angle measurement counter 22 is determined.
Is changed, it is possible to detect the speed with high accuracy even when the reverse rotation of the motor occurs at the time of starting the elevator.

Embodiment 2 In the elevator speed control apparatus (FIG. 3), an inverter 1 for driving a motor 1
The computer controls the arithmetic and control unit for controlling 0, and the elevator is operated by the computer. The speed detection circuit 3 is configured by software.

FIG. 2 shows the processing configuration (program) of the speed detection control. Reference numeral 201 denotes a pulse edge time detecting means for detecting an edge generation time interval of a 4F pulse obtained by quadrupling the pulse signal from the speed pulse detector 2 (FIG. 3);
Motor pulse counting means for counting F pulses.

Reference numeral 203 denotes a speed = 0 judgment signal from the zero speed judging means 205, which sets the operation mode of the edge speed measurement speed detection circuit to the detection 1F mode, and detects the operation mode when 5 pulses are counted from the speed ≠ 0 judgment. A speed detection circuit operation mode changing means for changing to the 4F mode and changing the measurement interval of the edge occurrence, a speed calculation means 204 for calculating the speed from the interval of the edge occurrence time, and a 205 for judging the speed = 0 from the calculated speed value. Zero speed determination means.

The speed detection control program is recorded on a recording medium and installed on the computer. Thus, as in the first embodiment, high-precision speed detection is possible even when reverse rotation of the motor occurs at the time of starting an elevator or the like.

[0064]

According to the elevator speed control apparatus of the present invention, when the speed detection circuit detects zero speed, control is performed to switch the set value of the motor rotation pulse counter from an integer multiple of four to an integer multiple of one. Since the set value of the counter is switched to an integral multiple of 4 at the fifth pulse, high-precision speed detection can be performed even when reverse rotation occurs at the time of starting the elevator or the like. Therefore, high-precision speed control becomes possible.

The speed detecting circuit can be constituted by changing software of an elevator speed control device using a computer.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method of switching an operation mode of a speed detection circuit according to a first embodiment;

FIG. 2 is a configuration diagram of a speed detection process according to a second embodiment;

FIG. 3 is a block diagram of an elevator speed control device.

FIG. 4 is a block configuration diagram of a speed detection circuit according to a conventional example.

FIG. 5 is a waveform chart showing an example of a quadruple frequency waveform.

FIG. 6 is a diagram illustrating characteristics of a speed pulse detector.

FIG. 7 is a flowchart of speed detection control according to a conventional example.

FIG. 8 is a block diagram of a speed detection circuit according to another conventional example.

FIG. 9 is a timing chart of a latch creation unit.

FIG. 10 is a timing chart of an angle measurement counter.

FIG. 11 is a timing chart of a time measurement counter.

FIG. 12 is a timing chart for explaining speed detection calculation when there is one or more edge detections;

FIG. 13 is a timing chart illustrating speed detection calculation.

14A is a timing chart for explaining speed detection calculation when there is no edge detection, and FIG. 14B is a diagram for explaining previous value time data.

FIG. 15 is a timing chart of the speed detection calculation when the pulse input is stopped.

FIG. 16 is a flowchart illustrating speed detection calculation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Elevator motor 2 ... Speed pulse detector 3 ... Speed detection circuit 4 ... Speed control amplifier 10 ... Inverter 15 ... Motor rotation pulse counter 16 ... Clock counter 17 ... Counter synchronization control unit 21 ... Latch signal creation unit 22 ... Angle measurement Counter (motor rotation pulse counter) 23 time counter (clock counter) 24-1 to 24-4 first data latch unit 25-1 to 25-4 second data latch unit 26 edge detection holding unit 27- 1-27-4, 28-1 to 28-4, 29 ... third
Data latch unit 30 CPU 31 Controller

Continued on the front page (72) Inventor Kenji Yamada 2-1-117 Osaki, Shinagawa-ku, Tokyo Inside the company Meidensha Co., Ltd. (72) Inventor Koji 2-1-1, Osaki, Shinagawa-ku, Tokyo Co., Ltd. Meidensha Co., Ltd. F term (reference) 3F002 CA05 DA02 GA09 3F303 CB12 CB13 FA01 FA02 5H550 AA07 BB05 HB08 JJ12 JJ14 JJ16 LL06 LL22

Claims (2)

[Claims] 1. A speed pulse detector attached to a motor, and a clock counter counts a clock while a motor rotation pulse counter counts a set of signals obtained by quadrupling the signal from the detector. In an elevator speed control device including a speed detection circuit that detects an elevator speed from a set count value of a pulse counter and a count value of a clock counter, and a speed control amplifier that calculates a deviation between a speed command value and a detected speed value, When the speed is detected, control is performed to switch the set value of the motor rotation pulse counter from an integral multiple of 4 to an integral multiple of 1, and the fifth pulse changes the set value of the counter to 4
A speed control device for an elevator, wherein the speed is switched to an integral multiple of the speed. 2. A detection control program for detecting a signal from a speed pulse detector attached to the motor and detecting a rotation speed of the motor when operating the elevator by controlling an inverter for driving the motor of the elevator by a computer. A rotation speed is detected by processing an interval of an edge occurrence time of a signal from the speed pulse detector, and the measurement interval of the edge occurrence is set to zero speed and a fifth pulse generation. A computer-readable recording medium recording an elevator speed detection program, which is switched at a time.