JP2000036728A - Circuit and method for generating clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit capable for reducing the number of multiplication of a multiplied clock, without increasing delay element or the like by detecting any specified multiplied clock out of phase-delayed multiplied clock by a phase synchronizing means and dividing the frequency of the multiplied clock with the time point of that detection as a reference. SOLUTION: When a DL-ACT at an H level is outputted from a set/reset flip-flop 16, a pulse counter 14 of a multiplying part 11 outputs a pulse C3 corresponding to a third clock watched from the rising edge of an input clock and outputs a pulse C4 corresponding to a fourth clock. When a multiplication number switching signal X3CNT is at an H-level, in order to multiply the frequency of the input clock triple, a multiplication number switching circuit 15 selectively outputs the pulse C3 without outputting the pulse C4, even when it is received. When the rising edge of the input clock is detected, in order to start oscillating the multiplied clock, the set/reset flip-flop 16 transits the signal level of DL-ACT into the H-level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit and a clock generation method for generating a divided clock or a multiplied clock having the same cycle as an input clock.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, IEICE Technical Report Vol. 9
7, No. 106 (issued in June 1997), is a configuration diagram showing a conventional clock generation circuit shown on pages 29 to 36, in which 1 denotes a multiplied clock obtained by multiplying the frequency of an input clock. 2 is a ring oscillator constituted by using a digital delay line 3 for delaying a multiplied clock, 3 is a digital delay line of the ring oscillator 2, and 4 is a digital delay line 3.
5 is a phase comparator that compares the phase of the input clock with the phase of the feedback clock output from the driver 9 and updates the counter value of the counter 7 in accordance with the phase difference. While delaying the multiplied clock generated by the circuit 1 to make the phase of the feedback clock coincide with the phase of the input clock,
A phase synchronization circuit that uses the multiplied clock after the delay as a PLL output, 7 is a counter of the phase synchronization circuit 6, 8 is a delay time corresponding to the counter value of the counter 7, and a multiplication circuit 1
Is a digital delay line for delaying the multiplied clock generated by the above. The digital delay line 8 includes a plurality of delay elements and a decoder. Reference numeral 9 denotes a driver that outputs the PLL output output from the phase synchronization circuit 6 to the phase comparator 5 as a feedback clock, and 10 denotes a driver that supplies the PLL output output from the phase synchronization circuit 6 to each block.

Next, the operation will be described. First, a clock generation circuit (hereinafter, PLL (Phase Locked)
Loop) is a circuit that generates a clock of the same cycle or a multiplied clock synchronized with the input clock. A recent microprocessor operates with a very high-speed clock of several tens to several hundreds of MHz. Built-in is mandatory.

A conventional PLL employs an analog PLL that controls the oscillation frequency by controlling the voltage of a capacitor holding a control voltage of a voltage controlled oscillator VCO using a charge pump. But,
The analog PLL is difficult to control at a low voltage, is susceptible to noise, and has a long time required for the operation to stabilize (lock time). Therefore, once the input clock stops, the PLL oscillation stops. There is a problem that it takes a long time to operate again.

Therefore, in the conventional example shown in FIG. 10, in order to solve such a problem, a digital delay line
L. Specifically, first, PL
When L receives the input clock, the digital delay line 3 of the multiplier 1 multiplies the frequency of the input clock by
A multiplied clock to be supplied to each block is generated (PL
L output), and the phase of the multiplied clock must match the phase of the input clock. Therefore, the phase comparator 5 and the phase synchronization circuit 6 perform the following phase synchronization processing.

That is, the phase comparator 5 compares the phase of the multiplied clock generated by the multiplying circuit 1 with the phase of the feedback clock (corresponding to the PLL output) output from the driver 9, and the phase difference is within an allowable range. Is determined. If the phase difference is within the allowable range, it is determined that the phase of the multiplied clock matches the phase of the input clock, and the counter 7 in the phase synchronization circuit 6
(The delay time of the phase synchronization circuit 6 is maintained), but if the phase difference is out of the allowable range, the phase of the multiplied clock does not match the phase of the input clock. Then, the counter value of the counter 7 is updated according to the phase difference (the counter value is increased or decreased), and the delay time of the phase synchronization circuit 6 is adjusted.

When the counter value of the counter 7 is set in this way, the digital delay line 8 of the phase synchronization circuit 6 delays the multiplied clock according to the counter value of the counter 7, and the delayed multiplied clock Is output to the drivers 9 and 10 as PLL outputs. As shown in FIG. 11, the digital delay line 8 finally adjusts the rising edge of the input clock to match the rising edge of the feedback clock with the rising edge of the input clock. The rising edge of the previous multiplied clock is delayed from the edge.

Therefore, the maximum delay time of the digital delay line 8 corresponds to one cycle of the multiplied clock,
The maximum delay time of the digital delay line 3 of the multiplying circuit 1 constituting the ring oscillator 2 corresponds to a half cycle of the multiplied clock. However, the maximum delay time of the digital delay line 8 depends on the cycle of the multiplied clock. For example, in order to reduce power consumption, a P multiplied by 1 is used.
When LL output is generated (period of input clock and PLL
When the output cycle is the same), digital delay line 8
Is equivalent to the time of one period of the PLL output, and the number of delay elements of the digital delay line 8 is
This is four times as large as the case where the multiplication number is four.

[0009]

Since the conventional clock generation circuit is configured as described above, if the multiplication number of the multiplied clock is reduced, the maximum delay time of the digital delay line 8 must be increased accordingly. It is necessary to install many delay elements and decoders,
Since the delay element and the decoder have a large occupied area, there is a problem that if the multiplication number of the multiplication clock is reduced, the circuit scale becomes large, and the cost of the chip increases. Further, since the multiplication number of the multiplication clock is fixedly used, there is also a problem that once the chip is generated, the multiplication number cannot be easily changed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a clock generation circuit and a clock generation method capable of reducing the number of multiplications of a clock without increasing the number of delay elements and the like. The purpose is to gain. Another object of the present invention is to provide a clock generation circuit and a clock generation method capable of changing the multiplication number of the multiplied clock as needed.

[0011]

A clock generation circuit according to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases have been delayed by the phase synchronizing means, generates the multiplied clock based on the detected time. The frequency is divided.

[0012] The clock generation circuit according to the present invention includes a multiplied clock whose phase is delayed by the phase synchronization means.
When a specific multiplied clock is detected, the frequency of the multiplied clock is divided based on the detection time, and the delay of the frequency dividing means is added to the multiplied clock whose phase has been delayed by the phase synchronization means.

The clock generation circuit according to the present invention is configured to convert either one of the divided clock generated by the frequency dividing means and the multiplied clock to which the delay has been added by the delay adding means into a PL.
This is selected as the L output.

In the clock generation circuit according to the present invention, the multiplier is switched according to the multiplier switching signal.

The clock generation circuit according to the present invention counts the number of pulses of the multiplied clock, and stops the generation of the multiplied clock in the ring oscillator when the number of pulses matches the multiplied number.

A clock generating circuit according to the present invention generates an n-multiplied clock and divides the n-multiplied clock by m.

The clock generation circuit according to the present invention includes a ring oscillator for adjusting a delay time by using a digital delay line composed of a transistor whose current changes when a gate voltage changes.

The clock generation circuit according to the present invention includes a ring oscillator for adjusting a delay time using a digital delay line composed of a transistor whose current changes when the back gate voltage changes.

The clock generation circuit according to the present invention is provided with phase synchronization means for adjusting a delay time by using a digital delay line composed of a transistor whose current changes when the gate voltage changes.

The clock generation circuit according to the present invention is provided with a phase synchronization means for adjusting a delay time using a digital delay line composed of a transistor whose current changes when the back gate voltage changes.

In the clock generation method according to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases have been delayed, the frequency of the multiplied clock is divided based on the detection time.

In the clock generation method according to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases are delayed, the frequency of the multiplied clock is divided based on the detected time, and the multiplied clock whose phase is delayed is used. This is to add a delay of the frequency division processing to the clock.

In the clock generating method according to the present invention, the multiplier is switched according to the multiplier switching signal.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a clock generation circuit according to a first embodiment of the present invention.
Is a multiplying unit (multiplier) for multiplying the frequency of the input clock to generate a multiplied clock, and 12 delays the phase of the multiplied clock generated by the multiplying unit 11 and provides a feedback clock (corresponding to a divided clock). The phase synchronization unit (phase synchronization means) 13 that matches the phase of the input clock with the phase of the input clock detects a phase synchronization clock immediately before the falling of the input clock out of the phase synchronization clocks output from the phase synchronization unit 12. A frequency dividing circuit (frequency dividing means) that divides the phase synchronous clock based on the detection time and outputs the feedback clock to the phase synchronous section 12.

When the H-level DL-ACT is output from the set / reset flip-flop 16, the pulse C3 is output at the third clock as seen from the rising edge of the input clock, and the pulse C4 is output at the fourth clock.
The pulse counter 15 outputs a multiplication number switching signal X3
When CNT is at the H level, the pulse C3 is selected and output. When the multiplier switching signal X3CNT is at the L level, the pulse switching circuit X4 is selected and output.
6 detects the rising edge of the input clock,
A set-reset flip-flop, which changes the signal level of the DL-ACT to the L level when the pulse C3 or the pulse C4 is output from the multiplier switching circuit 15 while the signal level of the L-ACT changes to the H level, 17 Detects the rising edge of the input clock,
While the signal level of T transitions to the L level, when the L-level DL-OUT is output, the set-reset flip-flop that transitions the signal level of the DL-STAT to the H level, and 18 is a set-reset flip-flop 16
D-flip-flop for synchronizing DL-ACT output from the
An OR gate that outputs a PLL-Reset when the DL-ACT or the external reset output from the flip-flop 18 is input.

Reference numeral 20 denotes an input clock that is divided by 2 to obtain 2
A divide-by-2 circuit 21 for generating a divided clock compares the phase of the divide-by-2 clock generated by the divide-by-2 circuit 20 with the phase of the multiplied clock output from the AND gate 30,
If the phase difference is out of the allowable range, the phase comparator that outputs an up signal or a down signal,
When the PLL-Reset is output from the gate 19, the counter value is reset to zero, and when an up signal or a down signal is output from the phase comparator 21, the counter increments or decrements the counter value. Is a decoder that decodes the upper 7 bits of the counter and outputs a 96-bit control signal, and 24 is a decoder that decodes the lower 3 bits of the counter value of the counter 22 and outputs an 8-bit control signal.

Reference numeral 25 denotes a fixed delay element for delaying the multiplied clock output from the AND gate 30;
Reference numeral 6 denotes a digital delay line that finely delays the multiplied clock according to the control signal output from the decoder 24, 27 denotes a digital delay line that coarsely delays the multiplied clock according to the control signal output from the decoder 23, and 29 denotes a DL-STAT. When the level becomes the H level, the OR gate 30 forcibly transits the DL-OUT output from the digital delay line 27 to the H level.
When ACT goes to L level, AND-OUT forcibly transitions DL-OUT to L level to close the ring oscillator.
The gate 31 outputs a lock detection signal when the phase comparator 21 detects the coincidence of the phases.
A Lock detector that stops outputting the lock detection signal when Reset is output. The delay element 2
5, Digital delay line 26, 27, OR gate 2
9 and an AND gate 30 constitute a ring oscillator.

Numeral 32 denotes the phase of the input clock and the driver 43
The phase comparator 33 compares the phase of the feedback clock output from the phase comparator 32 and outputs a UP signal or a DOWN signal when the phase difference deviates from an allowable range. When the signal is output, a counter that increments or decrements the counter value, a decoder 34 decodes the upper 5 bits of the counter value in the counter 33, and outputs a 32-bit control signal, and a decoder 35 outputs the lower 3 bits of the counter value in the counter 33. A decoder that decodes and outputs an 8-bit control signal, 36 is a digital delay line that finely delays the multiplied clock according to the control signal output from the decoder 35, and 37 is a coarsely multiplied clock according to the control signal output from the decoder 34 Digital delay to delay It is in.

A shift register 39 detects a phase-locked clock immediately before the falling of the input clock out of the phase-locked clocks output from the phase-locked section 12, detects the phase-locked clock, and outputs a X1RST shift register. Reference numeral 40 denotes a divide-by-4 circuit which divides the phase-locked clock by 4 based on the time when X1RST is output from the shift register 39, and 41 denotes a divide-by-4 circuit by which the phase-locked clock output from the phase synchronizer 12 is divided A fixed delay element (delay adding means) for adding a delay of 40, 42 selects the divide-by-4 clock output from the divide-by-4 circuit 40 as a PLL output when the multiple switching signal X1CNT is at the H level. When the multiplier switching signal X1CNT is at the L level, the phase synchronization clock output from the delay element 41 is used as the PLL output. Select the selector (selection means),
A driver 43 outputs the PLL output output from the selector 42 to the phase comparator 32 as a feedback clock, and a driver 44 supplies the PLL output output from the selector 42 to each block. FIG. 9 is a flowchart showing a clock generation method according to the first embodiment of the present invention.

Next, the operation will be described. First, when the pulse counter 14 of the multiplier 11 outputs the H-level DL-ACT from the set / reset flip-flop 16, as shown in FIG. 4, the pulse C3 at the third clock as viewed from the rising edge of the input clock. And outputs a pulse C4 at the fourth clock (step ST1).

When the multiplier switching signal X3CNT is at the H level, the multiplier switching circuit 15 selects the pulse C3 without receiving the pulse C4, in order to triple the frequency of the input clock. Output. On the other hand, when the multiplier switching signal X3CNT is at the L level, the frequency of the input clock is multiplied by four, so that even if the pulse C3 is received, it is not output, and the pulse C3 is selected and output.

When the set / reset flip-flop 16 detects the rising edge of the input clock, it starts oscillating the multiplied clock.
Is changed to the H level while the pulse switching circuit 15 outputs the pulse C3 or the pulse C4.
Since the set multiplication number is secured, the signal level of DL-ACT transits to L level. Thereby, when DL-ACT becomes L level, the AND gate 30 closes the ring oscillator, so that as shown in FIG.
The UT (multiplied clock) is forcibly shifted to the L level (step ST2).

The set-reset flip-flop 17 forcibly transitions the signal DL-OUT to the H level when the multiplied clock is delayed more than necessary (FIG. 4).
See).

On the other hand, the divide-by-2 circuit 20 sets the input clock to 2
When the frequency is divided to generate a frequency-divided clock, the AND gate 3
In order to make the phase of the multiplied clock output from 0 coincide with the phase of the divide-by-2 clock, the phase comparator 21 compares the phase of the divide-by-2 clock with the phase of the multiplied clock, and the phase difference falls within an allowable range. It is determined whether or not there is (step ST
3).

If the phase difference is within the allowable range, the phase comparator 21 determines that the phase of the multiplied clock coincides with the phase of the frequency-divided clock, and detects the lock detection signal by Lock detection. Output to the oscillator 31 and maintain the counter value of the counter 22 (maintain the delay time of the ring oscillator). Even if the lock detection signal is output, if a phase difference occurs due to temperature or other effects, a process for canceling the phase difference is performed in the same manner as in a case where the phase difference deviates from an allowable range described later. I do. However, when the lock detection signal is output, the PLL is output from the OR gate 19 to the PLL.
Output is not stopped unless Reset is output. On the other hand, if the phase difference deviates from the allowable range, it is determined that the phase of the multiplied clock does not match the phase of the divided-by-2 clock, and an up signal or a down signal is output to the counter 22. To update the counter value (step ST4).

Thus, when the up signal is output from the phase comparator 21, the counter value of the counter 22 becomes 1
When the signal is incremented and a down signal is output,
The counter value of the counter 22 is decremented by one. Then, the decoder 23 decodes the upper 7 bits of the counter value in the counter 22 in order to roughly bring the phase of the multiplied clock closer to the phase of the divided-by-2 clock,
A 96-bit control signal is output. On the other hand, the decoder 24
Decodes the lower 3 bits of the counter value in the counter 22 and outputs an 8-bit control signal in order to make the phase difference as close to zero as possible.

In this way, the decoder 24 outputs 8 bi
When the control signal of t is output, the digital delay line 26 finely delays the multiplied clock according to the 8-bit control signal output from the decoder 24 (step ST5). As shown in FIG. 5, the digital delay line 26 includes eight delay elements having slightly different delay times.
Are connected in parallel, and the delay time can be finely adjusted.

On the other hand, when a 96-bit control signal is output from the decoder 23, the digital delay line 27
The multiplied clock is roughly delayed according to the 96-bit control signal output from the decoder 23 (step ST
5). As shown in FIG.
In this example, 96 delay elements having a delay time ΔD are connected in series, and a multiplied clock is taken into the digital delay line 27 from the delay element selected by the counter value. Therefore, the delay time of the digital delay line 27 can be adjusted in 96 steps by changing the input position.

Note that the initial value of the counter 22 is set to 1 (minimum delay time), and the counter value is incremented by one every two divisions of the input clock. As a result, the delay time gradually increases from the minimum delay time, and the counter value is fixed at the phase of the rising edge of the input clock and the falling edge of the multiplied clock. The maximum delay time of the ring oscillator is a half cycle of the multiplied clock. However, if the multiplication factor is increased, the number of delay elements can be reduced.

The phase synchronizer 12 starts operating when a lock detection signal is output from the lock detector 31. In order to match the phase of the feedback clock output from the driver 43 with the phase of the input clock, , The phase comparator 32 compares the phase of the input clock with the phase of the feedback clock, and determines whether or not the phase difference is within an allowable range (step ST6). If the phase difference is within the allowable range, the phase comparator 32 determines that the phase of the feedback clock matches the phase of the input clock, and maintains the counter value of the counter 33 (digital delay). The delay time of the lines 36 and 37 is maintained). On the other hand, if the phase difference deviates from the allowable range, it is determined that the phase of the feedback clock does not match the phase of the input clock,
An up signal or a down signal is output to the counter 33 to update the counter value (step ST7).

Thus, when the up signal is output from the phase comparator 32, the counter value of the counter 33 becomes 1
When the signal is incremented and a down signal is output,
The counter value of the counter 33 is decremented by one. However, as the initial value of the counter 33, a result obtained by performing a predetermined calculation based on the counter value of the counter 22 at the time when the lock detection signal is output is adopted. Then, the decoder 34 decodes the upper 5 bits of the counter value in the counter 33 to roughly bring the phase of the feedback clock closer to the phase of the input clock, and 32 bits.
The control signal of t is output. On the other hand, the decoder 35 decodes the lower 3 bits of the counter value in the counter 33 to make the phase difference as close to zero as possible, and
The control signal of t is output.

In this way, the decoder 35 outputs 8 bi
When the t control signal is output, the digital delay line 36 finely delays the multiplied clock in accordance with the 8-bit control signal output from the decoder 35 (step ST8). Since the configuration of the digital delay line 36 is the same as that of the digital delay line 26, the description is omitted. On the other hand, when the 32-bit control signal is output from the decoder 34, the digital delay line 37 coarsely delays the multiplied clock according to the 32-bit control signal output from the decoder 34 (step ST8). Although the configuration of the digital delay line 37 is the same as that of the digital delay line 27, the description thereof is omitted,
The number of element stages is different.

Although the maximum delay time of the ring oscillator in the multiplier 11 is a half cycle of the multiplied clock, as described above, the digital delay lines 36 and 37 are used.
Requires the time of one cycle of the multiplied clock, the same delay as the delay elements constituting the digital delay lines 26 and 27 of the ring oscillator is required.
When the digital delay lines 36 and 37 are configured using the ay elements, a delay element twice as large as that of the multiplier 11 is required. Therefore, the delay time of the delay elements of the digital delay lines 36 and 37 is adjusted to be longer than the delay time of the delay elements of the digital delay lines 26 and 27.

FIG. 8 shows a method for increasing the delay time.
As shown in the figure, the gate length of the transistor can be increased,
In addition to the method of shortening the gate width, as shown in FIG.
When using a channel CMOS transistor, Nch C
The delay time is controlled by changing the current by adjusting the gate voltage of the MOS. Also, as shown in FIG.
When an Nch CMOS transistor is used, Nch
The delay time is controlled by changing the current by adjusting the back gate voltage of the CMOS.

Then, the frequency dividing circuit 13
Divides the phase synchronization clock output from
In order to make the phase of the PLL output coincide with the phase of the input clock, first, the shift register 39 sets X1RST at the rising edge of the phase synchronization clock immediately before the input clock falls out of the phase synchronization clock output from the phase synchronization section 12. As shown in FIG. 2, when the rising edge of the phase-locked clock is detected, the divided-by-2 clock is input to the flip-flop group that outputs to the flip-flop of the next stage, as shown in FIG. (See FIG. 2).

When the X1RST is output from the shift register 39, the divide-by-4 circuit 40 divides the phase synchronous clock by 4 with reference to the rising edge of the X1RST to generate a divided clock (step ST10). . Then, the selector 42 sets the multiplication number switching signal X1CNT to H
In the case of the level, the frequency-divided clock output from the divide-by-4 circuit 40 is selected as the PLL output, and the multiplication number switching signal X
When 1CNT is at L level, the phase-locked clock (delay element 41
Selects, as the PLL output, a phase-locked clock to which the delay of the divide-by-4 circuit 40 is added in order to match the phases of the phase-locked clock and the divided clock (step ST1).
1).

The PL output from the selector 42
The L output is supplied to each block via a driver 44, while the phase comparator 32 outputs a feedback clock as a feedback clock.
Is output to

As is clear from the above, the first embodiment
According to this, when the phase-locked clock immediately before the falling of the input clock is detected from the phase-locked clocks output from the phase-locking unit 12, the frequency of the phase-locked clock is divided based on the detected time. Therefore, the phase difference between the feedback clock (divided clock) and the divide-by-2 clock does not need to exceed one cycle of the multiplied clock. As a result, the number of multiplications of the multiplied clock can be reduced without increasing the number of delay elements and the like. Is achieved.

Embodiment 2 In the first embodiment, the phase-locked clock is divided by four in order to generate the PLL output having the same cycle as the input clock. However, the present invention is not limited to this. Is generated and the frequency is divided by m, it is possible to obtain a PLL output multiplied by n / m. Note that the divide-by-4 circuit 4
If 0 is replaced by an m frequency dividing circuit, the lengths of the digital delay lines 26 and 27 of the phase synchronization section 12 fall within 1 / m of the period of the PLL output.

[0050]

As described above, according to the present invention, among the multiplied clocks whose phases have been delayed by the phase synchronization means,
When a specific multiplied clock is detected, the frequency of the multiplied clock is divided based on the detection point, so that the phase difference between the divided clock and the input clock does not have to exceed one cycle of the multiplied clock. And, as a result, delay
There is an effect that the number of multiplication of the multiplied clock can be reduced without increasing the number of elements and the like.

According to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases have been delayed by the phase synchronizing means, the multiplied clock is frequency-divided on the basis of the detected time and the phase synchronizing means is used. Since the delay of the frequency dividing means is added to the multiplied clock whose phase has been delayed, the number of multiplications of the multiplied clock can be reduced without increasing the number of delay elements and the like. This has the effect of being able to output as

According to the present invention, one of the frequency-divided clock generated by the frequency dividing means and the frequency-multiplied clock to which the delay has been added by the delay adding means is selected as the PLL output. Thus, there is an effect that the multiplier of the PLL output can be changed.

According to the present invention, since the multiplier is switched in accordance with the multiplier switching signal, the multiplier of the PLL output can be changed as required.

According to the present invention, the number of pulses of the multiplied clock is counted, and when the number of pulses matches the multiplied number,
Since the generation of the multiplied clock in the ring oscillator is stopped, the multiplied clock can be generated from the input clock.

According to the present invention, since the n-multiplied clock is generated and the n-multiplied clock is divided by m, there is an effect that an n / m-multiplied PLL output can be obtained.

According to the present invention, the delay time is adjusted by using the digital delay line composed of the transistor whose current changes when the gate voltage changes. Therefore, the delay time of the ring oscillator can be easily adjusted. There is an effect that can be.

According to the present invention, since the delay time is adjusted by using the digital delay line composed of the transistor whose current changes when the back gate voltage changes, the delay time of the ring oscillator can be easily adjusted. There is an effect that can be.

According to the present invention, the delay time is adjusted by using the digital delay line composed of the transistor whose current changes when the gate voltage changes, so that the delay time of the phase synchronization means can be easily adjusted. There is an effect that can be.

According to the present invention, the delay time is adjusted by using the digital delay line composed of the transistor whose current changes when the back gate voltage changes, so that the delay time of the phase synchronization means can be easily adjusted. There is an effect that can be adjusted.

According to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases have been delayed, the multiplied clock is divided based on the detected time. The phase difference between the clocks does not need to exceed one cycle of the multiplied clock, and as a result, there is an effect that the number of multiplications of the multiplied clock can be reduced without increasing the number of delay elements and the like.

According to the present invention, when a specific multiplied clock is detected from the multiplied clocks whose phases have been delayed, the frequency of the multiplied clock is divided based on the detected time, and the divided clock is divided into a multiplied clock whose phase is delayed. Since the configuration is such that the delay of the rounding process is added, the number of multiplications of the multiplied clock can be reduced without increasing the number of delay elements and the like, and the multiplied clock can be output as a PLL output. effective.

According to the present invention, since the multiplier is switched in accordance with the multiplier switching signal, the multiplier of the PLL output can be changed as required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a detailed configuration of a frequency dividing circuit.

FIG. 3 is a timing chart of various signals.

FIG. 4 is a timing chart of various signals.

FIG. 5 is a configuration diagram showing a detailed configuration of a digital delay line.

FIG. 6 is a configuration diagram showing a detailed configuration of a delay element.

FIG. 7 is a configuration diagram illustrating a detailed configuration of a delay element.

FIG. 8 is a configuration diagram showing a detailed configuration of a delay element.

FIG. 9 is a flowchart showing a clock generation method according to the first embodiment of the present invention.

FIG. 10 is a configuration diagram showing a conventional clock generation circuit.

FIG. 11 is a timing chart of various signals.

[Explanation of symbols]

11 multiplication unit (multiplication unit), 12 phase synchronization unit (phase synchronization unit), 13 divider circuit (division unit), 41 del
ay element (delay adding means), 42 selector (selecting means).

Claims (13)

[Claims] 1. A multiplying means for multiplying the frequency of an input clock to generate a multiplied clock, and a phase of the multiplied clock generated by the multiplying means is delayed so that the phase of the divided clock is changed to the phase of the input clock. When a specific multiplied clock is detected from the phase synchronizing means to be matched and the multiplied clock whose phase has been delayed by the phase synchronizing means, the multiplied clock is frequency-divided based on the detection time point, and A clock generating circuit comprising: a frequency dividing means for outputting to a phase synchronizing means. 2. A multiplying means for multiplying the frequency of an input clock to generate a multiplied clock, and a phase of the multiplied clock generated by the multiplying means is delayed so that the phase of the divided clock is changed to the phase of the input clock. When a specific multiplied clock is detected from the phase synchronizing means to be matched and the multiplied clock whose phase has been delayed by the phase synchronizing means, the multiplied clock is frequency-divided based on the detection time point, and A clock generating circuit comprising: a frequency dividing means for outputting to a phase synchronizing means; and a delay adding means for adding a delay of the frequency dividing means to a multiplied clock whose phase is delayed by the phase synchronizing means. 3. A selecting means for selecting either a frequency-divided clock generated by the frequency dividing means or a frequency-multiplied clock to which a delay has been added by the delay adding means as a PLL output. A clock generation circuit as described. 4. The clock generating circuit according to claim 1, wherein the multiplying means switches the multiplication number according to a multiplication number switching signal. 5. A ring oscillator that generates a multiplied clock, and a stop circuit that counts the number of pulses of the multiplied clock and stops the generation processing of the multiplied clock in the ring oscillator when the number of pulses matches the multiplied number. 5. The clock generation circuit according to claim 4, wherein the multiplication means is configured by using a multiplication means. 6. The clock generating circuit according to claim 5, wherein the multiplying means generates an n-multiplied clock, and the dividing means divides the n-multiplied clock by m. 7. The clock generation circuit according to claim 6, wherein the ring oscillator adjusts the delay time using a digital delay line composed of a transistor whose current changes when the gate voltage changes. 8. The clock generation circuit according to claim 6, wherein the ring oscillator adjusts the delay time using a digital delay line composed of a transistor whose current changes when the back gate voltage changes. 9. The phase synchronization means according to claim 1, wherein the phase synchronization means adjusts the delay time by using a digital delay line comprising a transistor whose current changes when the gate voltage changes. The clock generation circuit according to claim 1. 10. The method according to claim 1, wherein the phase synchronization means adjusts the delay time using a digital delay line composed of a transistor whose current changes when the back gate voltage changes. A clock generation circuit according to any one of the preceding claims. 11. A multiplied clock is generated by multiplying the frequency of an input clock, and the phase of the multiplied clock is delayed so that the phase of the divided clock matches the phase of the input clock while the phase is delayed. A clock generation method that, when a specific multiplied clock is detected from the multiplied clocks, divides the frequency of the multiplied clock based on the detected time to generate a divided clock. 12. A multiplied clock is generated by multiplying the frequency of an input clock, and the phase of the multiplied clock is delayed so that the phase of the divided clock matches the phase of the input clock while the phase is delayed. When a specific multiplied clock is detected from the multiplied clocks, the multiplied clock is frequency-divided based on the detected time, a frequency-divided clock is generated, and the phase-delayed frequency-multiplied clock is delayed. Clock generation method to add 13. The multiplication number is switched according to a multiplication number switching signal.
2. The clock generation method according to 2.