JP2000032072A - Qpsk demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed performance for establishing phase locking and stable tracking performance for maintaining synchronization. SOLUTION: The QPSK demodulator that demodulate data based on an in-phase component signal and a quadrature component signal that are generated by a local oscillation signal and a QPSK modulation wave signal, is provided with a sampling means that samples both the component signals at a rate being a multiple of N of a symbol rate to generate N-sets of in-phase component data and N-sets of quadrature component data, a primary conversion circuit 16 that detects both the component data to produce the N-sets of in-phase component data and N-sets of quadrature component data, inner outer product arithmetic sections 17a-17d that equivalently calculate inner products and outer products between each vector based on the both component data sampled as to one period of a symbol rate and each vector based on both the component data sampled at N-preceding time, and a data demodulation section 19 that detects a symbol point based on the inner product and the outer product to demodulate modulation data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a QPK which demodulates modulated data from a QPSK modulated wave signal modulated by a QPSK (Quadrature Pase-Shift keying, Quadrature Phase Shift Keying) system such as .pi.
The present invention relates to an SK demodulator.

[0002]

2. Description of the Related Art As this kind of QPSK demodulator, FIG.
3 is conventionally known. The demodulator 51 includes a quadrature demodulator 2, a local oscillator circuit 3 for outputting a local signal, A / D converters 4 and 5, a sample timing control circuit 52, a demodulation processing circuit 53, a symbol synchronization holding circuit 54, and an AFC (Automatic Frequency Control
l) The processing circuit 55 and the reference signal SREF of a predetermined frequency
And a reference oscillation circuit 56 for oscillating.

In this demodulation device 51, when a QPSK-modulated received signal is input, the quadrature demodulator 2 outputs the received signal and the quadrature demodulator 2 at the same frequency as the received signal output from the local oscillation circuit 3 and orthogonal to each other. By mixing the two local signals SLI and SLQ with each other, an in-phase component signal SI and a quadrature component signal SQ, which are baseband signals, are generated. Next, the A / D converters 4 and 5
In-phase component data SI and quadrature component data DQ are generated by sampling the in-phase component signal SI and the quadrature component signal SQ in synchronization with the sampling signal SS output from the sample timing control circuit 52. Thereafter, the demodulation processing circuit 53 generates demodulated data based on both the component data DI and DQ.

In these operation processes, the symbol synchronization holding circuit 54 uses a PLL (Phase Lock) provided therein.
ed Loop) causes the circuit to oscillate synchronously with the synchronizing signal SSYN output from the demodulation processing circuit 53 at the same frequency as the symbol frequency of the symbol synchronizing signal included in the received signal, and the oscillation output is symbol-synchronized. The signal is output to the sample timing control circuit 52 as a symbol holding control signal SC. On the other hand, the sample timing control circuit 52 converts the sampling signal SS generated by dividing the frequency of the reference signal SREF output from the reference oscillation circuit 56 into A so that the phase is synchronized with the input control signal SC.
/ D converters 4 and 5. As a result, the sampling signal SS has the same frequency as the symbol rate of the received signal and is phase-synchronized, so that the received signal can be orthogonally demodulated.

The AFC processing circuit 55 monitors the control voltage when the PLL circuit in the symbol synchronization holding circuit 54 is locked, and determines whether or not the lock is performed within an appropriate lock range. . When the AFC processing circuit 55 determines that the PLL circuit is not locked in the appropriate lock range, the AFC processing circuit 55 outputs the AFC control signal SAFC
, The reference oscillation frequency of the reference oscillation circuit 56 is slightly corrected. Thereby, the oscillation frequency of the local oscillation circuit 3 becomes equal to the frequency of the received signal,
The A / D converters 4 and 5 provide the two component signals SI without any phase shift even when the frequency of the received signal fluctuates.
, SQ can be sampled properly.

[0006]

However, the conventional demodulator 51 has the following problems. First, in the conventional demodulation device 51, the A / D converters 4 and 5 generate a sampling signal SS for sampling the in-phase component signal SI and the quadrature component signal SQ. The PLL circuit generates the control signal SC. In this case, since the PLL circuit includes a feedback loop, it is difficult to generate the control signal SC following a high symbol rate. Further, the high-speed property required for establishing synchronization and the follow-up property required for maintaining synchronization are mutually contradictory characteristics in terms of response time. For this reason, there is a problem that it is very difficult to simultaneously satisfy a high-speed synchronization establishment and a synchronization holding that can stably follow. On the other hand, by using a feedback loop for establishing synchronization with a short time constant and a feedback loop for maintaining synchronization with a long time constant, the feedback rope is switched when establishing and maintaining synchronization, so that high-speed synchronization can be established and stable. It is also possible to simultaneously satisfy possible synchronization maintenance. However, in such a case, there is a problem that a complicated control process must be performed to switch between the two feedback loops. Further, since it is necessary to optimize constants in a feedback loop and constants in other circuits according to a symbol rate and the like, there is a problem that a complicated design must be performed for each system.

Second, in order to prevent the PLL circuit from being held out of synchronization by noise, the lock range (simultaneous holding range) of the PLL circuit in the symbol synchronization holding circuit 54 is required.
And the cap challenge (synchronization establishment frequency range) is restricted. For this reason, generally, the frequency range of the lock range in consideration of the noise bandwidth is about 1/16 to 1/8 of the symbol rate. Therefore, there is a problem that AFC processing is inevitably required to cope with the frequency deviation of the received signal. At the same time, the reference oscillation circuit 56 is also required to have high frequency stability performance, so that the cost of the reference oscillation circuit 56 also increases. In addition, since the control voltage range of the PLL circuit is narrow, when the frequency deviation of the received signal is large, AF
There is a problem that the C processing itself becomes difficult.

Third, if the lock range of the PLL circuit and the frequency range of the cap challenge are to be expanded even at the expense of loss of synchronization with noise, the following problems will occur. That is, when the sample timing control circuit 52 synchronizes the phase of the sampling signal SS with the control signal SC, the phase deviation increases. Therefore, it is difficult to accurately sample the in-phase component data DI and the quadrature component data DQ at the symbol points.

Fourth, the sample timing control circuit 52
, And the feedback control value of the AFC processing circuit 55 must be optimized according to the symbol rate, and the demodulation method of the demodulation processing circuit 53 must be designed according to the modulation method of the received signal. For this reason, in the conventional demodulation device 51, each time the symbol rate and the modulation method are different, each circuit must be designed so as to adapt to these, the design work is extremely complicated, and the development period is long. There is a problem that is becoming.

Fifth, in the conventional demodulator 51, in order to establish symbol synchronization, first, the sample timing control circuit 52 converts the sampling signal SS into a symbol synchronization signal included in the received signal. Must be generated. For this reason, the signal for symbol synchronization must always be included in the transmission signal, and the transmission speed of the transmission signal is reduced accordingly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its main object to provide a QPSK demodulator having high speed for establishing phase synchronization and stable tracking for maintaining synchronization. It is another object of the present invention to provide a QPSK demodulator capable of reliably demodulating without performing AFC processing even if a QPSK modulated wave signal has a certain frequency shift. It is another object of the present invention to provide a QPSK demodulator capable of demodulating various types of QPSK modulated wave signals without changing the configuration. Further, it is possible to provide a QPSK demodulation device which can be easily designed to adapt to a symbol rate of a QPSK modulated wave signal, and to provide a QPSK capable of increasing a transmission speed.
Yet another object is to provide a K demodulator.

[0012]

According to a first aspect of the present invention, there is provided a QPSK demodulator for mixing an in-phase component signal and a quadrature component signal by mixing two local oscillation signals orthogonal to each other and a QPSK modulated wave signal. Respectively, and
In a QPSK demodulator for demodulating modulated data from a QPSK modulated wave signal based on both component signals, an in-phase component signal and a quadrature component signal are respectively converted to a symbol rate N (N
Is an integer) times the sampling rate and N
Sampling means for generating N in-phase component data and N quadrature component data, and N in-phase component data DI0 to DI (n-1 ) And N pieces of quadrature component data DQ0 to DQ (n-1), in-phase component data DI0 to DI (n-1) and quadrature component data D sampled for one cycle of the symbol rate.
Each of the vectors based on Q0 to DQ (n-1), and the in-phase component data DI0 to DI (n-1) and the quadrature component data D sampled N times before each of the vectors, respectively.
An inner and outer product operation unit for equivalently calculating an inner product value and an outer product value between vectors based on Q0 to DQ (n-1), and a symbol based on the inner and outer product values calculated by the inner and outer product operation unit A data demodulator for detecting points and demodulating modulated data based on detected in-phase component data DI0 to DI (n-1) and quadrature component data DQ0 to DQ (n-1) corresponding to symbol points. It is characterized by having.

According to a second aspect of the present invention, in the QPSK demodulator of the first aspect, the data demodulator detects a symbol point based on an integrated value of the calculated inner product value and outer product value. Features.

According to a third aspect of the present invention, in the QPSK demodulator according to the first aspect, the data demodulating section performs symbol symbolizing based on an integrated value of the calculated absolute value of the inner product value and the absolute value of the outer product value. It is characterized by detecting points.

According to a fourth aspect of the present invention, in the QPSK demodulation apparatus according to the first aspect, the data demodulation unit is configured to perform the operation based on an absolute value of a difference between the calculated absolute value of the inner product value and the absolute value of the outer product value. And detecting a symbol point.

According to a fifth aspect of the present invention, in the QPSK demodulation apparatus according to any one of the second to fourth aspects, the data demodulation section includes a continuous M (M is an integer) number of integrated values or absolute values. It is characterized in that symbol points are detected based on the average value.

According to a sixth aspect of the present invention, there is provided a QPSK demodulator according to any one of the first to fifth aspects, wherein the primary conversion circuit is equivalent to the in-phase component data before detection and corresponding to the same. Detection is performed by multiplying a vector based on the generated quadrature component data and a complex conjugate vector of a vector based on the in-phase component data sampled N times earlier and the corresponding quadrature component data with each other. .

According to a seventh aspect of the present invention, in the QPSK demodulator according to any one of the first to sixth aspects, the primary conversion circuit corrects the primary conversion amount based on the inner product value and the outer product value to perform detection. It is characterized by doing.

According to an eighth aspect of the present invention, there is provided the QPSK demodulator according to any one of the first to seventh aspects, wherein the frequency of the local oscillation signal is corrected based on the inner product value and the outer product value. .

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a QPSK demodulator according to the present invention will be described below with reference to the accompanying drawings. Note that the same components as those of the conventional demodulation device 51 are denoted by the same reference numerals, and redundant description will be omitted.

The QPSK demodulator 1 shown in FIG. 1, for example, converts carrier waves in the 900 MHz band to "0,0", "0,
For example, a high-frequency signal that is π / 4-shifted QPSK-modulated based on quaternary modulation data of “1”, “1,0” and “1,1”, and a high-frequency signal that is QPSK-modulated based on the quaternary modulation data It is configured so that original quaternary data can be demodulated from various QPSK modulated wave signals. Hereinafter, an example of demodulating a received signal as a high-frequency signal subjected to π / 4 shift QPSK modulation will be described.

First, a specific configuration of the QPSK demodulator 1 will be described.

As shown in FIG. 1, a QPSK demodulator 1
Is the same as the conventional demodulator 51, the quadrature demodulator 2,
Local oscillation circuit 3, A / D converters 4 and 5 corresponding to sampling means in the present invention, and reference oscillation circuit 7
A fixed frequency dividing circuit 6 for dividing the reference signal SREF output from the reference oscillation circuit 7 by a fixed frequency dividing number to generate a sampling signal SS, and a demodulation processing circuit 8
And In the QPSK demodulation apparatus according to the present invention, a π / 4-shifted QPSK modulated wave signal as a received signal is based on in-phase component data DI and quadrature component data DQ sampled at a sampling rate N times the symbol rate. In the embodiment of the present invention, an example will be described in which data is demodulated based on in-phase component data DI and quadrature component data DQ obtained by sampling received data at a sampling rate four times the symbol rate.

Next, each component will be described. The fixed frequency dividing circuit 6 generates the sampling signal SS by dividing the reference signal SREF output from the reference oscillation circuit 7 by a fixed frequency. In this case, for example, the symbol rate of the received signal is 4800 symbols (symbol per secon).
In the case of d), the fixed frequency dividing circuit 6 divides the reference signal SREF by a predetermined frequency dividing number to obtain a symbol rate of 4
19200 Hz sampling signal S which is twice the frequency
Generate S. For this reason, the A / D converters 4 and 5
By sampling the received signal at a sampling rate of 200 sps (sample per second), four in-phase component data DI and 4
The orthogonal component data DQ are generated.

As shown in FIG. 4A, the A / D converter 4 samples four symbol periods of the received signal at sampling points a to d in synchronization with the sampling signal S s, thereby obtaining four signals. In-phase component data DI is generated. The A / D converter 5 samples the four orthogonal signals by sampling at the sampling points a to d in synchronization with the sampling signal SS for each one symbol period of the received signal, as shown in FIG. The component data DQ is generated.

As shown in FIG. 2, the demodulation processing circuit 8 includes memories 11 to 15, a primary conversion circuit 16, an inner and outer product operation circuit 1,
7a to 17d, averaging circuits 18a to 18d, and a numerical value judging circuit 19 corresponding to a data demodulation unit in the present invention.

The memory 11 stores data (YIB0, YIB1, YIB2,...) As in-phase component data DI generated by the A / D converter 4 sampling the received signal.
YIBm... (Hereinafter referred to as “in-phase component data YIB”).
Are the data (YQB0, YQB1, YQB2,..., YQBm,...) As the orthogonal component data DQ generated by the A / D converter 5 sampling the received signal. YQB ”)
Is temporarily stored. The primary conversion circuit 16 detects the in-phase component data DI and the quadrature component data DQ stored in the memories 11 and 12 by primary conversion, and detects the detected data (YIA) as the in-phase component data DI.
0, YIA1, YIA2,..., YIAm... (Hereinafter, also referred to as "in-phase component data YIA") are temporarily stored in the memory 14, and the detected quadrature component data DQ ( YQA0, YQA1, YQA2,
... YQAm (hereinafter, this data is also collectively referred to as “orthogonal component data YQA”) is temporarily stored in the memory 15. The memory 13 temporarily stores an intermediate operation result in the primary conversion operation by the primary conversion circuit 16.

The inner / outer product operation circuits 17a to 17d have substantially the same configuration. The inner and outer product operation circuit 17a is
Every four in-phase component data YIA, that is, data (YIA0, YIA4) sampled at a sampling point a of each symbol period shown in FIG.
,... YIA (4n)) and every fourth data of the orthogonal component data YQA, that is, data (YQA0, YQA4,..., YQA) sampled at the sampling point a of each symbol period shown in FIG. (4n)), the inner product and the outer product between the in-phase component data YIA and the quadrature component data YQA, and the integrated value of the absolute value of the inner product and the absolute value of the outer product are calculated. In this case, by calculating the absolute values of the two, the calculation for obtaining the minimum value of the integrated value described later becomes easy. Note that, depending on the calculation method, the integrated value of the inner product and the outer product may be calculated. Also,
Similarly, the inner / outer product operation circuit 17b outputs the data (YIA1, YIA5) sampled at the sampling point b.
,... YIA (4n + 1)) and data (YQA1, YQA5
,... YQA (4n + 1)), the inner and outer product operation circuit 17c outputs data (YIA2, YIA6,... YIA (4n + 2)) and data (YQA2, YQA6,. 4n + 2)), the inner / outer product operation circuit 17d outputs the data (YIA3, YIA7,...) Sampled at the sampling point d.
• YIA (4n + 3)) and data (YQA3, YQA7,
Based on YQA (4n + 3)), an inner product and an outer product between the in-phase component data YIA and the quadrature component data YQA, and an integrated value of the absolute value of the inner product and the absolute value of the outer product are calculated.

The structure of the inner / outer product operation circuit 17a will be specifically described. As shown in FIG. 3, the inner / outer product operation circuit 17a includes an inner product operation circuit 21, an outer product operation circuit 27, and a multiplier 33. The inner product operation circuit 21 includes two multipliers 22 and 23, two memories 24 and 25, and an adder 26. In the inner product operation circuit 21, when the in-phase component data YIA (for example, data YIA4) is input to the multiplier 22, the memory 24 stores one symbol period (four previous) with respect to the in-phase component data YIA.
The in-phase component data YIA (e.g., data YIA0) sampled as described above is output to the multiplier 22. Hereinafter, the data sampled four times before the in-phase component data YIA (or the quadrature component data YQA) is referred to as “in-phase component data YIA · Z ⁻¹ ” and “quadrature component data YQA · Z”.
^-1 ".

[0030] Specifically, the multiplier 22, in-phase component data YIA-phase component data YIA · Z ^{- 1} and integrating each other. On the other hand, when the orthogonal component data YQA (for example, data YQA4) is input to the multiplier 23, the memory 25 stores the orthogonal component data YQA · Z ⁻¹ (for example, four samples before the orthogonal component data YQA). The data YQA0) is output to the multiplier 23. Further, the multiplier 23 integrates the orthogonal component data YQA and the orthogonal component data YQA · Z− ¹ with each other. Further, the adder 26 adds the multiplied values obtained by the two multipliers 22 and 23 to each other, whereby
Inner product data DaIP (DaIP0, DaIP4,... DaIP
(4n),...) And outputs the inner product data DaIP to the numerical value judgment circuit 19. In this case, the inner product data DaIP
Is a vector rb based on the in-phase component data DI and the quadrature component data DQ sampled by the A / D converters 4 and 5, and a vector rb based on the in-phase component data DI and the quadrature component data DQ sampled four times before these. It corresponds equivalently to the inner product value with ra.

The outer product operation circuit 27 includes two multipliers 28 and 29, two memories 30 and 31, and a subtractor 3.
2 is provided. In the outer product operation circuit 27, the memory 30 stores the orthogonal component data YQA in the multiplier 29.
When data (for example, data YQA4) is input, in-phase component data YIA · Z ^-1 (for example, data YIA0) is multiplied by a multiplier 29.
Output to On the other hand, when the in-phase component data YIA (for example, data YIA4) is input to the multiplier 28, the memory 31 stores the quadrature component data YQA · Z ⁻¹ (for example, data YQA0).
) Is output to the multiplier 28. Therefore, the multiplier 28
Are in-phase component data YIA and quadrature component data YQA · Z ⁻¹
Are added to each other, and the multiplier 29 outputs the orthogonal component data YQA
And the in-phase component data YIA.Z- ¹ are integrated with each other. On the other hand, the subtracter 32 subtracts the multiplied value multiplied by the multiplier 29 from the multiplied value multiplied by the multiplier 28, thereby forming the outer product data DaOP (DaOP0, DaOP4).
,... DaOP (4n),...), And outputs the outer product data DaOP to the numerical value judging circuit 19. In this case, the outer product data DaOP is a vector rb based on the in-phase component data DI and the quadrature component data DQ sampled by the A / D converters 4 and 5, and the in-phase component data DI and quadrature sampled four times before these. It corresponds equivalently to the outer product value with the vector ra based on the component data DQ.

On the other hand, the multiplier 33 multiplies the absolute value DIP of the inner product data by the absolute value DOP of the outer product data to obtain the integrated data Da (DaO, Da4,... Da (4
n),...), and outputs the generated integrated data Da to the averaging circuit 18a. The inner and outer product operation circuit 17b
To 17d, similarly, the inner product data D
bIP (DbIP1, DbIP5,... DbIP (4n + 1),.
.), Inner product data DcIP (DcIP2, DcIP6,... D
cIP (4n + 2), ..) and inner product data DdIP (Dd
IP3, DdIP7,..., DdIP (4n + 3),. Similarly, each of the subtracters 32 of the inner and outer product operation circuits 17b to 17d outputs the outer product data DbOP (DbOP1, DbOP5,... DbOP (4n +
1), ..), cross product data DcOP (DcOP2, DcOP6
, ..DcOP (4n + 2), ..) and cross product data D
dOP (DdOP3, DdOP7,... DdOP (4n + 3),.
) Are output to the numerical value judgment circuit 19, respectively. further,
Similarly, the multipliers 33 of the inner and outer product operation circuits 17b to 17d similarly output the integrated data Db (Db1, Db5,... Db
(4n + 1), ..), integrated data Dc (Dc2, Dc6
, ..Dc (4n + 2), ..) and integrated data Dd
(Dd3, Dd7,... Dd (4n + 3),...) Are output to averaging circuits 18b to 18d, respectively.

The averaging circuits 18a to 18d are configured identically to each other.
To Dd, M consecutive integrated data Da to Dd
Is calculated, and the calculated integrated average value data DaA to
DdA is output to the numerical value judgment circuit 19. Numerical value judgment circuit 1
9 determines the minimum value among the integrated average value data DaA to DdA output from the averaging circuits 18a to 18d, and determines any one of the sampling points a to d having the minimum value as a symbol point. . The numerical value judging circuit 19 demodulates received data corresponding to each one symbol of the received signal based on the in-phase component data YIA and the quadrature component data YQA sampled at the determined symbol points.

Next, the overall operation of the QPSK demodulator 1 will be described.

First, the quadrature demodulator 2 performs quadrature demodulation by multiplying the input received signal by the local signals SLI and SLQ, thereby obtaining the in-phase component signal SI and the quadrature component signal SQ.
Generate Next, the A / D converters 4 and 5 respectively generate the in-phase component data DI and the quadrature component data DQ by sampling the in-phase component signal SI and the quadrature component signal SQ in synchronization with the sampling signal SS. Specifically, referring to FIG. 5, the received signal has a period (N
In −2), + 3π / 4 phase modulation (corresponding to + π / 2 phase modulation in QPSK modulation and a phase modulation for the value (0, 1)) is performed, and in the period (N−1), −π / phase modulation is performed.
Four-phase modulation (corresponding to -π / 2 phase modulation in QPSK modulation and a phase modulation for a value (1, 0))
The case where + π / 4 phase modulation (corresponding to 0 · π / 2 phase modulation in QPSK modulation and phase modulation with respect to a value (0, 0)) in the period N will be described as an example.

In this case, as shown in the figure, in the period (N-2), the A / D converters 4 and 5 output the times a (N-2), b () corresponding to the sampling points a to d. N-2),
Sampling is sequentially performed at c (N−2) and d (N−2). Further, in the period (N-1), times a (N-1) and b (N-N) corresponding to the sampling points a to d.
1), c (N-1) and d (N-1), the period N
At time a corresponding to sampling points ad
At the time of N, bN, cN and dN, sampling is performed, respectively. In-phase component data Y sampled at this time
When the IB and the orthogonal component data YQB are made to correspond to the vector on the polar coordinates, they are represented as shown in FIG. In the figure, the vector is represented by a natural logarithm with a natural number e as a base. In this specification, the natural logarithm is represented by e · jA, for example.
Notation. Therefore, for example, a received signal sampled at the sampling point a of the period (N−2) is expressed as ej (0). In the lower part of the column showing the natural logarithm in the figure, the in-phase component data YIB and the quadrature component data YIB before the primary conversion corresponding to the vector are shown.
Indicates QB.

Next, the primary conversion circuit 16 of the demodulation processing circuit 8
Performs primary conversion on the in-phase component data DI and the quadrature component data DQ for detection. In this case, the primary transformation is
Vectors r · n corresponding to the sampled in-phase component data YIB and quadrature component data YQB, and vectors corresponding to the in-phase component data YIB · Z ⁻¹ and quadrature component data YQB · Z ⁻¹ sampled four times before. r
This is performed by multiplying the complex conjugate vector of (n-4). That is, in this linear transformation, the vector r · (n
-4) is plotted on the I-axis of the polar coordinate with the initial rotation angle of 0 ° being plotted, and the rotation angle of the vector r · n (the advance or delay of the phase) with respect to the rotation angle (0 °) of the vector r · (n−4) (Degree). Accordingly, in the following processing, the π / 4 shift QPSK modulated wave signal and the QPSK modulated wave signal can be processed in the same manner.

More specifically, if the vector before the primary conversion and the vector after the primary conversion are denoted by “rB” and “rA”, respectively, the received signal in the period (N−2) is the vector rB · a (N -2), rB · b (N-2), rB ·
c (N−2), rB · d (N−2), and these complex conjugate vectors are vectors r ⁻¹ · a (N−2), r
⁻¹ · b (N−2), r ⁻¹ · c (N−2), r ⁻¹ ·
d (N−2). “R ⁻¹ ” means a complex conjugate vector. The received signal in the period (N-1) is represented by vectors rB.a (N-1) and rB.b (N-
1), rB * c (N-1), rB * d (N-1).

Next, for each vector of the period (N-1), a primary conversion is performed based on the complex conjugate vector of each vector in the period (N-2), and the vector after the primary conversion is the vector rA · a (N− 1), rA · b (N−
1), rA * c (N-1), rA * d (N-1). The vector rA · a (N−
1), rA.b (N-1), rA.c (N-1), rA
D (N−1) is e · j as shown in FIG.
(12π / 16), ej (8π / 16), ej (4
π / 16), e · j (0). In the lower part of the column showing the natural logarithm in the figure, the in-phase component data YIA and the quadrature component data YQA after the primary conversion corresponding to the vector are shown.

Next, similarly, the primary conversion is performed for each vector of the period N. In this case, the received signal in the period (N-1) is the vector rB .a (N-1), rB.
b (N-1), rB * c (N-1), rB * d (N-
1), and these complex conjugate vectors are represented by a vector r
⁻¹ · a (N−1), r ⁻¹ · b (N−1), r ⁻¹ ·
c (N−1), r ⁻¹ · d (N−1). Further, the received signal in the period N is represented by a vector rB · aN, rB ·
bN, rB.cN, rB.dN. Then, the cycle N
Of each vector in the period (N-1) based on the complex conjugate vector of each vector, the vector after the primary conversion is the vector rA.aN, rA.b
N, rA.cN, rA.dN. The vectors after these primary conversions are represented as shown in FIG. The vectors rA-aN, rA-bN, rA-
As shown in FIG. 7, cN, rA · dN are e ·
j (-4π / 16), ej (-2π / 16), ej
(0), e · j (2π / 16). In the lower part of the column showing the natural logarithm in the figure, the in-phase component data YIA and the quadrature component data YQA after the primary conversion corresponding to the vector are shown.

Thereafter, the inner and outer product operation circuits 17a to 17d
Calculates the inner product, the outer product, and the absolute value of the inner product and the integrated value of the absolute value of the outer product based on the in-phase component data YIA and the quadrature component data YQA after the primary conversion. In this calculation process, for example, the inner / outer product calculation circuit 17a calculates the period (N-1)
The vector rA · a (N) based on the in-phase component data YIA0 and the quadrature component data YQA0 sampled at
-1) and the inner product data DaIP, the outer product data DaOP, and the integrated data Da between the vector rA.aN based on the in-phase component data YIA4 and the quadrature component data YQA4 sampled in the cycle N are calculated. In this case, for the inner product data DaIP, the multiplier 22 calculates a multiplied value of the in-phase component data YIA4 and the in-phase component data YIA0, for example, and the multiplier 23 calculates the multiplied value of the quadrature component data YQA4 and the quadrature component data YQA0, for example. Calculate. Next, the adder 26 calculates the inner product data DaIP4 by adding these calculated values.

For the outer product data DaOP, the multiplier 28 calculates a multiplication value of the in-phase component data YIA4 and the quadrature component data YQA0, for example, and the multiplier 29 calculates the multiplication value of the quadrature component data YQA4 and the in-phase component data YIA0, for example. Calculate the value. Next, the subtracter 32 computes the outer product data DaOP by subtracting the computed value of the subtractor 32 from the computed value of the multiplier 28. Further, the inner and outer product operation circuit 1
The same processing is performed in 7b to 17d. Since the inner product operation and the outer product operation are equivalent to an operation using a vector, a detailed description will be given below using a vector operation.

The inner / outer product operation circuit 17a first calculates the rotation angle difference (phase difference) between the vector rA.a (N-1) and the vector rA.aN. In this example, the phase difference is π, as shown in FIG. Therefore, the inner product data Da
According to the characteristic diagram of the inner product value with respect to the phase difference shown in FIG. 8A, IP4 is a value (-1), and the outer product data DaOP4
Is 0 according to the characteristic diagram of the cross product value with respect to the phase difference shown in FIG. Therefore, the integrated data Da4
Has the value 0. Similarly, in the inner / outer product operation circuit 17b, the vector rA · b (N−1) and the vector rA ·
Calculate the phase difference of bN. In this example, the phase difference is 10π / 16 as shown in FIG. Therefore, the inner product data DbIP4 becomes a value (−0.38), and the outer product data DbIP4 becomes
bOP4 becomes the value (0.92) and the integrated data Db4
Is the value (0.35). Similarly, the inner / outer product operation circuit 17c calculates the phase difference between the vector rA.c (N-1) and the vector rA.cN. In this example, FIG.
As shown in FIG. Therefore, the inner product data DcIP4, outer product data DcOP4, and integrated data Dc4 have values (0.71), (0.71),
(0.5). Similarly, the inner / outer product operation circuit 17d
Then, the vector r A · d (N-1) and the vector r A
Calculate the phase difference of dN. In this example, the phase difference is π / 8, as shown in FIG. Therefore, the inner product data D
dIP4, cross product data DdOP4 and integrated data Dd4
Are the values (0.92), (0.38), (0.3
5).

The inner product data D obtained by the above operation
aIP (DaIP0, DaIP4,... DaIP (4n),.
.), DbIP (DbIP1, DbIP5,... DbIP (4n
+1), ..), DcIP (DcIP2, DcIP6,... D
cIP (4n + 2), ..), DdIP (DdIP3, DdIP7
,... DdIP (4n + 3),...), And cross product data DaOP (DaOP0, DaOP4,..., DaOP (4n),.
.), DbOP (DbOP1, DbOP5,... DbOP (4n
+1), ..), DcOP (DcOP2, DcOP6,... D
cOP (4n + 2), ..), DdOP (DdOP3, DdOP7)
,... DdOP (4n + 3),.
9, the integrated data Da (Da0, Da4,...)
Da (4n), ..), Db (Db1, Db5,... D
b (4n + 1),...), Dc (Dc2, Dc6,.
c (4n + 2), ..), Dd (Dd3, Dd7,... D
d (4n + 3),...) are output to averaging circuits 18a to 18d, respectively.

On the other hand, the averaging circuits 18a to 18d output the M consecutive integrated data Da,
b, the average value of the integrated data Dc and the average value of the integrated data Dd are calculated, and the calculated integrated average value data DaA to DdA are sequentially output to the numerical value judging circuit 19. As a result, the numerical value judging circuit 19 outputs the integrated average value data DaA to Dd which are the average values.
By detecting a symbol point based on A, it is possible to prevent erroneous detection due to superimposition of noise on a received signal. The numerical value judging circuit 19 judges the minimum value of the inputted integrated average value data DaA to DdA. In this example, since the average value of the vector rA · aN sampled at the sampling point a is the minimum, in this case, the numerical value judging circuit 19 determines that the preceding sampling point a is a symbol point.

Thereafter, unless the minimum value of the average value changes to another sampling point, the numerical value judging circuit 19 continues to treat the sampling points a, a,... As symbol points as shown in FIG. When the minimum value of the average value changes to, for example, the sampling point c, the sampling point c is handled as a symbol point. Next, the numerical value judgment circuit 19
Determines whether the vector rA.N based on the in-phase component data YIA and the quadrature component data YQA sampled at the determined symbol point a belongs to any of the first to fourth quadrants. In this case, as shown in FIG. 9, the first to fourth quadrants are respectively 0 to π / 2,
/ 2 to π, π to 3π / 2 (that is, -π / 2 to
-Π), and 3π / 2 to 2π (that is, 0 to -π / 2)
And corresponds to the phase modulation of the value (0, 0), the value (0, 1), the value (1, 1), and the value (1, 0).

In this case, the numerical value judgment circuit 19
The vector rA · a (N-1) based on the in-phase component data YIA4 and the quadrature component data YQA4 is e as shown in FIG.
Since it is j (12π / 16), it is determined that it belongs to the second quadrant. As a result, the numerical value judgment circuit 19 determines that the modulation data of the received signal in the period (N-2) is the value (0,
Numerical determination is made that 1). Also, the vector rA · aN
Is ej (-4π / 16) as shown in the figure, so that it is determined that it belongs to the fourth quadrant. As a result, the numerical value judgment circuit 19 numerically judges that the modulation data of the received signal in the cycle (N-1) is the value (1, 0).

Next, the numerical value judging circuit 19 executes an AFC process. In this process, the numerical value judgment circuit 19 first judges whether the value of the inner product data DaIP4 and the value of the outer product data DaOP4 for the vector rA · aN for which the numerical value has been judged is positive or negative. In this case, the synchronization shift between the in-phase component signal SI and the quadrature component signal SQ and the sampling signal SS is equivalent to the phase θ (θ is − π / 4 to + π / 4). In this case, the numerical value determining circuit 19 determines which of the first to fourth quadrants shown in FIG. 11 the vector based on the determined numerical value exists. Next, when the vector is rA1 shown in FIG. 12, “0 × π /
2), it is determined whether the values of the inner product data DaIP and the outer product data DaOP at that time are positive or negative. In this case, for example, when the rotation angle of the vector rA1 is in the range of 0 to π / 2, as shown in FIGS. 8A and 8B, the inner product value is positive and the outer product value is positive. At this time, the numerical value judgment circuit 1
9, the phase of the received data is "0x" as shown in FIG.
π / 2 ”, and both the inner product value and the outer product value correspond to the“ + ”column, so that it is determined that the reception frequency is high.

When it is determined that the reception frequency is high, the numerical value judgment circuit 19 sends the AFC data D to the primary conversion circuit 16.
By outputting the AFC, the primary conversion amount by the primary conversion circuit 16 is corrected. Specifically, at the time of the primary conversion, for example, the rotation angle of the complex conjugate vector obtained by multiplying the vector rB · aN is slightly increased to the negative side. Thus, the phase shift between the vector rB.aN and the sampling signal SS is corrected. Note that the numerical value determination circuit 19 continuously performs this processing, and when a result opposite to the result determined earlier (that is, in this example, it is determined that the reception frequency is low), the AFC processing is performed. Stop.

On the other hand, when the rotation angle of the vector rA4 is 0 to -π
In the range of / 2, the inner product value is positive and the outer product value is negative, as shown in FIGS. 8 (a) and 8 (b). At this time,
As shown in FIG. 12, the numerical value determination circuit 19 determines that the phase of the received data is “0 × π / 2”, the inner product value is “+”, and the outer product value is “−”. It is determined that the frequency is low. At this time, the numerical value determination circuit 19 slightly increases the rotation angle of the complex conjugate vector to the positive side, and when the result is opposite to the result determined earlier (that is, in this example, the reception frequency is higher). ), The AFC process is stopped. Thus, the phase shift between the vector rB.aN and the sampling signal SS is corrected. Similarly,
As shown in FIG. 12, the phase of the received data is “1 × π /
2 ”,“ 2 × π / 2 ”, or“ 3 × π / 2 ”, the reception frequency is determined according to the sign of the inner product value and the outer product value, as shown in the right column of that column. Is determined, and AFC processing is executed according to the determination result.

As a result, without changing the frequency of the reference signal SREF in the reference oscillation circuit 7, the in-phase component signal SREF
I and the quadrature component signal SQ can be reliably synchronized with the sampling signal SS. Therefore, in the conventional demodulator 51, the accuracy of the reference signal SREF had to be about 1/8 to 1/16 of the symbol rate, whereas in the QPSK demodulator 1, the precision was within 1/4 of the symbol rate. If so, the in-phase component signal SI and the quadrature component signal SQ and the sampling signal SS can be surely phase-synchronized, whereby the modulated data can be reliably demodulated. When the phase shift exceeds ± π / 4, the numerical value judging circuit 19 sends the AF signal to the reference oscillation circuit 7.
By outputting the C control signal SAFC, the reference signal SREF in the reference oscillation circuit 7 is corrected.

The present invention is not limited to the configuration shown in the embodiment of the present invention, but can be appropriately changed. For example, in this embodiment, the numerical value determination circuit 19 detects the symbol point based on the integrated data Da to Dd which is the integrated value of the inner product value and the outer product value, but the absolute value of the inner product value and the outer product value are detected. Can be detected based on the absolute value of the difference from the absolute value of. In this case, a sampling point having a larger absolute value of the difference is detected as a symbol point.

In this embodiment, the received signal is set to 9
Although the case of the 00 MHz band has been described, the present invention is not limited to the reception frequency. Also, an example of demodulating a π / 4-shifted QPSK modulated wave signal has been described, but the present invention is not limited to this.
Demodulation can be performed by the configuration of the demodulation device 1.

Further, in the present embodiment, the hardware configuration has been described for easy understanding. However, all other configurations except the quadrature demodulator 2, the local oscillation circuit 3, and the reference oscillation circuit 7, or An arbitrary part in another configuration may be configured by a DSP (Digital Signal Processor), and its function may be executed by software.
In the present embodiment, the inner product value, the outer product value, and the like are calculated by digital calculation. However, the calculation can be performed in an analog manner without A / D conversion. Further, in the embodiment of the present invention, an example in which the inner product value and the outer product value are obtained by performing a vector operation for easy understanding has been described. However, the present invention is not limited thereto, and the in-phase component data YIA and the quadrature component data YQA are used. It is needless to say that the inner product value and the outer product value can be obtained by numerical operation based on in addition,
The configuration of the primary conversion circuit and the conversion method can also be appropriately changed.

[0055]

As described above, the QP according to the first to fourth aspects is described.
According to the SK demodulator, data can be demodulated without using a feedback loop such as a PLL.
The phase synchronization can be established at high speed, and the synchronization can be stably maintained and followed. Also, QPS
Even if the K-modulated wave signal has a phase shift of up to 1/4 of the symbol rate, it is possible to theoretically reliably demodulate data without performing AFC processing.

Further, according to these QPSK demodulators, it is possible to demodulate a π / 4 shift QPSK modulated wave signal or a QPSK modulated wave signal with the same configuration, and thus demodulate various QPSK modulated wave signals having different systems. In this case, it is not necessary to change the configuration, whereby the design cost can be reduced. Further, a conventional demodulator which only needs to determine the frequency of the sampling rate, that is, the value of N, in accordance with the symbol rate of the QPSK modulated wave signal and needs to optimize each circuit in accordance with the modulation scheme and symbol rate. Unlike 51, the design for matching the symbol rate can be completed very easily and in a short time.

According to these QPSK demodulators, a symbol point can be detected and a symbol point can be established based on original data, so that it is not necessary to include a symbol synchronization signal in a transmission signal. . As a result, the transmission speed for the original data can be increased accordingly.

Further, according to the QPSK demodulation device of the present invention, the data demodulation unit detects a symbol point based on the average value of the continuous M integrated values or absolute values, so that the QPSK modulated wave signal can be obtained. Even when noise is superimposed, symbol points can be detected without error, and thus the reliability of demodulated data can be improved.

Further, according to the QPSK demodulation apparatus of the sixth aspect, the primary conversion circuit comprises a vector based on the in-phase component data and the quadrature component data before detection, and the in-phase component data and the quadrature component sampled N times before. By multiplying the complex conjugate vector of the vector based on the data with the complex conjugate vector for detection, it is possible to easily detect the in-phase component data and the quadrature component data before detection.

Further, according to the QPSK demodulation device according to the seventh aspect, the primary conversion circuit performs detection while correcting the primary conversion amount based on the inner product value and the outer product value.
Even when the K-modulated wave signal or the local oscillation signal has a certain frequency shift, the data can be demodulated without performing the AFC process. This allows
Since a high-precision performance is not required for the reference oscillator for generating the local oscillation signal, an inexpensive reference oscillator can be used, so that the manufacturing cost of the device can be reduced.

According to the QPSK demodulating device of the eighth aspect, by correcting the frequency of the local oscillation signal based on the inner product value and the outer product value, it is not necessary to use the control voltage of the PLL circuit at that time. Therefore, even when a large frequency shift occurs in the QPSK modulated wave signal or the local oscillation signal, the AFC processing can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a QPSK demodulator according to an embodiment of the present invention.

FIG. 2 is a block diagram of a demodulation processing circuit 8;

FIG. 3 is a block diagram of an inner / outer product operation circuit 17a.

4A is an explanatory diagram for explaining sampling points of in-phase component data DI, and FIG. 4B is a diagram illustrating quadrature component data DQ.
FIG. 4 is an explanatory diagram for explaining sampling points of FIG.

FIG. 5 is a polar coordinate diagram for explaining sampling points in periods (N-2), (N-1), and N.

FIG. 6 is an explanatory diagram showing values of vectors sampled at sampling points a to d of periods (N-2), (N-1), and N before primary conversion.

FIG. 7 is an explanatory diagram showing values after primary conversion of vectors sampled at each sampling point of a period (N-1) and N, an inner product value, an outer product value, and an integrated value based on these vectors.

FIG. 8A is a phase difference-inner product value characteristic diagram showing a sampled vector and an inner product value with respect to a phase difference of a vector sampled one cycle before the sampled vector, and FIG. Phase difference indicating a cross product value with respect to the phase difference of the vector sampled one cycle before-
It is an outer product value characteristic diagram.

FIG. 9 is a polar coordinate diagram showing a range of each of a first quadrant to a fourth quadrant which is a criterion for a numerical value judgment by the numerical value judgment circuit 19.

FIG. 10 is an explanatory diagram showing detected symbol points.

FIG. 11 is a first to fourth quadrants for explaining AFC processing;
FIG. 4 is a polar coordinate diagram showing a relationship between a quadrant and a sampled vector.

FIG. 12 is an explanatory diagram for describing the contents of an AFC process.

FIG. 13 is a block diagram of a conventional demodulation device 51.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 QPSK demodulator 2 Quadrature demodulator 3 Local oscillation circuit 4 A / D converter 5 A / D converter 8 Demodulation processing circuit 16 Primary conversion circuit 17a-17d Inner / outer product operation circuit 18a-18d Averaging circuit 19 Numerical value judgment circuit

Claims (8)

[Claims] 1. Two local oscillation signals orthogonal to each other and Q
A QPSK demodulator that mixes the PSK modulated wave signal to generate an in-phase component signal and a quadrature component signal, respectively, and demodulates modulation data from the QPSK modulated wave signal based on the two component signals; Sampling means for sampling the quadrature component signals at a sampling rate N (N is an integer) times the symbol rate to generate N in-phase component data and N quadrature component data; By detecting N pieces of quadrature component data, N pieces of in-phase component data DI0 to DI are obtained.
(N−1) and N orthogonal component data DQ0 to DQ (n−
1) and a vector based on the in-phase component data DI0 to DI (n-1) and the quadrature component data DQ0 to DQ (n-1) sampled for one cycle of the symbol rate. , And the in-phase component data DI0 to DI (n−1) sampled N times before each of the vectors.
And an inner / outer product operation unit for equivalently calculating an inner product value and an outer product value between vectors based on the orthogonal component data DQ0 to DQ (n−1); and the inner product value calculated by the inner / outer product operation unit And detecting a symbol point based on the outer product value and detecting the in-phase component data DI0 corresponding to the symbol point.
To DI (n-1) and the orthogonal component data DQ0 to DQ (n
-1) a data demodulation unit for demodulating the modulated data based on the following equation: 2. The QPSK demodulator according to claim 1, wherein the data demodulation unit detects the symbol point based on an integrated value of the calculated inner product value and the outer product value. 3. The data demodulation unit detects the symbol point based on an integrated value of the calculated absolute value of the inner product value and the absolute value of the outer product value.
The QPSK demodulator according to claim 1. 4. The data demodulation section detects the symbol point based on an absolute value of a difference between the calculated absolute value of the inner product value and the absolute value of the outer product value. The QPSK demodulator according to claim 1. 5. The data demodulation section detects the symbol point based on an average value of M consecutive values (M is an integer) of the integrated values or the absolute values. The QPSK demodulator according to any one of the above. 6. The primary conversion circuit, equivalently, comprises a vector based on the in-phase component data before detection and the quadrature component data generated corresponding thereto, and the in-phase component sampled N times earlier. The QPSK demodulator according to any one of claims 1 to 5, wherein detection is performed by multiplying data and a complex conjugate vector of a vector based on the orthogonal component data corresponding to the data. 7. The Q according to claim 1, wherein the primary conversion circuit performs detection while correcting a primary conversion amount based on the inner product value and the outer product value.
PSK demodulator. 8. The QPSK demodulator according to claim 1, wherein the frequency of the local oscillation signal is corrected based on the inner product value and the outer product value.