JP2000031491A - Semiconductor device, its manufacture, semiconductor substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform acceleration or the like by setting a strain application layer made of a mixed crystal semiconductor layer to the thickness of a specific range, and reducing the thickness of an Si layer between SiGe strain application layer and an SiO2 insulating layer at most to the thickness of the SiGe strain application layer, thereby setting the thickness of the strain channel layer to the critical thickness of Si of a specific value or less on the SiGe. SOLUTION: In the semiconductor device 100, an SiGe strain application layer 102 made of an SiGe (0<=x<=1) and a strain Si channel layer 104 are sequentially laminated and grown on an upper surface of an Si substrate 101, and a structure having an SiO2 insulating layer 103 therein is formed at a surface layer of the substrate 101. The layer 102 of the device 10 is formed in a thickness of about 50 to 200 nm, and the thickness of the Si layer between the layer 102 and the layer 103 is set to the thickness of less of the SiGe strain application layer. Further, the thickness of the layer 104 is set to a power of about (3-2x) times of 10 as a critical thickness nm in which Si is strain grown on the SiGe.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, a semiconductor substrate, and a method of manufacturing a semiconductor substrate, and more particularly to a technology effective when applied to a manufacturing technology of a semiconductor device including a SiGe heterostructure transistor.

[0002]

2. Description of the Related Art With the increase in the density of integrated circuits, there is an urgent need to reduce the size and speed of Si field-effect transistors. On the other hand, development of a high-speed, low-power transistor for communication is strongly desired.

It has been suggested that a strained Si (heterostructure) transistor in which strain is applied to a Si channel can be much faster than a conventional Si field-effect transistor (M.
V. Fischetti and SELaux: J. Appl. Phys. 80 (1996) 223
Four).

In a heterostructure transistor formed on a Si substrate, a buffer layer (strain applying layer) having a different lattice constant from the channel layer must be provided below the channel layer in order to apply a strain to the channel layer. Conventionally, Si _1-x Ge _x mixed crystal (0 ≦
x ≦ 1) was used as the buffer layer, but it was necessary to stack a buffer layer having a thickness of 1 μm or more, and due to the problem of dislocations penetrating to the upper part of the buffer layer and the deterioration of the surface roughness, the transport of the channel layer was The characteristics are adversely affected, and it is difficult to realize a high mobility transistor having desired electron transport characteristics.

Further, regarding transistors using Si and Ge (field effect transistors), Extended Abstract of 1993 International Conference on Solid State Devices and Materials, McHari, 1993, pp. 201-203 (Extended Abstravts) of the 1993 Intern
ational Conference on Solid State Devices and Mate
rials, Makuhari (1993) pp. 201-203).

[0006] The field effect transistor (high mobility transistor) described in this document is composed of SiGe on a Si substrate.
It has a buffer layer, and has a structure having a Si channel layer and a SiGe layer on the SiGe buffer layer. In addition, the SiGe
In the middle of the layer, a delta-doped layer (electron supply layer) composed of a single atomic layer doped with Sb is provided.

On the other hand, use of an SOI substrate having a silicon layer provided on an insulating plate has been studied in consideration of high-speed operation.
Several methods, such as a bonded substrate, have been proposed for SOI substrates, but the SIMOX method, in which oxygen ions are implanted into a Si substrate and then annealed to form an oxide layer, holds promise. The use of a SIMOX substrate offers significant advantages in the fabrication of strained Si transistors as well as conventional Si field effect transistors.

That is, when a SiGe strain applying layer is formed on a SIMOX substrate, a large number of dislocations are generated in SiO ₂ in the substrate and the Si layer thereon, so that the dislocation density of the SiGe layer can be reduced. However, in order to reduce dislocation density,
The thickness of the SiGe layer needs to be at least 500 nm or more, which is not desirable because of the flatness of the film surface and productivity.

As described above, in the prior art, it was difficult to form a high-quality strain applying layer necessary for realizing a high-speed SiGe heterostructure high mobility transistor (HEMT). For examples of forming field-effect transistors and high-mobility transistors using a SIMOX substrate, see DKNayak, JSPark, J.
CSWoo, KLWang, GKYabiku, and KPMacWilliams In
It is described in the ternational Electron Devices Meeting (IEDM).

[0010]

In the above-mentioned prior art, there are problems such as threading dislocations in the buffer layer, deterioration in surface properties, and deterioration in productivity of the buffer layer.
This has hindered the realization of heterostructure high mobility transistors.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a heterostructure transistor capable of achieving high speed, high performance, and high integration by realizing a heterostructure having good crystallinity, and a semiconductor device excellent in productivity. It is to provide a manufacturing method.

Another object of the present invention is to provide a Si substrate (semiconductor substrate) having a heterostructure with good crystallinity. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of typical inventions disclosed in the present application. (1) An SiO ₂ insulating layer formed on the Si substrate and formed inside the main surface of the Si substrate, a strain applying layer made of a mixed crystal semiconductor layer provided on the main surface of the Si substrate, and A strain channel layer made of a Si layer provided on the application layer, a pair of diffusion regions forming a source region or a drain region provided in the strain channel layer, and gate insulation on the strain channel layer between the pair of diffusion regions. A semiconductor device having a field-effect transistor constituted by a gate electrode provided through a film, wherein the strain applying layer is made of Si _1-x G
e _x (0 ≦ x ≦ 1), the strain applying layer has a thickness of about 50 to 200 nm, and a Si layer between the Si _1-x Ge _x strain applying layer and the SiO ₂ insulating layer. The thickness is equal to or less than the Si _1-x Ge _x strain applying layer, and the thickness of the strain channel layer is a critical thickness at which Si grows on Si _1-x Ge _{x in a} strain growth, 10 ( 3-2x).

Such a field effect transistor is manufactured by the following manufacturing method. Si formed between a source region and a drain region provided on the Si substrate and formed on the Si substrate.
For manufacturing a semiconductor device having a field effect transistor having a strained channel layer composed of layers and a gate electrode provided on a strained channel layer between the source region and the drain region via a gate insulating film And said
Forming a strain applying layer made of a mixed crystal semiconductor layer on the main surface of the Si substrate, and implanting oxygen ions from the surface of the strain applying layer and annealing to form a SiO ₂ insulating layer in the Si substrate Forming the strain channel layer on the strain applying layer; forming an element isolation insulating region on the main surface side of the Si substrate to form an element formation region; and forming the element formation region in the element formation region. Forming a gate electrode and a diffusion region forming a source region and a drain region. The conditions for the oxygen ion implantation and annealing are selected so that the surface layer of the Si substrate remains between the strain applying layer and the SiO ₂ insulating layer. The strain applying layer is formed to have a thickness of 50 to 200 nm, and the thickness of the strain channel layer is formed to be about 10 (3−2 ×) nm or less.

(2) In the configuration of the means (1), the upper surface of the SiO ₂ insulating layer is in contact with the lower surface of the strain applying layer. That is, a strain applying layer formed on a Si substrate and formed of a mixed crystal semiconductor layer (Si _1-x Ge _x layer (0 ≦ x ≦ 1)) having a thickness of 50 to 200 nm provided on the main surface of the Si substrate. A SiO ₂ insulating layer provided in the Si substrate so that an upper surface is in contact with a lower surface of the strain applying layer and extends along the strain applying layer, and a thickness provided on the strain applying layer is 10 (3-2x)
A strained channel layer made of a Si layer having a power of about nm or less, a pair of diffusion regions provided in the strained channel layer to form a source region or a drain region, and a gate insulating film on the strained channel layer between the paired diffusion regions. And a gate electrode provided through the gate electrode.

In such a field effect transistor, in the manufacturing method according to the means (1), the conditions for the oxygen ion implantation and annealing are selected, and the SiO ₂ insulating layer is formed on the lower surface of the strain applying layer. It is formed so that the upper surfaces match.

(3) In the configuration of the means (1) or (2), a spacer layer, a carrier supply layer doped with a conductivity type determining impurity, and a cap layer are sequentially formed on the strain channel layer to form modulation doping. Field-effect transistor.

[0018] In the modulation doping type field effect transistor according to the above (1) or (2), the spacer layer and the delta carrier doped with a conductivity type determining impurity are formed on the strained channel layer. Supply layer,
A cap layer is sequentially formed to form a modulation-doped field effect transistor.

(4) An Si substrate, a mixed crystal semiconductor layer grown and formed on the main surface of the Si substrate, and a SiO ₂ insulating film formed by annealing oxygen ions implanted from the surface of the mixed crystal semiconductor layer. A semiconductor substrate comprising a layer. Between the SiO ₂ insulating layer and the mixed crystal semiconductor layer, there is an Si layer constituting a Si substrate having a thickness equal to or less than the thickness of the mixed crystal semiconductor layer. The mixed crystal semiconductor layer is composed of a Si _1-x Ge _x layer (0 ≦ x ≦ 1), and its thickness is
It is 50-200 nm.

In such a semiconductor substrate, a step of growing and forming a mixed crystal semiconductor layer on the main surface of the Si substrate and a step of forming an oxygen distribution peak from the surface of the mixed crystal semiconductor layer into the Si substrate are performed. It is manufactured by a step of implanting ions and a step of annealing the Si substrate to form the SiO ₂ insulating layer.

(5) In the configuration of the means (1), the upper surface of the SiO ₂ insulating layer is coincident with the lower surface of the mixed crystal semiconductor layer.

According to the means (1), (a) the structure of the field-effect transistor is the same as that of the field-effect transistor manufactured using the SIMOX substrate.
The thickness of the strain applying layer can be reduced to about 200 nm or less, which is half or less of that of the SIMOX substrate of about 500 nm or more, and as a result, the thickness of the SiGe strain applying layer is about 10 to the power of (3-2x) nm. The following thin strained Si channel layer can be formed.

(B) By the above (a), the SiGe strain applying layer can be flattened, and the thickness of the strained Si channel layer is reduced to 10 (3-2x).
Since the thickness can be made as thin as about the power of nm, the punch-through current of the field effect transistor can be reduced, and the mobility can be prevented from lowering due to the occurrence of transition into the channel layer. Improvement) can be achieved.

(C) According to the above (b), the SiGe strain applying layer can be flattened, the strained Si channel layer can be thinned and fine processing can be performed, and high integration can be achieved.

(D) According to the above (a), the time for forming the SiGe strain applying layer and the strained Si channel layer can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

(E) The thickness of the Si layer between the SiGe strain applying layer and the SiO ₂ insulating layer is less than the thickness of the SiGe strain applying layer, and an effective formation of the SiGe strain applying layer is achieved. it can.

According to the means (2), in addition to the effect of the means (1), the lower surface of the strain applying layer has the Si
Since the SiO ₂ insulating layer is formed such that the upper surface of the O ₂ insulating layer is in contact with the O ₂ insulating layer, the stray capacitance can be reduced and the characteristics of the field effect transistor can be improved.

According to the means (3), it is possible to manufacture a semiconductor device having a modulation-doped field effect transistor having the effect of the structure of the means (1) or (2).

According to the means (4), the silicon-on-insulator (SO) whose surface is a mixed crystal semiconductor layer
I) A new semiconductor substrate having excellent structure flatness can be provided. This semiconductor substrate has a mixed crystal semiconductor layer (SiGe layer) on a Si substrate, and SiO ₂ formed by injecting oxygen ions and annealing inside the surface layer of the Si substrate.
Since the structure has an insulating layer, the thickness of the mixed crystal semiconductor layer can be reduced in the manufacture thereof, and the mixed crystal semiconductor layer also has a difference in lattice constant from Si (the lattice constant of Si is 5.4309 °, Ge
Has a lattice constant of 5.6575 °), and can be a layer acting as a strain applying layer. Therefore, fine processing can be performed by using the semiconductor substrate, and high integration of the semiconductor device can be realized. In addition, since the semiconductor substrate has a mixed crystal semiconductor layer having good flatness and a strain application layer,
When a strain channel layer is formed in the mixed crystal semiconductor layer, a high-speed, high-performance field-effect transistor or a modulation-doped field-effect transistor can be manufactured by forming a spacer layer, a carrier supply layer, and the like. Can be achieved.

According to the means (5), the semiconductor substrate has the effect of the semiconductor substrate according to the structure of the means (4), and the upper surface of the SiO ₂ insulating layer coincides with the lower surface of the mixed crystal semiconductor layer. With this configuration, a reduction in stray capacitance can be achieved.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIGS. 1 to 5 relate to a semiconductor device according to an embodiment (Embodiment 1) of the present invention. FIG. 1 is a schematic sectional view of the semiconductor device, and FIGS. 5
FIG. 3 is a schematic cross-sectional view of each step in the manufacture of a semiconductor device.

In the first embodiment, a semiconductor device having a field effect transistor will be described. 1 to 5
FIG. 3 is a diagram showing only a field-effect transistor portion.

As shown in FIG. 1, the semiconductor device 100 of the first embodiment has an Si _1-x Ge _x (0
≦ x ≦ 1), and has a structure in which a SiGe strain applying layer 102 and a strained Si channel layer 104 are sequentially grown. Also, S
i In the surface portion of the substrate 101, an SiO ₂ insulating layer 103
It has a structure having.

An element isolation insulating region 105 that penetrates through the strained Si channel layer 104, the SiGe strain applying layer 102, and the Si layer on the SiO ₂ insulating layer 103 and has a bottom reaching the SiO ₂ insulating layer 103 is formed. Is formed. A pair of diffusion regions 108 constituting a source region and a drain region of a field effect transistor are provided in an element formation region 121 surrounded by the element isolation insulating region 105.

The strain Si between the pair of diffusion regions 108
On the surface of the channel layer 104, a gate oxide film 106 is provided. A gate electrode 107 is provided on the gate oxide film 106, and side walls (sidewalls) 122 made of an insulator are provided on both ends of the gate oxide film 106 and the gate electrode 107. The diffusion regions 108 are provided at both ends of the gate oxide film 106, respectively.

The strained Si channel layer 104 and the gate electrode 107
On the side wall 122, an interlayer insulating film 109 is provided.
A contact hole is provided in the interlayer insulating film 109, and a metal wiring is formed in the contact hole.
111 is formed, and a gate wiring connected to the gate electrode 107 and a wiring for source and drain connected to the diffusion region 108 are formed, thereby forming a field effect transistor.

Next, with reference to FIGS. 2 to 5, a method of manufacturing the semiconductor device of the first embodiment and the composition and dimensions of each component will be described.

First, as shown in FIG. 2, an Si substrate 101 having a thickness of several hundred μm is prepared. After that, the Si substrate 101 is cleaned to obtain a clean Si substrate 101.

Next, immediately after cleaning, a chemical vapor deposition apparatus is used.
(CVD apparatus), and as shown in FIG.
Si _1-x Ge _x mixed crystal layer (0 ≦ x ≦ 1) on one flat surface (principal surface) of
A SiGe strain applying layer (SiGe buffer layer) 102 made of is formed. In the first embodiment, the mixed crystal ratio x is 0.3. Therefore, the SiGe strain applying layer 102 becomes the Si _0.7 Ge _0.3 strain applying layer 102. In CVD, for example, SiH4 and
It is grown at a growth temperature of 500 ° C. using GeH4 to a thickness of 150 nm.

The method of forming the Si _0.7 Ge _0.3 strain application layer 102 (mixed crystal ratio x) is not limited to the chemical vapor deposition method, but may be any method capable of forming a high-purity SiGe layer. The thickness of the SiGe layer is desirably about 50 to 200 nm in consideration of element isolation performance and reduction of stray capacitance. In addition, the composition ratio of Si and Ge is basically arbitrary because the SiGe alloy is a solid solution system, but it is suitable for giving appropriate strain to the Si channel layer and maintaining flatness of the Si channel layer. As an important value, Ge ratio (mixed crystal ratio x) is 10%
From about 40% is desirable. It is also effective to change the Ge composition (gradient composition) in the film thickness direction.

Next, oxygen ions are implanted from above the SiGe strain applying layer 102 under the conditions of an acceleration voltage of 200 KeV and a dose of 4 × 10 ¹⁷ / cm ² , and thereafter annealing is performed at 1300 ° C. for 8 hours. As a result, as shown in FIG.
The SiO ₂ insulating layer 103 is formed on the surface layer portion of the Si substrate 101 immediately below the second. The thickness of the SiO ₂ insulating layer 103 is approximately 100 nm, and a withstand voltage of 50 V or more is ensured. By the annealing treatment, S
The iGe strain applying layer 102 has a very low defect density, is flat, and has sufficient strain relaxation.

Here, the implantation depth of oxygen ions (the top position of the oxygen concentration profile) is extremely important. If the distance between the SiO ₂ insulating layer and the Si channel is made as short as possible, that is, if the implantation depth is reduced and oxygen is implanted into the SiGe layer in order to be advantageous in reducing the floating capacitance, etc. Oxidation and the precipitation of Ge occur, which makes it impossible not only to maintain sufficient insulation properties, but also significantly deteriorates surface flatness. Therefore, it is necessary that the implantation depth of oxygen ions be directly below the SiGe layer and inside Si. In this way, a flat SiO ₂ layer having excellent insulation properties is formed in the heat treatment process. During the heat treatment process, the SiGe layer recovers from damage due to oxygen ion implantation, the strain is relaxed,
A significantly thinner SiGe strain applying layer can be formed than before. Furthermore, it is desirable that the distance between the SiGe layer and the oxygen ion implantation position is as short as possible. For example, it is preferable that the distance be equal to or less than the critical thickness for strain growth of Si and SiGe (about 400 nm at a Ge concentration of 20% and about 100 nm at a 50% concentration). By doing so, a SiGe strain applying layer in which strain is effectively alleviated is formed. If this distance is significantly reduced, the bottom of the oxygen ion implantation concentration profile enters the SiGe layer. However, if the implantation position (apex of the concentration profile) is located within the Si layer, the above-described step is performed in the subsequent annealing step. The effect of problems such as Ge precipitation is extremely small.

According to this method, a SiGe strain applying layer which is thinner and flatter than the conventional one and has very few crystal defects can be formed on the SiO ₂ insulating layer. The thickness of the Si layer between the SiGe strain applying layer and the SiO ₂ insulating layer may be any thickness that is equal to or less than the SiGe strain applying layer.

Next, as shown in FIG. 4, the strained Si channel layer 10 is formed on the SiGe strain applying layer 102 by a chemical vapor deposition method.
Form 4. The film thickness was 20 nm. Since the strained Si channel layer 104 is formed on the SiGe strain applying layer 102 as described above, the strain is sufficiently relaxed by the SiGe strain applying layer 102 and is extremely flat, which is effective for the strained Si channel layer 104. , And the crystal defect density of the channel layer becomes extremely small. In addition, the strained Si channel layer 10
In order to reduce the punch-through current of the field-effect transistor and to prevent the mobility from being lowered due to the transfer into the channel layer, the thickness of the layer 4 should be approximately 10 (3-2x) nm or less. desirable. In the strained Si channel layer 104, the lattice constant of the SiGe strain applying layer 102 is larger than Si (Si is 5.4309Å,
Ge receives tensile strain because it is 5.6575Å). As a result, the carrier (electron and hole) mobilities therein are larger than the mobility of 1500 (electrons) and 500 (holes) in unstrained Si, for example, about 3500 (electrons) and 5000 (holes). Become.

Next, as shown in FIG. 4, an element isolation insulating region 105 is formed by a conventional method, and an element forming region 121 for forming a field effect transistor or a circuit element including the field effect transistor is formed. . The element isolation insulating region 105
Is formed, for example, by forming a trench and filling the trench with an oxide film.

The element forming region 121 is surrounded by the element isolation insulating region 105, and the lower portion is provided with the SiO ₂ insulating layer 103, so that the element forming region 121 has high electric insulation. Characteristics can be improved.

Next, as shown in FIG. 4, after the surface of the strained Si channel layer 104 is thermally oxidized to form an oxide film and a polysilicon film is overlaid, the polysilicon in the portion excluding the gate formation region is formed. The gate oxide film 106 and the gate electrode 107 are formed by etching the film and the oxide film.

Next, as shown in FIG.
After an oxide film is formed on the main surface side of the substrate, the oxide film is removed by anisotropic etching, and side walls (sidewalls) 122 are formed on both side surfaces of the gate oxide film 106 and the gate electrode 107.

Next, as shown in FIG. 5, a resist is selectively provided on the main surface side of the Si
Using FIG. 2, a diffusion region 108 constituting a source region and a drain region is formed by self-alignment.

Next, as shown in FIG.
Is formed, a contact hole 110 is opened, and a metal film such as Al is deposited and patterned to form a metal wiring 111 on the contact hole 110, thereby completing a field effect transistor (see FIG. 1).

In this field effect transistor, the ion implantation in the formation of the diffusion region
By implanting a group element, an n-type region can be formed and an n-channel field-effect transistor (NMOS) can be formed. By implanting a group III element such as Ga, a p-type region can be formed and a p-channel field-effect transistor (NMOS) can be formed. PMOS). Therefore, the same Si substrate
By forming a PMOS and an NMOS in 101, a CMOSFET can also be manufactured.

The Si substrate 101 shown in FIG. 3 manufactured in the manufacture of the semiconductor device according to the first embodiment is commercially available as it is as a semiconductor substrate.

That is, this semiconductor substrate has a structure in which the SiGe strain applying layer 102 is provided on the main surface of the Si substrate 101, and the SiO ₂ insulating layer 103 is provided inside the surface layer of the Si substrate 101. Then, the dimensions of each part as described above, SiGe strained applied layer 102 has a thickness of about 50 to 200 nm, SiO ₂ insulating layer
103 is approximately 100 nm. The thickness of the Si layer between the SiGe strain applying layer 102 and the SiO ₂ insulating layer 103 is smaller than the thickness of the SiGe strain applying layer.

According to the first embodiment, the following effects can be obtained. (1) The structure of the field effect transistor is excellent in element isolation similar to that of a field effect transistor manufactured using a SIMOX substrate, but the thickness of the SiGe strain applying layer 102 is about 500 nm of the SIMOX substrate. Less than half of that
The thickness can be reduced to about 200 nm or less, and the flatness is improved. As a result, it is possible to prevent threading dislocations, cracks, and deterioration in surface properties of the SiGe strain applying layer, and to realize a heterostructure having good crystallinity. In addition, due to the planarization of the SiGe strain applying layer 102, the strained Si channel layer 104 formed on the SiGe strain applying layer 102 can be made as thin as 10 (3-2x) nm or less. Therefore, reduction of the punch-through current of the field effect transistor,
It is possible to prevent a decrease in mobility due to the occurrence of transition into the channel layer, and to achieve a higher speed and higher performance of the field effect transistor.

(2) According to the above (1), the SiGe strain applying layer
The flattening of the semiconductor layer 102 can be achieved, and fine processing can be performed by reducing the thickness of the strained Si channel layer 104, thereby achieving high integration.

(3) By reducing the thickness of the SiGe strain applying layer 102 and the strained Si channel layer 104, the film formation time can be shortened and the manufacturing cost of the semiconductor device can be reduced.

(4) SiGe strain applying layer 102 and SiO ₂ insulating layer 103
In this case, the thickness of the Si layer becomes smaller than the thickness of the SiGe strain applying layer 102, and the effective formation of the SiGe strain applying layer 102 can be achieved.

(5) It is possible to provide a new semiconductor substrate excellent in flatness of a silicon-on-insulator (SOI) structure whose surface is a SiGe mixed crystal semiconductor layer. This semiconductor substrate has a structure in which a SiGe strain applying layer 102 is provided on a Si substrate 101, and a SiO ₂ insulating layer 103 formed by oxygen ion implantation and annealing is provided inside a surface layer portion of the Si substrate 101. Therefore, in the manufacture thereof, the thickness of the SiGe strain applying layer 102 can be reduced, and
Also the difference in lattice constant from Si (Si lattice constant is 5.4309Å, Ge
Has a lattice constant of 5.6575 °), so that the layer acts as a strain applying layer. Therefore, by using this semiconductor substrate, fine processing of the semiconductor device is also possible, and high integration of the semiconductor device becomes possible. In addition, since a semiconductor substrate having a mixed crystal semiconductor layer having good flatness and serving as a strain applying layer is provided, when a strained channel layer is formed in the mixed crystal semiconductor layer, a high-speed, high-performance field-effect transistor can be manufactured. Can be achieved. Further, as described later, by forming a spacer layer, a carrier supply layer, a cap layer, and the like on the strained Si channel layer 104, a high-speed, high-performance modulation-doped field-effect transistor can be achieved.

(Embodiment 2) FIG. 6 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention. In the second embodiment, in the field-effect transistor of the first embodiment, when the SiO ₂ insulating layer 103 is formed without interposing the Si layer between the SiO ₂ insulating layer 103 and the SiGe strain applying layer 102, When oxygen ions are implanted from the surface of the SiGe strain applying layer 102 on the Si substrate 101 and annealing is performed, the upper surface of the SiO ₂ insulating layer 103 is deformed by controlling the oxygen ion implantation depth and the annealing process. The SiO ₂ insulating layer 103 is formed so as to match the lower surface of the application layer 102.

With this structure, the stray capacitance can be reduced in addition to the effect of the first embodiment.
Improvement of the characteristics of the field effect transistor can be achieved.

In the manufacture of the semiconductor device according to the second embodiment, the device at the stage where the SiO ₂ insulating layer 103 is formed can be sold as a semiconductor substrate. FIG. 7 shows that the upper surface of the SiO ₂ insulating layer 103 has S
5 is a cross-sectional view of a new semiconductor substrate 130 having a structure corresponding to the lower surface of the iGe strain applying layer 102. FIG. The semiconductor substrate 130 having this structure can be marketed as it is, and a semiconductor device having a field-effect transistor, a modulation-doped field-effect transistor described later, or the like can be manufactured using the semiconductor substrate 130.

Embodiment 3 In Embodiment 3, a semiconductor device having a modulation-doped field-effect transistor will be described. FIG. 8 is a schematic cross-sectional view illustrating a modulation-doped field-effect transistor, and FIGS. 9 to 12 are schematic cross-sectional views illustrating a method of manufacturing the modulation-doped field-effect transistor according to the third embodiment.

The semiconductor device 140 of the third embodiment is different from the semiconductor device 100 of the first embodiment in that the strained Si channel layer 1
04, a Si _1-x Ge _x mixed crystal (0 ≦ x ≦ 1) having a thickness of 15 nm
Ge spacer layer 211, SiGe carrier supply layer (carrier doping layer) 212 composed of Sb-doped Si _1-x Ge _x mixed crystal (0 ≦ x ≦ 1) with a thickness of 5 nm, Si _1-x Ge with a thickness of 10 nm _x mixed crystal (0 ≦ x ≦ 1)
The structure has a SiGe cap layer 213 made of Si and a Si cap layer 214 made of Si having a thickness of 5 nm. The mixed crystal ratio x
Is, for example, 0.3.

Further, sidewalls 122 are formed on both ends of the Si cap layer 214 in the element forming region 121 surrounded by the element isolation insulating region 105.
A gate oxide film 106 and a gate electrode 107 are provided. Diffusion regions 108 serving as a source region or a drain region are provided at both ends of the gate oxide film 106. This diffusion region 108 has a structure that reaches the middle depth of the strained Si channel layer 104.

In the manufacture of the semiconductor device 140 according to the third embodiment, as shown in FIG. 9, a SiGe strain applying layer 102 is provided on the main surface of a Si substrate 101, and the SiGe strain applying layer 102 is formed inside the surface layer of the Si substrate 101. A semiconductor substrate having the SiO ₂ insulating layer 103 is manufactured.
This manufacturing method is the same as that of the first embodiment, and has exactly the same structure as that of FIG.

Next, as shown in FIG. 10, a film thickness of 15 nm is formed on the strained Si channel layer 104 by a chemical vapor deposition method.
SiGe spacer layer 211 made of Si _1-x Ge _x mixed crystal (x = 0.3)
A SiGe carrier supply layer (carrier doping layer) 212 made of a 5-nm _- thick Sb-doped Si _1-x Ge _x mixed crystal (x = 0.3),
A 10 nm thick SiGe cap layer 213 made of a mixed crystal of Si _1-x Ge _x (x = 0.3) and a 5 nm thick Si cap layer 214 made of Si are sequentially grown.

Next, as shown in FIG. 11, an element isolation insulating region 105 is formed by a conventional method to form an element forming region 121. The element isolation insulating region 105 is formed, for example, by forming a trench and filling the trench with an oxide film.

Next, as shown in FIG. 11, after the surface of the Si cap layer 214 is thermally oxidized to form an oxide film and a polysilicon film is formed on the silicon cap layer 214, a portion of the polysilicon film excluding the gate forming region is formed. Etch the film and oxide film,
As shown in FIG. 12, the gate oxide film 106 and the gate electrode 107
To form

Next, although not shown, the gate oxide film 106 and the gate electrode 107 are formed in the same manner as in the first embodiment.
After forming sidewalls (sidewalls) 122 on both side surfaces of the semiconductor device, a diffusion region 108 constituting a source region and a drain region is formed by self-alignment using the sidewalls 122 in a conventional manner, and then an interlayer insulating film 109 is formed. Then, a contact hole is opened, and a metal film such as Al is deposited and patterned to form a metal wiring 111 in the contact hole portion, thereby forming an n-type modulation-doped field effect transistor as shown in FIG. Form. The diffusion region 108 has strained Si
The channel layer 104 is formed so as to reach an intermediate depth.

In the ion implantation for forming the diffusion region 108, a p-channel modulation-doped field effect transistor can be manufactured by implanting a Group III element.

Also in the modulation-doped field-effect transistor according to the third embodiment, the flatness is improved by reducing the thickness of the SiGe strain applying layer 102, and the strained Si channel layer 104 formed on the SiGe strain applying layer 102 is also improved. It can be made as thin as 10 (3-2x) nm or less, which can reduce punch-through current, prevent the mobility from dropping due to dislocation into the channel layer, and increase the speed and performance of the field-effect transistor. Can be achieved.

Further, since the strained Si channel layer 104 is made thinner by flattening the SiGe strain applying layer 102, fine processing becomes possible and high integration can be achieved.

Further, by reducing the thickness of the SiGe strain applying layer 102 and the strained Si channel layer 104, the film formation time can be shortened, and the effects such as the reduction of the manufacturing cost of the semiconductor device can be achieved.

Also in the third embodiment, the SiGe strain applying layer
As the upper surface of the SiO ₂ insulating layer 103 is coincident with the lower surface of 102 SiO ₂
By employing the technique of forming the insulating layer 103, the stray capacitance of the modulation-doped field-effect transistor can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, for example, even in the case of a semiconductor device in which another mixed crystal semiconductor layer such as GaAs is formed as the strain applying layer 102 formed on the Si substrate 101, the same effect as in the above embodiment can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technique of the field effect transistor, which is the field of application as the background, has been described, but the invention is not limited to this.

The present invention can be applied to the manufacture of a semiconductor device having at least an active element such as a transistor or a diode.

[0079]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) The field-effect transistor according to the present invention and the semiconductor device incorporating the same have a lower punch-through current, a significantly reduced defect density in the channel portion, and a greater thickness of the strain applying layer (buffer layer) than in the prior art. And the channel portion is excellent in flatness.
That is, the industrial value of the device is extremely high because the speed, integration and performance of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a schematic cross-sectional view of a Si substrate having a SiGe layer formed on a main surface in manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a schematic cross-sectional view in which an SiO ₂ insulating layer is formed on a surface portion of a Si substrate in manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a schematic cross-sectional view of a Si substrate having a gate oxide film and a gate electrode formed on the surface of an element formation region in the manufacture of the semiconductor device of the first embodiment.

FIG. 5 is a schematic cross-sectional view of an Si substrate provided with a contact hole in an interlayer insulating film in manufacturing the semiconductor device of the first embodiment.

FIG. 6 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention.

FIG. 7 is a schematic sectional view showing a semiconductor substrate according to a second embodiment.

FIG. 8 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

FIG. 9 is a schematic cross-sectional view in which a SiGe layer is formed on a main surface and an SiO ₂ insulating layer is formed on a surface layer of a Si substrate in manufacturing the semiconductor device of the third embodiment.

FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to the third embodiment;
FIG. 2 is a schematic cross-sectional view of a Si substrate in which semiconductor layers are sequentially stacked on a main surface of the substrate.

FIG. 11 is a schematic cross-sectional view of a Si substrate in which an element isolation insulating region is provided and a surface portion of the uppermost Si substrate is formed of an oxide film in the manufacture of the semiconductor device of the third embodiment.

FIG. 12 is a schematic cross-sectional view of a Si substrate on which a gate oxide film and a gate electrode have been formed in the manufacture of the semiconductor device of Embodiment 3;

[Explanation of symbols]

100: semiconductor device, 101: Si substrate, 102: Si _0.7 Ge _0.3 buffer layer, 103: SiO ₂ insulating layer, 104: strained Si channel layer, 10
5 ... element isolation insulating region, 106 ... gate oxide film, 107 ... gate electrode, 108 ... diffusion region, 109 ... interlayer insulating film, 110 ... contact hole, 111 ... metal wiring, 121 ... device formation region, 12
2 ... side wall (side wall), 130 ... semiconductor substrate, 140 ... semiconductor device, 211 ... SiGe spacer layer, 212 ... SiGe carrier supply layer, 213 ... SiGe cap layer, 214 ... Si cap layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinya Yamaguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. F-term in Central Research Laboratory (reference) 5F040 DA01 DA18 DB06 DC01 EB12 EC07 EE06 EH02 EK05 EM00 FA03 FA05 5F102 FA00 GA14 GC01 GD10 GJ03 GL03 GL08 HA02

Claims (15)

[Claims] 1. An SiO ₂ insulating layer formed on a Si substrate and formed inside a main surface of the Si substrate, a strain applying layer made of a mixed crystal semiconductor layer provided on the main surface of the Si substrate, A strain channel layer made of a Si layer provided on the strain applying layer, a pair of diffusion regions forming a source region or a drain region provided in the strain channel layer, and a strain channel layer between the pair of diffusion regions. A semiconductor device having a field-effect transistor including a gate electrode provided with a gate insulating film interposed therebetween, wherein the strain applying layer is made of Si _1-x Ge _x (0 ≦ x ≦ 1); 50 applied layers
~ 200 nm thick, the thickness of the Si layer between the Si _1-x Ge _x strain applying layer and the SiO ₂ insulating layer is less than the thickness of the Si _1-x Ge _x strain applying layer. And the thickness of the strain channel layer is
A semiconductor device characterized in that it is about 10 (3-2x) nm or less. 2. A strain applying layer formed on a Si substrate and comprising a mixed crystal semiconductor layer provided on a main surface of the Si substrate, and an upper surface being in contact with a lower surface of the strain applying layer and being along the strain applying layer. An SiO ₂ insulating layer provided in the Si substrate so as to extend, a strain channel layer made of a Si layer provided on the strain applying layer, and a source region or a drain region provided in the strain channel layer A semiconductor device comprising: a field-effect transistor including a pair of diffusion regions and a gate electrode provided on a strained channel layer between the pair of diffusion regions with a gate insulating film interposed therebetween. 3. The strain applying layer is made of Si _1-x Ge _x (0 ≦ x ≦ 1), the strain applying layer has a thickness of 50 to 200 nm, and the strain channel layer has a thickness of 10 3. The semiconductor device according to claim 2, wherein the power is about (3-2x) nm or less. 4. A spacer layer on the strain channel layer,
4. The modulation-doped field effect transistor according to claim 1, wherein a carrier supply layer doped with a conductivity type determining impurity and a cap layer are sequentially formed. 13. The semiconductor device according to claim 1. 5. A strain channel layer formed on a Si substrate and having a Si layer between a source region and a drain region provided on the Si substrate, and a strain channel layer between the source region and the drain region. A method for manufacturing a semiconductor device having a field-effect transistor formed by providing a gate electrode with a gate insulating film interposed therebetween, wherein a strain applying layer made of a mixed crystal semiconductor layer is formed on a main surface of the Si substrate. Forming a SiO ₂ insulating layer in the Si substrate by implanting and annealing oxygen ions from the surface of the strain applying layer, and forming the strain channel layer on the strain applying layer, Forming a device isolation region on the main surface side of the Si substrate to form a device formation region, and forming a diffusion region constituting the gate electrode and a source region or a drain region in the device formation region. The method of manufacturing a semiconductor device characterized by a step. 6. The method according to claim 1, wherein said oxygen ion implantation and annealing treatment conditions are selected so that a surface portion of said Si substrate remains between said strain applying layer and said SiO ₂ insulating layer. A method for manufacturing a semiconductor device according to claim 5. 7. The method according to claim 5, wherein the conditions for the implantation and annealing of the oxygen ions are selected so that the upper surface of the SiO ₂ insulating layer coincides with the lower surface of the strain applying layer. Of manufacturing a semiconductor device. 8. A spacer layer, a delta carrier supply layer doped with a conductivity type determining impurity, on the strain channel layer,
8. The method of manufacturing a semiconductor device according to claim 5, wherein a capping layer is sequentially formed to form a modulation-doped field effect transistor. 9. The strain applying layer is formed to a thickness of 50 to 200 nm, and the thickness of the strain channel layer is formed to be about 10 (3−2 ×) nm or less. To claim 8
13. The method for manufacturing a semiconductor device according to claim 1. 10. A Si substrate, a mixed crystal semiconductor layer grown and formed on a main surface of the Si substrate, and a SiO ₂ insulating layer formed by annealing oxygen ions implanted from the surface of the mixed crystal semiconductor layer. A semiconductor substrate comprising: 11. An Si layer constituting a Si substrate having a thickness equal to or less than the thickness of the mixed crystal semiconductor layer exists between the SiO ₂ insulating layer and the mixed crystal semiconductor layer. A semiconductor substrate according to claim 10. 12. The SiO ₂ insulating layer according to claim 10, wherein a lower surface of said mixed crystal semiconductor layer and an upper surface of said SiO ₂ insulating layer coincide with each other.
A semiconductor substrate according to claim 1. 13. The mixed crystal semiconductor layer has a thickness of 50 to 200 nm.
2. The method according to claim 1, wherein
3. The semiconductor substrate according to any one of 2. 14. The mixed crystal semiconductor layer is formed of Si _1-x Ge _x (0 ≦ x ≦
The semiconductor substrate according to any one of claims 10 to 13, wherein the semiconductor substrate comprises (1). 15. The method for manufacturing a Si substrate according to claim 10, wherein the step of growing and forming a mixed crystal semiconductor layer on a main surface of the Si substrate comprises: Implanting oxygen ions from the surface of the crystalline semiconductor layer so that the peak of the implantation distribution is located in the Si substrate; and
Forming the SiO ₂ insulating layer by annealing the substrate.