JP2000030461A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which operation speed can be increased and power source voltage can be reduced. SOLUTION: A semiconductor memory 1 is provided with a NAND gate 2 for a DRAM, a clock generating circuit 3, an address buffer 4 a row decoder 5, a column decoder 6, an input buffer 10, an output buffer 11, and a memory cell array 8 for a SRAM. The semiconductor memory 1 is operated for a CPU as a DRAM in which operation speed is high and which can be operated by low power source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a memory cell array including a plurality of static memory cells arranged in a matrix.

[0002]

2. Description of the Related Art FIG. 6 is a time chart showing the operation of a semiconductor integrated circuit device having a CPU (central processing unit) and a DRAM (dynamic random access memory). The DRAM control signals / RAS and CAS are originally asynchronous with the clock signal CLK, but are not synchronized with the clock signal CL.
Since it is difficult for a CPU that operates in synchronization with K to operate an asynchronous signal, the CPU operates in synchronization with the clock signal CLK.
The AM control signals / RAS and CAS are created. Actually, a rising edge of clock signal CLK (at time t)
0), the control signal / RAS is set to the "L" level of the activation level, the address signal ADD is supplied to the DRAM as the row address signal RA, and the control signal / CAS is set to the activation level at the third clock (time t1). DRAM at "L" level and address signal ADD as column address CA1
The output data D1 of the DRAM is read at the fourth clock (time t2).

[0003]

However, in the conventional semiconductor integrated circuit device, the specification of the CPU is revised and the speed is increased, and the frequency of the clock signal CLK is, for example, 50 MHz.
When becomes 75MHz from time T _RAC from when the control signal / RAS to "L" level of the active level until retrieve data DO1 is, 50 MHz T _RAC when the
= 20 ns × 4 clocks = 80 ns, which is sufficient, but at 75 MHz, T _RAC = 13.3 ns × 4 clocks = 53.2 ns, so there is no room.

Similarly, the time T _CAC from the time when the control signal / CAS is set to the “L” level of the activation level to the time when the data DO1 is taken out is T _CAC = 20 ns × 50 MHz.
There is room for one clock = 20 ns (specification is about 13 ns), but at 75 MHz, T _CAC = 1
At 3.3 ns, the timing becomes strict in the DRAM. Therefore, when the speed of the CPU is increased, the CPU needs to be revised at the same time to delay the access timing to the DRAM or to use another high-speed memory. Therefore, it has not been easy to increase the operation speed of the semiconductor integrated circuit device.

Even if the specification of the CPU is revised to a low power supply voltage, for example, 2 V, the operating voltage of the DRAM is limited to 5 V to 3.3 V, and the semiconductor integrated circuit device is designed according to the CPU. 5V for DRAM
Alternatively, a power supply circuit for supplying 3.3 V is separately required. Therefore, it has not been easy to reduce the power supply voltage of the semiconductor integrated circuit device.

[0006] Therefore, a main object of the present invention is to provide a semiconductor integrated circuit device capable of increasing operating speed and reducing power supply voltage.

[0007]

The invention according to claim 1 is
A semiconductor integrated circuit device including a memory cell array including a plurality of static memory cells arranged in a matrix, including a row decoder, a column decoder, an address buffer, and a data input / output circuit. The row decoder selects one of the memory cell rows in the memory cell array according to a row address signal. The column decoder selects one of the memory cell columns in the memory cell array according to the column address signal. The address buffer supplies an external address signal to the row decoder as a row address signal in response to the first control signal, and supplies the external address signal to the column decoder as a column address signal in response to the second control signal.
The data input / output circuit exchanges data with a memory cell selected by a row decoder and a column decoder in the memory cell array.

According to a second aspect of the present invention, there is provided the data input / output circuit according to the first aspect of the present invention, which operates in synchronization with a clock signal, and supplies an external address signal and first and second control signals to an address buffer. And a control circuit for transmitting and receiving data.

[0009]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory 1 according to an embodiment of the present invention.
Referring to FIG. 1, a semiconductor memory 1 includes a NAND gate 2, a clock generation circuit 3, an address buffer 4, a row decoder 5, a column decoder 6, a memory mat 7, an input buffer 10, and an output buffer 11, and a memory mat. 7
Denotes an SRAM memory cell array 8 and an input / output control circuit 9
including. This semiconductor memory 1 includes circuits 2 to 2 for DRAM.
10 and 11 and a memory mat 7 for SRAM (static random access memory).
Hereinafter, each of the DRAM and the SRAM will be described in detail.

FIG. 2 is a block diagram showing a configuration of a conventional DRAM 12. As shown in FIG. Referring to FIG.
Comprises a NAND gate 2, a clock generation circuit 3, an address buffer 4, a row decoder 5, a column decoder 6, a memory mat 13, an input buffer 10 and an output buffer 11, and the memory mat 13 is a DRAM memory cell array 14.
And a sense amplifier + input / output control circuit 15.

NAND gate 2 and clock generation circuit 3 control signals / WE, / CAS,
/ RAS, and selects a predetermined operation mode based on DRA.
It controls the entire M12.

Address buffer 4 generates a row address signal RA and a column address signal CA based on an externally applied address signal ADD, and applies the generated signals RA and CA to row decoder 5 and column decoder 6, respectively.

DRAM memory cell array 14 includes a plurality of DRAM memory cells each storing 1-bit data. Each DRAM memory cell is arranged at a predetermined address determined by a row address and a column address.

Row decoder 5 specifies a row address of DRAM memory cell array 14 in response to a row address signal RA given from address buffer 4. Column decoder 6 designates a column address of DRAM memory cell array 14 in response to a column address signal CA provided from address buffer 4.

Sense amplifier + input / output control circuit 15 writes / reads data of a memory cell at an address designated by row decoder 5 and column decoder 6. In a write mode, input buffer 10 supplies externally input data DI to a selected memory cell via sense amplifier + input / output control circuit 15 in response to control signal / WE. Output buffer 11 outputs read data DO from the selected memory cell to the outside in response to a control signal / OE input from the outside in the read mode.

FIG. 3 is a partially omitted circuit block diagram showing the configuration of memory mat 13 of DRAM 12 shown in FIG.

Referring to FIG. 3, DRAM memory cell array 14 includes a plurality of DRAM memory cells MC arranged in a matrix, word lines WL provided corresponding to each row,
It includes a pair of bit lines BL, / BL provided corresponding to each column. Each DRAM memory cell MC is connected to a word line WL in a corresponding row. The plurality of DRAM memory cells MC in each column are alternately connected to bit lines BL or / BL, respectively.

Each DRAM memory cell MC includes an N-channel MOS transistor Q for access and a capacitor C for storing information. The gate of N-channel MOS transistor Q of each DRAM memory cell MC is connected to word line WL of the corresponding row. N channel MOS transistor Q
Is connected between the bit line BL or / BL of the corresponding column and one electrode (storage node) of the capacitor of the memory cell MC. The other electrode of capacitor C of each DRAM memory cell MC receives the cell potential. Word line WL transmits the output of row decoder 5 and activates DRAM memory cells MC in the selected row. Bit line pair B
L and / BL input / output data to / from the selected DRAM memory cell MC.

The sense amplifier + input / output control circuit 15 includes a sense amplifier SA, a column selection gate CSG, and a column selection line CSL provided for each column, and a data input / output line commonly provided for all columns. IO, / IO, a preamplifier 16 and a write buffer 17 are included. In the read mode, sense amplifier SA operates corresponding bit line pair BL, / B
The small potential difference appearing between L is amplified to the power supply voltage. Column select gate CSG includes two N-channel MOS transistors connected between bit lines BL and / BL and data input / output lines IO and / IO, respectively. Two N channels M
The gate of the OS transistor is connected to column decoder 6 via a corresponding column selection line CSL. When column select line CSL is raised to the selected level "H" level by column decoder 6, two N-channel MOS transistors are turned on, and bit line pair BL, / BL and data input / output line pair IO,
/ IO.

The preamplifier 16 supplies data DO according to the potential difference appearing on the data input / output lines IO and / IO to the output buffer 11 in the read mode. Write buffer 17
In the write mode, one of data input / output lines IO and / IO is set to "H" level and the other is set to "L" level in accordance with data DI applied from input buffer 10, and selected DRAM memory cell MC Is written in the data DI.

Next, the DRAM 1 shown in FIGS.
Operation 2 will be briefly described. In the write mode, column decoder 6 raises column selection line CSL of the column corresponding to column address signal CA to an activation level of "H" level to conduct column selection gate CSG.

In response to a control signal / WE, input buffer 10 applies externally applied write data DI via sense amplifier + input / output control circuit 15 to a bit line pair BL, / BL of a column selected. Give to. Write data DI is applied as a potential difference between bit lines BL and / BL. Next, row decoder 5 raises word line WL of the row corresponding to row address signal RA to an activation level of "H" level,
The MOS transistor Q of the memory cell MC in that row is turned on. A charge corresponding to the potential of the bit line BL or / BL is stored in the capacitor C of the selected memory cell MC.

In the read mode, after the potentials of bit lines BL and / BL are equalized to a predetermined potential by an equalizer (not shown), row decoder 6 sets word line WL of a row corresponding to row address signal RA to a selected level. It is raised to "H" level. The potentials of bit lines BL and / BL change by a very small amount according to the amount of charge of capacitor C of activated DRAM memory cell MC.

Next, the voltage between the bit lines BL and / BL is amplified to the power supply voltage by the sense amplifier SA. That is, when the potential of bit line BL is slightly higher than the potential of bit line / BL, the potential of bit line BL is raised to "H" level and the potential of bit line / BL is lowered to "L" level. Conversely, when the potential of bit line / BL is slightly higher than bit line BL, the potential of bit line / BL is raised to "H" level and the potential of bit line BL is lowered to "L" level. .

Next, the column decoder 6 outputs the column address signal C
The column selection line CSL of the column corresponding to A is set to the selection level “H”.
Level, and the column select gate SCG of that column is turned on. The data of the bit line pair BL, / BL of the selected column is applied to the column select gate CSG, the data input / output line pair IO, / I
O and the output buffer 11 via the preamplifier 16. Output buffer 11 outputs read data DO to the outside in response to control signal / OE.

FIG. 4 is a block diagram showing the configuration of a conventional SRAM 20. Referring to FIG.
Are the row address buffer 21 and the column address buffer 2
2, a row decoder 23, a column decoder 24, a memory mat 7, an input buffer 25, and an output buffer 26,
Memory mat 7 includes an SRAM memory cell array 8 and an input / output control circuit 9.

Row address buffer 21 transmits an externally applied row address signal RA to row decoder 23. Column address buffer 22 transmits an externally applied column address signal CA to column decoder 24. SR
AM memory cell array 8 includes a plurality of SRAM memory cells each storing 1-bit data. Each SR
The AM memory cell is arranged at a predetermined address determined by a row address and a column address.

The row decoder 23 includes a row address buffer 2
1 in response to a row address signal RA given from SR1.
A row address of the AM memory cell array 8 is specified. Column decoder 24 specifies a column address of DRAM memory cell array 8 in response to a column address signal CA provided from column address buffer 22.

Input / output control circuit 9 writes / reads data of a memory cell at an address designated by row decoder 23 and column decoder 24. Input buffer 25
Is an externally applied control signal WE in the write mode.
In response to an externally applied data DI to the selected memory cell via the input / output control circuit 9. Output buffer 26 externally outputs read data DO from the selected memory cell in response to a control signal / OE input externally in the read mode.

FIG. 5 is a block diagram showing a configuration of the memory mat 7 of the SRAM shown in FIG.

Referring to FIG. 5, SRAM memory cell array 8 includes a plurality of (four for simplicity of the drawing and description) SRAM memory cells MC arranged in a matrix.
A word line WL provided corresponding to each row, a bit line pair BL, / BL provided corresponding to each column, and a bit line load 2 provided corresponding to each bit line BL or / BL.
7 and an equalizer 28 provided corresponding to each bit line pair BL, / BL.

The SRAM memory cell MC includes load resistance elements 31 and 32 and a driver transistor (N-channel MOS).
Transistors) 33, 34, access transistor (N
Channel MOS transistors) 35 and 36 and storage nodes N1 and N2. The load resistance elements 31 and 32 are respectively connected to the power supply potential VCC line and the storage nodes N1 and N2
Connected between Driver transistors 33, 34
Are connected between storage nodes N1 and N2 and a line of ground potential GND, respectively, and their gates are connected to storage nodes N2 and N1, respectively. The resistance elements 31 and 32 and the driver transistors 33 and 34 form a flip-flop. The access transistors 35 and 36
Bit lines BL, corresponding to storage nodes N1, N2, respectively,
/ BL, and each gate is connected to a corresponding word line WL.

The SRAM memory cell MC has a storage node N
1 and N2 hold the “H” level and the other “L”
By storing the level, 1-bit data is stored. For example, when "H" level is written to storage node N1 and "L" level is written to storage node N2, driver transistor 34 is turned on and driver transistor 33 is turned off, and storage nodes N1 and N2 are turned off. , That is, data is held. When the corresponding word line WL attains the "H" level of the selected level, access transistors 35 and 36 become conductive and SRAM memory cell MC
Is activated. That is, storage nodes N1 and N2 are coupled to bit lines BL and / BL, respectively, and bit line B
Data can be written to / read from the SRAM memory cell MC via L and / BL.

Bit line load 27 is formed of an N-channel MOS transistor diode-connected between a power supply potential VCC line and one end of corresponding bit line BL or / BL. To the power supply potential VCC. Equalizer 28 is connected between corresponding bit line pair BL and / BL, and has a P-channel MOS gate whose gate receives bit line equalize signal BLEQ.
It is composed of transistors, and equalizes the potentials of corresponding bit lines BL and / BL in the read mode.

The input / output control circuit 9 includes a column selection gate CSG and a column selection line CSL provided corresponding to each column.
And a data input / output line pair I commonly provided for all columns.
O, / IO, preamplifier 37 and write buffer 38
And The column selection gate CSG is connected to the bit line B
It includes two N-channel MOS transistors connected between the other ends of L and / BL and data input / output lines IO and / IO. The gates of the two N-channel MOS transistors are connected to column decoder 24 via a corresponding column selection line CSL. When column select line CSL is raised to the "H" level of the selected level by column decoder 24, the two N-channel MOS transistors are turned on, and bit line pair BL, /
BL and data input / output line pair IO, / IO are coupled.

In the read mode, preamplifier 37 supplies data DO to output buffer 26 in accordance with the potential difference appearing on data input / output line pair IO, / IO. Write buffer 3
In the write mode, one of the data input / output lines IO and / IO is set to the "H" level and the other is set to the "L" level in accordance with the data DI given from the input buffer 25, and the selected SRAM memory cell The data DI is written to the MC.

Next, the SRAM 2 shown in FIGS.
The operation of 0 will be described. During a write operation, row address signal RA is externally applied to row decoder 23 via row address buffer 21, and word line WL corresponding to row address signal RA is selected to "H" by row decoder 23. The level is raised to the level, and the SRAM memory cell MC connected to the word line WL is activated. Also, a column address signal CA is externally applied to a column decoder 24 via a column address buffer 22, and the column decoder 2
4, a column selection line C corresponding to the column address signal CA.
SL is raised to the selected level "H" level, column select gate CSG is turned on, and activated memory cell MC is connected to bit line pair BL, / BL and data input / output line pair IO,
It is connected to the write buffer 38 via / IO.

The write buffer 38 is connected to the input buffer 25.
In accordance with data DI externally supplied via the data SRAM, one of the data input / output line pairs IO and / IO is set to the "H" level and the other is set to the "L" level to select the selected SRAM.
The data DI is written to the memory cell MC. Word line W
When L and column select line CSL fall to "L" level, data DI is stored in that memory cell MC.

At the time of a read operation, a column address signal CA is externally applied to column decoder 24 via column address buffer 22, and column select line CSL corresponding to the column address signal CA is selected by column decoder 24 at the selected level " The level is raised to "H" level, column select gate CSG is turned on, and bit line pair BL, / BL is connected to preamplifier 37 via data input line pair IO, / IO. Further, bit line equalize signal / BLEQ attains the "L" level of the activation level, equalizer 28 conducts, and bit lines BL and / BL
Is equalized.

After bit line equalize signal / BLEQ attains an inactive level of "H" level and equalizer 28 is rendered non-conductive, externally, row address signal RA is applied to row decoder 23 via row address buffer 21. Given
The word line WL corresponding to the row address signal RA is raised to the selected level “H” by the row decoder 23, and the memory cells MC connected to the word line WL are activated. As a result, a current flows into the SRAM memory cell MC from one of the bit line pair BL and / BL according to the data stored in the SRAM memory cell MC, and the current flows between the data input / output line pair IO and / IO. One of the potentials decreases. The preamplifier 37 compares the potentials of the data input / output lines IO and / IO, and outputs data DO according to the comparison result to the outside via the output buffer 26.

As described above, in the DRAM 12, a certain time is required for the sense amplifier SA to detect and amplify the minute potential difference between the pair of bit lines BL and / BL generated by the charge of the capacitor C of the memory cell MC. .

On the other hand, in the SRAM 20, since the memory cell MC includes a flip-flop, when the word line WL is set to the selected level and the memory cell MC is activated,
A larger potential difference than the DRAM 12 appears immediately on the bit line pair BL, / BL. For this reason, the sense amplifier operation as in the DRAM 12 becomes unnecessary, and the access speed becomes lower.
It is much faster than AM12.

Therefore, as shown in FIG. 1, control signals / RAS, / CAS, / WE, / OE for DRAM, address signal ADD, NAND gate 2, clock generation circuit 3, address buffer 4, row decoder 5 , Column decoder 6, input buffer 10 and output buffer 11 use the conventional DRAM 12, and memory cell array 8 and input / output control circuit 9 use the conventional SRAM 20 to form semiconductor memory 1.

This semiconductor memory 1 has a normal DRAM 12
Since _TRAC and _TCAC behave as a fraction of a high-speed DRAM as compared with the above, it is not necessary to change the timing of controlling the memory of the CPU even when the specification of the CPU is revised and the speed is increased.

By using the SRAM memory cell array 8 and the input / output control circuit 9, the semiconductor memory 1 behaves as a DRAM that operates at a lower power supply voltage than a normal DRAM. Therefore, even when the power supply voltage is lowered, it is not necessary to separately provide a power supply circuit for the DRAM.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0047]

As described above, according to the first aspect of the present invention, a memory cell array and a data input / output circuit for an SRAM, and a row decoder, a column decoder and an address buffer for a DRAM are provided. Therefore, the memory section of this semiconductor integrated circuit device has an access speed several times higher than that of a normal DRAM, and operates at a low power supply voltage.
Act as AM.

According to a second aspect of the present invention, in the data input / output circuit according to the first aspect of the present invention, the data input / output circuit operates in synchronization with a clock signal, and supplies an external address signal and first and second control signals to an address buffer. And a control circuit for transmitting and receiving data. In this case, even if the speed of the control circuit is increased, the memory section operates at a sufficiently high speed, so that it is not necessary to delay the timing at which the control circuit exchanges data. Further, since the memory section operates at the low power supply voltage even if the control circuit is lowered in power supply voltage, it is not necessary to separately provide a power supply circuit for the memory section.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional DRAM.

FIG. 3 is a circuit block diagram showing a configuration of a memory mat shown in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a conventional SRAM.

FIG. 5 is a circuit block diagram showing a configuration of a memory mat shown in FIG.

FIG. 6 is a time chart showing an operation of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 semiconductor memory, 2 NAND gate, 3 clock generation circuit, 4 address buffer, 5,23 row decoder, 6,24 column decoder, 7,13 memory mat,
8 SRAM memory cell array, 9 input / output control circuit,
10, 25 input buffer, 11, 26 output buffer, 12 DRAM, 14 DRAM memory cell array, 15 sense amplifier + input / output control circuit, 16, 37
Preamplifier, 17, 38 write buffer, 21 row address buffer, 22 column address buffer, 27
Bit line load, 28 equalizer, 31, 32 load resistance element, 33, 34 driver transistor, 35, 3
6 access transistor, MC memory cell, WL
Word line, BL, / BL bit line pair, IO, / IO data input / output line pair, CSG column selection gate, CSL column selection line, SA sense amplifier.

Claims (2)

[Claims] 1. A semiconductor integrated circuit device provided with a memory cell array including a plurality of static memory cells arranged in a matrix, wherein one of the memory cell arrays is selected according to a row address signal. A row decoder for selecting one of the memory cell columns in the memory cell array according to a column address signal; an external address signal provided as a row address signal to the row decoder in response to a first control signal; And an address buffer for providing an external address signal as a column address signal to the column decoder in response to the control signal of No. 2 and exchanging data with a memory cell selected by the row decoder and the column decoder in the memory cell array. A semiconductor integrated circuit device including a data input / output circuit. A control circuit that operates in synchronization with a clock signal, supplies the external address signal and the first and second control signals to the address buffer, and exchanges data with the data input / output circuit. The semiconductor integrated circuit device according to claim 1, further comprising: