JP2000029782A - Memory control method and device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a cache hit rate and to improve the throughput of a system by performing an appropriate address conversion processing at memory accessing. SOLUTION: A frame memory 4 is a memory accessible by a row address, and a column address and is constituted of two frame buffers. A bus mediation part 9 mediates a bus request and an access request from respective controllers 7, 8 and 10 and converts a logical address for access to the frame memory 4 provided from the respective controllers to a real address for improving the cache hit rate. For instance, the bus mediation part 9 converts a logical address group for indicating successive two segments constituted of the prescribed number of the same column address groups on the same row address of the two frame buffers into a real address group for indicating successive two segments on the same row address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control method and device. In particular, the present invention relates to a memory control method and apparatus suitable for controlling a frame memory for image use, which is used for an interface between a host device (personal computer, workstation, TV) and a display device.

[0002]

2. Description of the Related Art Hitherto, it has been known that a frame memory for image use is configured by using a protocol control DRAM with a sense amplifier cache. Further, in controlling a display such as a ferroelectric liquid crystal display (FLCD) having a function of maintaining an image display state, a so-called partial rewriting process for rewriting based on a portion where an image content has changed is known. Have been.

In such a partial rewriting process, the CP
Unlike random access of the main memory from U, random memory access will frequently occur. For this reason, the system overhead increases due to a decrease in the cache hit rate.
In order to supplement the overhead, a memory configuration having a sufficient memory bandwidth has been used.

The refresh control required for the DRAM is performed during the input horizontal / vertical synchronization period in order to effectively use the bandwidth of the memory. In a system where refresh cannot be performed during this period, the refresh control is performed anywhere. However, a memory having a sufficient memory bandwidth to cope with the problem was used.

[0005]

However, as in the above prior art, in order to cope with a decrease in the cache hit rate and a decrease in the memory bandwidth due to refresh, etc.,
The use of a means simply extending to a memory configuration having a sufficient memory bandwidth raises the problem of increasing the minimum memory unit cost required for the system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a memory control method and apparatus which improves a system throughput by improving a cache hit rate.

Another object of the present invention is to improve the cache hit rate by performing appropriate address translation.

Another object of the present invention is to realize refresh-free by performing appropriate address conversion.

[0009]

According to an aspect of the present invention, there is provided a memory control apparatus having the following configuration. That is, a memory control device for accessing a memory by a row address and a column address, wherein two logical addresses composed of a predetermined number of the same column address groups that are continuous on two different row addresses having a predetermined positional relationship A conversion unit for converting the group into two real address groups each including a predetermined number of continuous column address groups that do not overlap on the same row address; and using the address included in the access command as a logical address. And an access execution unit for providing access to the conversion unit and executing an access using the real address obtained as a conversion result.

[0010]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of a display device system according to a first embodiment. In FIG. 1, reference numeral 1 denotes a host device such as a personal computer / workstation / TV, which outputs a synchronization signal and the like together with input image data. Reference numeral 2 denotes a motion detection unit which converts a video signal from the host device 1 into a data format in the display device, compares data of the previous frame with the current frame in line units, and compares the comparison result with a random display line address. It is output to the display controller 5 of the display controller 5 or the memory controller 3 as information 11. In the data comparison in the motion detecting unit 2, the data of the previous frame is read from the frame memory 4 via the memory control unit 3, and the input data of the current frame from the host device 1 and the read data are compared in line units. The write data used for this processing is output to the memory control unit 3 through.

On the other hand, the frame memory 4 (in this embodiment, a DRAM of a protocol system with a sense amplifier cache represented by an RDRAM is used) has a double buffer structure for two frames. The write controller 7, the read controller 8, and the display controller 10 issue an address (hereinafter, logical address) to the frame memory 4 so as to read from one frame buffer and write to the other frame buffer. That is, one buffer is used as a write-only frame buffer and the other buffer is used as a read-only frame buffer, and these frame buffers can be switched as appropriate on a frame basis.

Further, the display controller 5 requests the display controller 10 of the memory controller 3 to read data corresponding to the random display line address information 11 described above. The display controller 10
The logical address is set so that the corresponding data is read from the read-only buffer of the frame memory 4, and the read data is transferred to the display control unit 5 via the bus arbitration unit 9 as dispatch data (panel transfer data). The control unit 5 converts the dispatch data into an appropriate data format for the flat display 6,
Display on the display 6 is performed.

As described above, in the present embodiment, three types of access to the frame memory 4 are generated: read / write / dispatch (read). Further, for access to the frame memory 4, the bus arbitration unit 9 performs appropriate bus arbitration and protocol control adapted to the frame memory 4.

Next, the memory control unit 3 will be described in detail. The main function of the memory control unit 3 is the bus arbitration described above. A data buffer (FIFO) that saves data for each request in order to efficiently perform arbitration between the three parties each time a read / write / dispatch request occurs.
Is provided.

When a read control signal requesting a data read from the frame memory 4 is input to the read controller 8 from the motion detector 2, the read controller 8
Based on the read control signal, a read request (hereinafter, RREQ) is sent to the bus arbitration unit 9, and a memory read address (hereinafter, RADD) is calculated and output by the read frame address generation circuit 16. The memory read request is output to the bus arbitration unit 9 before the motion detection unit 2 needs data. When a read acknowledgment (RACK) as an arbitration result is received from the bus arbitration unit 9 and the bus right is acquired, data (RDATA) corresponding to RADD is read from the frame memory 4 and temporarily stored in the read FIFO 13. You. Lead F
The read data stored in the IFO 13 is stored in the motion detector 2
Is read out at an appropriate timing by the
Provided to

When write data is output from the motion detector 2, the output write data is sequentially stored in the write FIFO 12. When a predetermined amount of write data is accumulated, the write controller 7 issues a write request (hereinafter, WREQ) to the bus arbitration unit 9 and writes a memory write address (hereinafter, WA) to be written to.
DD) is calculated by the write frame address generation circuit 15 and output. As an arbitration result, when a write acknowledge (WACK) is received from the bus arbitration unit 9 and the bus right is acquired, data is written to the frame memory 4. The generation of the memory write request occurs with a certain delay time after the read of the motion detection unit 2 occurs.

As described above, the read / write access is executed at a speed synchronized with the frame frequency of the host device 1, and the data is read from and written to the frame memory 4. Each of the write FIFO 12 and the read FIFO 13 absorbs the time waited by bus arbitration, and cannot maintain a speed synchronized with the frame frequency of the host device 1 (a state in which FIFO overflow / underflow occurs). It has a minimum capacity so that there is no.

Further, in the present embodiment, an output request (dispatch request) to the flat panel is randomly generated during the read / write transfer access described above. The frequency of occurrence depends on the scan frequency of the flat panel display, and occurs asynchronously with the input frame frequency.

When the display controller 10 receives a dispatch control signal from the display controller 5, the display controller 10
A dispatch request (hereinafter DREQ) is issued to the bus arbitration unit 9. At this time, the dispatch line address generation circuit 17 of the display controller 10
Based on the random display line address information 11 output by the motion detector 2, a memory dispatch address (hereinafter, DADD) is calculated and output. The memory dispatch request is output before the display control unit 5 needs the dispatch data. Then, the display controller 10 receives a read acknowledgment (hereinafter, DACK) as an arbitration result from the bus arbitration unit 9 and, when acquiring the bus right, reads data from the frame memory 4 and temporarily stores the data in the dispatch FIFO 14. The dispatch data stored in the dispatch FIFO 14 is read out at an appropriate timing by the display control unit 5 and displayed on the flat panel display 6.

FIG. 2 shows the timing of a series of control described above. FIG. 2 is a timing chart showing an operation in each access of write / read / dispatch.

In FIG. 2, reference numeral 18 denotes a timing in write data transfer. The write FIFO 12 absorbs the transfer gap between the write data output from the motion detector 2 and the high-speed transfer data (WDATA) to the frame memory 4. The write FIFO 12 allocates half of the capacity for one transfer, and every half is written to Half.
A flag “Full (HFULL)” is set, and WREQ is output to the bus arbitration unit 9.

Reference numeral 19 denotes the timing in read data transfer. The read FIFO 13 absorbs the transfer gap between the read data output to the motion detector 2 and the high-speed transfer data (RDATA) from the frame memory 4. The read FIFO 13 also allocates half the capacity for one transfer. The read FIFO 13 performs write setup (AllFull state) on the entire capacity before the read request from the motion detection unit 2, and thereafter, every time half the read is performed
Set a flag called HalfEmpty (HEMPTY) and RRE
Q is output to the bus arbitration unit 9.

Reference numeral 20 denotes the data timing of the dispatch data transfer. The dispatch FIFO 14 outputs dispatch line data to the display control unit 5 and high-speed transfer data (DDAT) from the frame memory 4.
The transfer gap with (A) is absorbed. Dispatch F
The FIFO 14 also allocates half the capacity for one transfer amount,
Prior to a read request from the display control unit 5 (synchronizing with the flat panel synchronization signal of 23), writing setup (AllFull state) is performed for all the capacity. afterwards,
A flag HalfEmpty (HEMPTY) is set every time half is read, and DREQ is output to the bus arbitration unit 9.

With reference to FIG. 3, a means for realizing continuous real-time transfer for all three kinds of requests of read / write / dispatch in response to the above-mentioned FIFO control method will be described in detail. FIG. 3 is a diagram showing the transfer timing of read, write, and dispatch data in the segment division time. FIG.
Is enlarged.

The segment division time 30 (TSEG) is a segment division time obtained by dividing the image data from the motion detector 2 by the amount of data for the burst transfer to the frame memory 4. Specifically, the following conditional expression (1) is defined by: Segment segmentation time (TSEG) = valid period of input image data / (horizontal data amount / frame memory burst transfer amount) (1).

In this segment division time TSEG, the current write data is written to the write FIFO 12 and, at the same time, the write data written in the previous segment is transferred to the frame memory 4. The write transfer time 32 (TW) is determined by the bandwidth of the frame memory 4. Similarly, within the segment division time TSEG, the current read data is read FI
At the same time that data is read from the FO 13 to the motion detection unit 2, read data to be read in the next segment is input from the frame memory 4. This read transfer time 3
1 (TR) is determined by the bandwidth of the frame memory.

As described above, the write and read operations operate in synchronization with the rate of the input image. Therefore, if the following conditional expression (2) TSEG- (TR + TW)> 0 (2) is observed, continuous operation is possible. Transfer is realized.

Since the read request is generated earlier than the write request is generated (as described above, the read is always generated earlier than the write on the same line because the motion detector 2 detects the motion). Do),
The order of fitting the read transfer time TR and the write transfer time TW into the segment division time TSEG is uniquely determined as shown in FIG.

Next, a description will be given of how the dispatch data of the random cycle is continuously transferred from the frame memory 4 in response to the dispatch request from the flat display 6 which is generated asynchronously with the read / write.

As an overview, the segment division time TSEG
The dispatch time is allocated to the remaining time other than the read transfer time TR and the write transfer time TW.

In the case of dispatch data transfer, similarly to the above-mentioned read / write data transfer, the segment division time T
Based on the fit into the SEG. Segment division time TS
In the EG, the dispatch data is sent to the dispatch FI
At the same time as the data is read from the FO 14 to the display control unit 5, the dispatch data read in the next segment is provided from the frame memory 4 to the FIFO 14.
The dispatch transfer time 33 (TD) is determined by the bandwidth of the frame memory.

Under the condition of the expression (2), the dispatch fitting time 34 (TINSERT) is defined by the following conditional expression (3): TINSERT = TSEG- (TR + TW)> 0 (3) By satisfying the condition of equation (3),
Dispatch in segment time of dispatch leads /
It does not prevent continuous transfer of the write.

By satisfying the following conditional expression (4), TDSCAN> TWAIT + TD (4), continuous dispatch transfer can be realized. In equation (4), TDSCAN is the dispatch skip time 36, which is the time during which data for the burst transfer of dispatch is read from the dispatch FIFO 14 to the display control unit 5. Also, TWAIT
Is the dispatch waiting maximum time 35, and the dispatch request occurs at the fastest time in the segment (57 in FIG. 3).
(See FIG. 3) when a read request is generated at the same time as when a read request is generated).

The basic operation of the system according to this embodiment has been described above in detail. The feature of this embodiment is to improve the performance of the memory control unit of the entire system. Hereinafter, the case where the video transfer rate from the host device 1 increases (the segment division time 30 in FIG. 3).
(When TSEG is shortened) will be described.

FIG. 4 is a block diagram showing the internal configuration of the bus arbitration unit 9 according to this embodiment. In FIG. 4, a bus arbitration circuit 37 receives (requires) the above-described requests for read data transfer, write data transfer, and dispatch data transfer, and determines (arbitrates) to which controller the bus right is transferred.
Based on the arbitration result of the bus arbitration circuit 37, the address selector 39 selects the above-mentioned addresses (RADD, WADD,
DADD). The selected address is
The address is provided to the address conversion circuit 40 as a logical address 42. The address conversion circuit 40 converts the logical address 42 into a physical address 43 to be provided to the frame memory 4 by an address conversion method described later.

On the other hand, the memory protocol control circuit 38
The control protocol packet 41 for the frame memory 4 is generated according to the conversion method of the address conversion circuit 40.

The memory protocol control circuit 38 controls a transfer protocol to the frame memory 4. More specifically, as shown in FIGS. 5 to 8, at the time of write data transfer and read data transfer, the current frame memory 4
The access time is switched by determining whether or not the data of the row address is present in the sense amplifier cache inside the frame memory 4.

FIG. 5 is a diagram showing a data transfer cycle time when a cache hit occurs during read data transfer. As shown in FIG. 5, the read data transfer cycle time is: TRHC (45) + TRHA (46) + TRT (47) (5)

FIG. 6 is a diagram showing a data transfer cycle time when a cache miss occurs during read data transfer. As shown in FIG. 6, the read data transfer cycle time in this case is TRMHC (48) + TRMHA (49) + TRT (50) (6).

In the above equations (5) and (6), TRHC
Since (45) = TRMHC (48), the difference overhead time of the read data transfer between the cache hit and the mishit is given by the following equation (2) −equation (1) = TRMHA (49) −TRHA (46) 7)

FIG. 7 shows a data transfer cycle time when a cache hit occurs during write data transfer. As shown in FIG. 7, the read data transfer cycle time in this case is TWHC (51) + TWT (52) (8). FIG. 8 is a diagram showing a data transfer cycle time when a cache miss occurs during write data transfer. As shown in FIG. 8, the read data transfer cycle time in this case is TWMHC (53) + TWMHA (54) + TWT (55) (9).

In the above equations (8) and (9), TWH
Since C (51) = TWMHC (53), the differential overhead time of the write data transfer at the time of a cache hit and at the time of a mishit is given by Expression (10) -Equation (9) = TWMHA (54) (10) .

By making the overhead times (7) and (10) close to 0, the segment division time T
The SEG can be reduced, and as a result, the performance of the entire system can be improved. This is realized by the address conversion circuit 40 in the present embodiment.

First, a general technique for generating the physical address 43 as a through without converting the logical address 42 by the address generation circuit 40 will be described with reference to the logical address mapping image of FIG. FIG. 9 is a diagram showing general address mapping in a double buffer configuration.

In the case of using a double buffer configuration in which a write frame buffer and a read frame buffer are separated, 1280 × 1024 data is stored in the frame memory 4 by address mapping as shown in FIG. Here, the data transfer of read (hereinafter R) and write (hereinafter W) and random dispatch (hereinafter D) according to the raster rule are performed as described above as R → W → D → R.
Are repeated in this order. In this case, the access indicated by the arrow in FIG.
1, row # 0, segment # 0) → W (frame # 0,
Row # 0, segment # 0) → D (frame # 1, row #N, segment #M) → R (frame # 1, row #)
0, segment # 1)... Occur in the frame memory 4.
The transitions 60, 61, and 62 at this time are all misses because there is no regularity of the same row address.

If one of the double buffers is fixed as a write-only buffer and one is a read / dispatch-only buffer, a random hit does not occur in the write-only buffer, so a cache hit occurs. However, in such control, it is necessary to swap buffers at the timing of the frame period in order to update the display. When a buffer is swapped, a buffer that was physically read before may be replaced by a write,
R → W (buffer # 1) → D (buffer # 0) → <swap> → R (buffer # 1) → W (buffer # 0) → D
(Buffer # 1), and a write miss occurs. In practice, if there is a possibility of a miss hit, it is necessary to estimate the worst. Therefore, assuming that the write is also a mishit, the total overhead of the transfer access time within one segment division time (TSEG) is (TRMHA (49) −TRHA (46)) × 2 + TMWHA (54) (11).

Next, the address mapping of the present embodiment in which the logical address 42 is converted by the address conversion circuit 40 to generate the physical address 43 will be described. The address conversion circuit 40 of the present embodiment reads and writes a logical address 42 for continuously reading and writing the same row address and column address in different frame memories with respect to the same row address in the same frame memory. (To be referred to as the same row address mapping). FIG. 10 is a diagram illustrating the same row address mapping according to the first embodiment.

The same row address mapping provides a mixed state of a write frame buffer and a read frame buffer. In the case of the example of FIG.
The data of × 1024 is stored in the frame memory 4 by the address as shown in FIG. Here, read data transfer (hereinafter R) and write data transfer (hereinafter W) according to the raster rule and random dispatch data transfer (hereinafter D) repeat transfer in the order of R → W → D → R. And Then, an access as indicated by an arrow in FIG. 7, that is, R (frame # 0, row # 0, segment # 1)
→ W (frame # 0, row # 0, segment # 0) → D
(Frame # 1, row #N, segment #M) → R (frame # 0, row # 0, segment # 3)... Occur in the frame memory 4. Of the transitions 63, 64 and 65 at this time, R → W transition 6 having regularity of the same row address
3 is a hit, a transition 64 of W → D, D → R without regularity,
65 is a miss hit.

Therefore, one segment division time (TSEG)
The total overhead of the transfer access time in (2) is (TRMHA (49) -TRHA (46)) × 2 (12).

The difference in performance between the case where the address conversion is performed and the case where the address conversion is not performed is as follows: Equation (11) -Equation (12) = TWMHA (13) per one segment division time. Then
TWMHA × (number of segments) × (number of lines) = 4 cycles × 8 × 1024 = 32768 cycles (14) The system performance can be improved.

FIG. 11 is a diagram for explaining an address conversion process by the address conversion circuit 40 according to the first embodiment. As shown in FIG.
Defines the breakdown of the logical address LADD [18: 0] as LADD [18] ... chip address LADD [17] ... bank address LADD [16: 8] ... row address LADD [7: 0] ... column address To the physical address MADD [18: 0]
MADD [18] ← LADD [17] MADD [17: 9] ← LADD [16: 8] MADD [8: 6] ← LADD [7: 5] MADD [5] ← LADD [18] (Read: 1) / Write: 0) MADD [4: 0] ← LADD [4: 0]

As described above, the access at the time of data transfer shown in FIG. 10 is realized by converting the address. That is, a write address (WADD), a read address (RADD), a dispatch address (DAD)
D) is issued as a frame memory having a double buffer configuration of a read-only frame buffer and a write-only frame buffer. At this time, continuous WA
The DD and RADD (both WADD and RADD addressing with a column group of 32 columns as a burst unit) continuously access the same row address of different chip addresses. The address conversion circuit 40
ADD and RADD are input as LADD, and these addresses are converted into continuous column groups on the same row address of the same chip. Therefore, a cache hit occurs in the WADD access following the RADD access.

As described above, according to the first embodiment, by performing address conversion utilizing the regularity of raster scan access to the frame memory, the cache hit rate is improved, and the minimum memory bandwidth is Can configure the system.

[Second Embodiment] The read / write operation of the first embodiment operates in synchronization with the host synchronization signal 22 (horizontal synchronization signal or the like). Then, each memory access is always in an idle state (a state in which there is no memory access) (see FIG. 2). Usually dynamic RAM for image applications
When a (DRAM) type memory is used, a memory refresh operation is generally performed during the blanking period 24. To achieve this, the refresh reference input 26 of the refresh circuit 27 in FIG. 1 may be generated regularly during the blanking period.

However, as in the first embodiment, a series of dispatch transfers 20 synchronized with the flat panel synchronization signal 23 generated asynchronously with the host synchronization signal 22 is likely to occur during this blanking period. . Therefore, a refresh operation cannot be inserted within the blanking period.

In such a case, if an external clock having a refresh cycle of the memory is input as a refresh reference signal and the refresh request (REFREQ) 26 is generated asynchronously, the transfer bandwidth of the frame memory is reduced. Requires a high-speed memory that further increases the number of memory cells. In addition, the write FIFO 1
The FIFO amount of the 2 / read FIFO 13 / dispatch FIFO 14 must be further increased. Furthermore, by the refresh address interrupt,
The regularity of the address conversion of the first embodiment is lost, and the effects of the first embodiment cannot be obtained.

Therefore, a dynamic RAM (DRAM)
In a system such as the first embodiment in which is used for high-band and random memory access, a system configuration that does not need to be refreshed (refresh-free) is indispensable.

First, the following example is considered as a system condition. 1) Host input unit: input resolution SXGA mode (128
0 × 1024, 75Hz) 2) Flat panel: display resolution (1280 ×
1024) Number of display colors (12 bits / pixel) 3) Frame memory used: 16M (× 8) RDRAM.

In the address conversion shown in FIG. 10, lines 0 to 1023 are sequentially accessed (written and read) at a scan rate based on a raster input from the host device 1. Low-speed reading by dispatch occurs by arbitration with read access from a frame buffer asynchronously with the input frame frequency. Therefore, in the end, both frame buffers can be updated only at the frame scan rate without being affected by the dispatch asynchronous with the input (line scan cycle of the flat panel).

On the other hand, under the above conditions, the prescribed refresh period of the RDRAM is 1024 rows / 16 ms.
To protect this, the input frame with the above configuration must be at least 1/1
It can be seen that 6 ms = 62.5 Hz or more is sufficient.
Therefore, it is possible to deal with the 75 MHz of this embodiment in a refresh-free manner without increasing the memory bandwidth.

However, when the input frame frequency is lower than the refresh frequency, the refresh regulation cannot be satisfied by the address conversion as shown in FIG. Therefore, in the second embodiment, a method for realizing the refresh-free operation even under the above conditions is proposed below.

First, the following example is considered as another system condition. 1) Host input unit: display resolution XGA mode (1024 × 768, 60 Hz) 2) Flat panel: display resolution (1280 ×
1024) Number of display colors (12 bits / pixel) 3) Frame memory used: 8M (× 32) SGRAM.

First, under this condition, since the input frame frequency has not reached 62.5 Hz, the first
It is impossible to realize refresh-free with the configuration of the embodiment.

FIG. 12 is a diagram for explaining address mapping according to the second embodiment. FIG. 12 shows an address mapping that realizes refresh-free even under the above conditions.

In the memory physical address model shown in FIG.
It is characterized in that a 1-line / 8-row address conversion method is used. In other words, one burst transfer of 32 columns is filled in the column address direction (because burst transfer cannot be performed across row addresses), and the next transfer is filled in the row address direction incremented by one. In this example, data for one line is allocated to 8 rows (× 32 columns). With this configuration, the scan of the frame memory flows in the 69 scan directions at the frame rate. In the configuration of FIG. 9, only one row can be accessed in one line scan time.
In the configuration shown in FIG. 12, it is possible to access eight rows in one line scan time.

That is, even if the input frame frequency is reduced to ８ times (62.5 Hz / 8 = 7.8 Hz) as compared with the method of FIG.
Data retention is guaranteed only by accessing the frame memory by raster scanning.

The transitions 66, 67, and 68 have the same row address regularity as in the first embodiment, so that equivalent performance is maintained.

From the above, the system performance is improved by the address conversion method of the second embodiment,
In addition, refresh-free memory control system can be constructed with a wide degree of freedom even if system conditions (input conditions / connection panel conditions, etc.) change.

FIG. 13 is a diagram for explaining an address conversion process according to the second embodiment. As shown in FIG.
In the conversion method according to the second embodiment, the logical address LADD
If the configuration of [18: 0] is LADD [18] ... chip address LADD [17] ... bank address LADD [16: 8] ... row address LADD [7: 0] ... column address, the physical address 43MADD [18: 0] ] Is MADD [18] ← LADD [17] MADD [17:15] ← LADD [7: 5] MADD [14] ← LADD [18] (Read: 1 / Write: 0) MADD [13: 5] ← LADD [16: 8] MADD [4: 0] ← LADD [4: 0] By performing such address conversion by the address conversion circuit 40, the address mapping as shown in FIG. 14 is realized. In this case, a cache hit does not occur, but the overhead for the refresh cycle is reduced by eliminating the need for a refresh cycle.

As described above, RADD and WADD designating a column group (32 columns) at the same row address number on different chips correspond to the address conversion circuit 40.
Is converted to an address indicating an adjacent column group in the same row address number on the same chip. Then, R adjacent to each of the above RADD and WADD
ADD and WADD are converted into addresses indicating adjacent column groups in the row address number next to the row address. As a result, eight rows are accessed while accessing 256 columns. As described above, according to the second embodiment, with respect to the memory refresh, the address conversion for optimizing the physical address configuration of the memory is performed such that the access rate to the row address of the frame memory exceeds the refresh rate of the memory. Therefore, refresh-free of the memory is realized, and the system can be configured with a minimum memory bandwidth.

[Third Embodiment] The first and second embodiments are described above.
In the embodiment, a method has been proposed in which the overhead of the access time to the frame memory 4 is reduced by performing address conversion. These embodiments are solutions when the frame memory 4 performs only non-interleaved transfer. Therefore, in the third embodiment, the frame memory 4
A method for improving the system performance in the case of supporting interleave transfer will be described.

In the frame memory of the protocol system compatible with interleaving, 1) the memory chip currently accessed for data transfer is physically different from the memory chip to be accessed for the next data transfer. 2) A command packet (including address information) for the next transfer can be inserted under the condition that the currently accessed memory and the bank of the memory to be accessed next are physically different. Is generally known.

Specifically, at the time of the mishit shown in FIGS. 6 and 8, if the next transfer address can be received before the current access, the command packet for the next transfer is transmitted to the TRMHA (49). ) Or TWMHA
It can be inserted into the cache miss time of (54). By inserting such a command packet,
The next transfer can always be treated as a cache hit.

Based on the above, the address conversion by the address conversion circuit 40 of the third embodiment is as shown in FIG. FIG. 14 is a diagram illustrating address mapping for realizing refresh-free according to the third embodiment. This corresponds to the refresh-free operation described in the second embodiment and address conversion incorporating the interleaving condition 1).

Hereinafter, a control method for realizing interleaving will be supplementarily described with reference to FIG.

Since read / write is a regular raster scan, the next address can be easily predicted in advance. Therefore, every time the data transfer is completed, each pre-latch address is generated by an address counter in the write frame address generation circuit 15 and the read frame address generation circuit 16 (FIG. 1).
Can be generated. On the other hand, since the dispatch occurs randomly, the above regularity cannot be used.

Therefore, by using the motion detecting section 2 shown in FIG. 1, the random display line address 11 is predicted in advance, and the dispatch line address generation circuit 17 generates a pre-latch address for dispatch based on this. . By generating the pre-latch pulse 75 at 17 in FIG. 1 in the same manner as described above, notification of the next address to the frame memory 4 is realized. The motion detector 2 detects a line that has moved, and generates a dispatch address based on the detection result. Therefore, the dispatch address can be predicted in advance by referring to this result.

In FIG. 15, in a series of transitions of addresses at the time of interleaving, at the timing indicated by 76, the transfer address of the read data transfer is RADD # 0, and WADD # 0 is the pre-latch address for interleaving. At the timing indicated by 77, the transfer address of the write data transfer is WADD # 0, and DADD # 0 becomes the interleave pre-latch address. Further, at the timing indicated by 78, the transfer address of the dispatch data transfer is DADD # 0, and in this case, the pre-latch address is not generated because of the non-interleaving due to the physical configuration of the memory described above.

FIG. 16 is a block diagram showing the internal configuration of the bus arbitration unit 9 according to the third embodiment. Here, in order to realize the interleaved address pre-latch as in the present embodiment, the bus arbitration circuit 37 is provided with a function of simultaneously performing the bus arbitration of the current transfer and the bus arbitration of the next transfer. The address of the memory transfer request determined to have a high priority by the bus arbitration circuit 37 is selected by the address selector 39 according to the high priority address selection signal 81, and is provided to the address conversion circuit 40 as the logical address 42 of the current transfer. You. The address of the memory transfer request determined to have a low priority is selected by the address selector 79 according to the low priority address selection signal 82, and the pre-latch for interleaving to the frame memory 4 during the address period during the current transfer is selected. The address is output to the address conversion circuit 40 as the address 80. Note that the address conversion circuit 40 performs address mapping as described with reference to FIG. 14 to realize refresh-free operation.

In the interleave access as described above, transitions 70 and 71 of R → W and W → D in FIG. 14 are transfer transitions (interleaves) between different chips, and a cache hit is caused by the above-described pre-latch address.
The transition 72 from D to R is a cache miss due to a transfer transition between the same chips (non-interleave). Therefore, the total overhead of the transfer access time within one segment division time (TSEG) is (TRMHA (49) -TRHA (46)) (15).

The performance with and without the above address conversion is as follows: Equation (11) -Equation (15) = (TRMHA (49) -TRHA (46)) + TMWHA (16) per segment time. Further, when converted per frame in the above example, the system performance can be improved by the formula (16) × (the number of segments) × (the number of lines) = 8 cycles × 8 × 1024 = 65536 cycles.

This means that a system performance improvement of 32768/65536 = 2 times as large as that in the case of non-interleave is obtained.

FIG. 17 is a diagram for explaining an address conversion process according to the third embodiment. As shown in FIG.
In the address conversion method according to the third embodiment, each bit configuration of the logical address LADD [18: 0] is represented by LADD [18]... Chip address LADD [17]... Bank address LADD [16: 8]. 7: 0] ... column address, the physical address MADD [18: 0] becomes MADD [18:17] ← LADD [18:17] MADD [16: 8] ← LADD [13: 5] MADD [ 7: 5] ← LADD [16:14] MADD [4: 0] ← LADD [4: 0] By such address conversion, as in the second embodiment, eight rows can be accessed in one line scan time, and refresh-free operation is realized.

As described above, according to the third embodiment,
By performing access prediction using a motion detection unit in advance for random access, the cache hit rate in the memory interleave method is improved. For this reason, the system can be configured with a minimum memory bandwidth.

[Fourth Embodiment] In the fourth embodiment,
The address conversion method at the time of non-interleave described in the second embodiment (FIGS. 4 and 12) and the address conversion method at the time of interleave described in the third embodiment (FIGS. 14 and 16) We propose a method of switching and using according to the type.

FIG. 18 is a block diagram showing a detailed configuration of the address conversion circuit according to the fourth embodiment. In FIG. 18, the microcomputer 83 detects the connection memory information 84 of the frame memory 4 by reading the unique device ID of the frame memory 4 at the time of initializing, and determines whether or not interleaving is supported. The switching switch 87 selects the output physical address from the non-interleaving address conversion circuit 85 if interleaving is not supported, and selects the output physical address from the interleaving address conversion circuit 86 if interleaving is supported.

As described above, by allowing the microcomputer to detect the connection memory information and to select the optimum address conversion method, it is possible to flexibly cope with the case where memories having different specifications are configured.

As described above, in accessing the frame memory provided at the interface between the host device and the flat panel display, the address conversion to the frame memory having the capacity of two frames is performed.
In the case of a non-interleaved memory, optimization is performed according to the regularity of raster scanning (first and second embodiments), and in the case of an interleaved memory, optimization is performed by prior access prediction using the motion detection unit 9. (Third Embodiment), and further, when the frame memory is a DRAM, by optimizing so that accesses exceeding the refresh rate of the memory occur continuously (second and third embodiments). Mode), the following effects can be obtained.

(1) In a frame memory used for an image in which random access occurs, the cache hit rate can be increased only by adding a low-cost circuit, and as a result, the performance of the entire system can be improved. it can.

(2) The motion detection circuit 9 can be used as a circuit for random access prediction, and the circuit scale is increased and the cost is increased by adding a large-scale prediction circuit only for random access prediction. Can be suppressed.

(3) It is not necessary to increase an unnecessary memory bandwidth only for refreshing, and the bit cost of the DRAM used for the frame memory can be reduced.

(4) It is possible to suppress an increase in the capacity of the buffer memory for temporarily saving other data transfer for performing memory access during the refresh period.

The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), and can be applied to a single device (for example, a copier, a facsimile) Device).

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided on a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0100]

As described above, according to the present invention,
In the access to the memory, by performing an appropriate address conversion process, the cache hit rate is improved, and as a result, the throughput of the system is improved. Also, refresh-free operation in a wide range of frame rates is realized by appropriate address conversion.

[0101]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a display device system according to a first embodiment.

FIG. 2 is a timing chart showing an operation in each access of write / read / dispatch.

FIG. 3 shows reading, writing,
FIG. 3 is a diagram illustrating transfer timing of dispatch data.

FIG. 4 is a block diagram showing an internal configuration of a bus arbitration unit 9 according to the embodiment.

FIG. 5 is a diagram showing a data transfer cycle time when a cache hit occurs during read data transfer.

FIG. 6 is a diagram showing a data transfer cycle time when a cache miss occurs during read data transfer.

FIG. 7 is a diagram showing a data transfer cycle time when a cache hit occurs during write data transfer.

FIG. 8 is a diagram illustrating a data transfer cycle time when a cache miss occurs during write data transfer.

FIG. 9 is a diagram showing general address mapping in a double buffer configuration.

FIG. 10 is a diagram illustrating the same row address mapping according to the first embodiment.

FIG. 11 is an address translation circuit 40 according to the first embodiment;
FIG. 4 is a diagram for explaining an address conversion process according to FIG.

FIG. 12 shows an address mapping for realizing a refresh-free operation even under the above conditions.

FIG. 13 is a diagram illustrating an address conversion process according to the second embodiment.

FIG. 14 is a diagram illustrating address mapping for realizing refresh-free according to the third embodiment.

FIG. 15 is a diagram illustrating access timing to a frame memory according to the third embodiment.

FIG. 16 is a block diagram showing an internal configuration of a bus arbitration unit 9 according to the third embodiment.

FIG. 17 is a diagram illustrating an address conversion process according to the third embodiment.

FIG. 18 is a block diagram illustrating a detailed configuration of an address conversion circuit according to a fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host apparatus 2 Motion detection part 3 Memory control part 4 Frame memory 5 Display control part 6 Flat display 7 Write controller 8 Read controller 9 Bus arbitration part 10 Display controller 12 Write FIFO 13 Read FIFO 14 Dispatch FIFO 15 Write frame address generation circuit 16 Frame address generation circuit for read 17 Line address generation circuit for dispatch 27 Refresh circuit

Claims (12)

[Claims] 1. A memory control device for accessing a memory by a row address and a column address, wherein the memory control device comprises a predetermined number of identical column address groups which are continuous on two different row addresses having a predetermined positional relationship. Conversion means for converting one logical address group into two real address groups consisting of two non-overlapping predetermined number of continuous column address groups on the same row address; A memory control device, comprising: an access execution unit that provides the address as an address to the conversion unit and executes an access using a real address obtained as a conversion result. 2. The memory control device according to claim 1, wherein the two different row addresses having the predetermined positional relationship indicate the same row address in each of two different frame memories. 3. The memory control device according to claim 1, wherein the predetermined number of column address groups form a segment obtained by dividing one line of image data into a plurality of transfer units. 4. The conversion means converts two logical address groups indicating two segments at the same column position on two different row addresses having a predetermined positional relationship into two adjacent address groups on the same row address. 4. The memory control device according to claim 3, wherein conversion is performed into two real address groups indicating one segment. 5. The memory control device according to claim 4, wherein said conversion unit further arranges adjacent segments on the same row address indicated by the logical address group on different row addresses. . 6. The memory control device according to claim 1, wherein said memory has a sense amplifier cache for row data. 7. A memory control device for accessing a memory by a row address and a column address, including a group of a predetermined number of continuous column addresses on the same row address, and dividing one line of image data into a plurality of transfer units. Input means for inputting a logical address group representing the segment, and converting means for converting two adjacent segments on one row address on the logical address into real addresses arranged in segments on different row addresses; A memory control device comprising: an access execution unit that executes an access using a real address obtained as a result of conversion by the conversion unit. 8. One frame of image data can be stored.
A memory control device for controlling access to two frame memories having sense amplifier caches for row data, wherein said memory control device includes a segment obtained by dividing one line of image data into a plurality of transfer units in a predetermined segment order. Input means for inputting image data; first reading means for reading image data of a previous frame corresponding to a segment input by the input means from a first frame memory; and image data input by the input means in the second frame. Writing means for writing to a corresponding segment position in a memory; detection for performing motion detection by comparing the image data of the previous frame read by the first reading means with the image data of the current frame input by the input means Means for storing image data from the first frame memory based on the detection result by the detection means. A second read means for reading out the first read means, the write means, and the second read means, in the process of sequentially repeating the read operation, including a row address generated in a next access based on a detection result by the detection means. A memory control device, comprising: issuing means for issuing a command packet. 9. In the process of sequentially repeating the first reading means, the writing means, and the second reading means, the issuing means generates a next access based on the predetermined segment order and the detection result. 9. A command packet including a row address to be issued is issued.
3. The memory control device according to 1. 10. The issuing means, wherein: the first reading means;
10. The memory control device according to claim 9, wherein, in the process of sequentially repeating the writing unit and the second reading unit, the command packet is issued when interleaved access occurs. 11. A memory control method for accessing a memory by a row address and a column address, comprising a predetermined number of identical column address groups that are continuous on two different row addresses having a predetermined positional relationship. Converting two logical address groups into two real address groups consisting of two non-overlapping predetermined number of continuous column address groups on the same row address, and an address included in the access command. A logical address to the conversion step, and performing an access using the real address obtained as a result of the conversion. 12. A storage medium for storing a control program for realizing a memory control for accessing a memory by a row address and a column address by a computer, the control program comprising two different rows having a predetermined positional relationship. Two logical address groups composed of a predetermined number of identical column address groups that are consecutive on an address are replaced with two real address groups composed of two of the predetermined number of continuous column address groups that do not overlap on the same row address. A code of a conversion step of converting the address into a group of addresses, and a code of an access execution step of providing an address included in the access command as a logical address to the conversion step and executing an access using a real address obtained as a conversion result. A storage medium comprising: