JP2000013754A - Teletext broadcast data extraction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract character data without the intervention of a CPU and to reduce a cost due to the reduction of a circuit scale by first sampling the character data with a clock for character data and next slicing it with average value (AVL 1) that is calculated from MAX value and MIN value of character data of a pulse (CRIG) part which shows a CRI part of the character data. SOLUTION: A CRIG is a pulse that shows a CRI part of a teletext signal 1 and is generated by a timing pulse generation circuit 11. The maximum value and minimum value of the signal 1 in a '1' period of the CRIG are calculated by a detection circuit 1:5 of CRI part maximum value/minimum value/slice value. A data extraction circuit 4 slices teletext data with a slice value (AVL 1) that is calculated by the circuit 1:5 after sampling it with a clock generated by a clock generation circuit 12 and outputs it as binarized character data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data extracting circuit used in a data receiving circuit for teletext broadcasting of a television video signal.

[0002]

2. Description of the Related Art FIG. 17 shows a conventional example of a data extracting circuit in a teletext broadcast receiving circuit. In this figure,
Reference numeral 91 denotes an input terminal of the character multiplex signal 1, reference numeral 92 denotes an AD conversion circuit for performing AD conversion of the character multiplex signal 1 at a frequency n times the transmission rate of the character multiplex signal, reference numeral 93 denotes an input terminal of a clock used for extracting character data, and reference numeral 94. Is a sync separation circuit for generating horizontal and vertical synchronizing signals for generating a reference pulse used for extracting character multiplexed data, and 102 is an output of the sync separation circuit 94 and information of the timing register 98 when extracting character multiplexed data. , A timing generation circuit for generating a character data extraction reference pulse and a character data clock based on the multiplexed signal 1, a transversal filter (hereinafter referred to as TF) 9 for removing a ghost from the character multiplexed signal 1, 9
Reference numeral 6 denotes an input register for recording the digital character multiplexed signal 1 after the AD conversion and outputting data to the CPU 105 at the time of waveform equalization. Reference numeral 99 denotes a digital video signal after waveform equalization and data to the CPU 105 at the time of waveform equalization. An output register for outputting 105, a CPU for taking in data of the input register 96 and the output register 99 at the time of waveform equalization and calculating a tap value to be set in the tap register 99 for software processing, and 99 for recording the tap value calculated by the CPU 105 Tap register, 101 is a correlation phase detection circuit for calculating the correlation and phase relationship between the reference pulse generated by the timing generation circuit and the character multiplexed data after waveform equalization, and 100 is a waveform based on the detection result of the correlation phase detection circuit 101 A data interpolation circuit that interpolates the data after equalization so that the data matches the phase of the reference pulse. Character data output terminal for outputting the interpolated character data, 104 a timing generation circuit 102
Is a character data clock output terminal for outputting the character data clock generated in step (1).

In the CPU 105, the least squares error method (MS
An algorithm such as E) performs a correlation operation between the value of the input register 165 and the error signal detected from the value of the output register 167, and corrects the tap value based on the result. The tap value thus calculated is written to the tap register 97, and the TF 95 performs waveform equalization. Here, the principle of the timing generation circuit will be described with reference to FIG.

The input character multiplexed signal 1 is written to an input register after A / D conversion. At this time, the writing is controlled based on a pulse (CRIG) indicating the CRI portion of the character multiplexed data.

The CPU 105 has an ideal waveform pattern of the CRI section, and T1 (distance from the falling edge of the horizontal synchronizing signal to the rising edge of the CRGI) in FIG. 11 so that the CPU waveform matches the waveform of the input register. And outputs it to the timing register 98 and the timing generation circuit 102.

Further, in the timing generation circuit 102,
When the correlation between the waveform-equalized data and the waveform generated by the timing recovery circuit is generated from the CRIG, a correlation calculation pulse is generated and a correlation operation is performed.
The phase difference between the correlation calculation pulse and the data after waveform equalization is calculated, and data interpolation is performed by the data interpolation circuit 103 so that the data is shifted by the phase difference.

[0007]

In the conventional example, since waveform equalization and timing register control are performed by software processing by a CPU, a CPU and a memory are required to extract character data, so that a system becomes large and cost increases. There is a problem of becoming.

[0008]

In order to solve the above-mentioned problem, the present invention provides a first aspect of the present invention in which CRI of character data is used.
A pulse indicating the part is generated (this pulse is hereinafter referred to as CRIG
It is written. ), MAX value of character data in CRIG part and M
Calculate the IN value.

The calculation of the MIN value and the MAX value is based on the CRIG
Is divided into two equal periods, and the average value of the MAX value and the MIN value calculated for each is calculated. Further, the average value (AVL1) is calculated from the MAX value and the MIN value thus calculated.

The character data clock is a center 6 clock period (CR) of the CRI section of the CRIG with respect to each of 10 phase clocks obtained by shifting the phase of (8/10) fsc generated from 8 fsc of burst lock by 8 fsc.
In IG2), the character multiplexed data is added, and the clock having the maximum value is used as the clock for character data. To extract the character data, the character data is first sampled by the character data clock, and then sliced by the AVCL1. With such a configuration, a character data extracting circuit that does not require a CPU is provided.

[0011] As a second invention, first, the above-mentioned CRI
In the latter half of the half of G, the averaging of character data (slice value 2) is calculated. Next, the character data clock generation method according to the first invention applies a CRIG CR to each of the five-phase clocks obtained by shifting the phase of (8/5) fsc generated by the burst lock 8 fsc by 8 fsc.
By adding the absolute value of the data obtained by subtracting the above-described slice value 2 from the character multiplexed data in the center 6 clock period (CRIG2) of the I section, and making the clock the maximum value,
Provided is a character data extracting circuit capable of doubling the detection accuracy and improving the accuracy of character data clock generation.

A third aspect of the present invention relates to the first aspect and the second aspect.
In the character data slice of the present invention, data smaller than the above slice value 2 for character data before slicing is replaced with a smaller value (for example, 0, etc.). The present invention provides a character data extracting circuit capable of improving the receiving performance of a character.

[0013] Further, as a fourth invention, the first invention, the second invention,
In the third and third aspects of the present invention, the CRIG is detected by detecting the phase of the signal from which character data has been extracted and the phase of the CRIG, and shifting the CRIG to an optimal position (hereinafter, this pulse is referred to as C
Notated as RIG3. Thus, there is provided a character data extracting circuit capable of generating a more optimal character data clock and extracting data.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a text multiplex broadcast data extracting circuit according to the present invention. (Embodiment 1) FIG. 1 is a block diagram of a teletext broadcast data extracting circuit according to Embodiment 1.

In FIG. 1, reference numeral 1 denotes a character multiplexed signal 1 input terminal, 2 denotes an AD conversion circuit for converting the character multiplexed signal 1 into digital data, and 3 denotes a CRI unit maximum / minimum / slice value detection circuit 1. The delay circuits 1 and 4 for outputting the character multiplexed signal 2 whose data has been delayed by the detection time are provided by the character multiplexed signal 2.
A data extraction circuit that extracts character data from
Reference numeral 5 denotes a data extraction circuit for calculating a slice value used for slicing character data. CRI unit maximum / minimum / slice value detection circuits 1 and 6 are used to generate a reference pulse used for extracting character data. An input terminal for a horizontal synchronizing signal, 7 is an input terminal for a vertical synchronizing signal used to generate a vertical reference pulse of character data, and 8 is a CR
A detection control signal input terminal for controlling the detection timing by the maximum value / minimum value / slice value detection circuit 1 of the I part, and 9 is a burst locked 8f used for extracting character data.
A clock input terminal for inputting an SC clock, 10 is 8
From the clock of fsc, the clock of (8/10) fsc is changed to 8
a frequency dividing circuit for generating a clock whose phase is shifted by fsc; a timing pulse generating circuit for generating a pulse for gating a portion indicating a CRI unit;
A clock generation circuit for selecting a clock suitable for extracting character data from a 10-phase clock of 0, a character data output signal output terminal 13 for outputting a signal extracted from character data, an output terminal 14 for a clock for character data, 1
Reference numeral 5 denotes a clock control input terminal for controlling a pulse width for detecting the phase of the CRI unit when generating a clock.

The operation of the present invention will be described below with reference to FIGS. FIG. 11 is a timing chart illustrating the basic principle of the present invention. In FIG. 11, T1 indicates the time from the falling edge of the horizontal synchronizing signal to the CRI part of the text multiplex signal, and is about 9 μS in the text multiplex broadcasting.

CRIG is a pulse indicating the CRI portion of the character multiplex signal (the period of "1" is the CRI portion).
Reference numeral 2 denotes a pulse that sets “1” to a 6-clock period of the center of the CRI section of the character multiplexed signal 2.

These pulses are generated by a timing pulse generation circuit 11. FIG. 9 shows an example of the timing pulse generation circuit.

In FIG. 9, reference numeral 73 denotes a vertical synchronizing pulse input terminal, and reference numeral 80 denotes a vertical pulse period, which is a pulse which sets a period in which character multiplexed data is superimposed to "1" (hereinafter referred to as TXG). The counters 3 and 74, which are generated in conjunction with the terminal, input a clock of 8 fsc, 75
Is a terminal for inputting a horizontal synchronizing pulse, and 78 is a pulse CRIG indicating the CRI portion of the character multiplex signal (the period of "1" is CR
1 and 82 are output terminals for outputting CRGI, and 83 is a C terminal.
A differentiation circuit 84 for differentiating the rising edge of the RIG has a character multiplex signal C 84 for generating a character data clock.
Counters 2 and 86 which generate a pulse in which the 6 clock periods at the center of the RI section are set to “1” in conjunction with the decoding circuit 85 are output terminals for outputting CRIG2.

In the present invention, T1 in FIG.
Set the decoding circuit 1 of FIG.
An IG is generated, and the maximum value and the minimum value of the character multiplexed signal 1 during the period when the CRIG pulse is "1" are calculated by the CRI part maximum value / minimum value / slice value detection circuit 1.

FIG. 4 shows an example of a circuit for detecting the maximum value / minimum value / slice value of the CRI section. In FIG. 4, 19 is a character multiplexed data input terminal, 28 is a terminal for inputting a clock of 8 fsc, 29 is the above CRIG input terminal, 30 is a timing control signal input terminal, and 33 is an 8 fsc input terminal only during the period when CRIG is "1". The counter 35 counts up by a clock. The output of the counter 33 is compared with the value of the timing control signal.
38 is an AND circuit which takes an AND logic of CRIG and a signal obtained by inverting the output of the comparator 35;
Is a maximum value calculation circuit for calculating the maximum value of the character multiplexed data in the period when the output of the comparator 35 is "1";
A maximum value calculation circuit for calculating the maximum value of the character multiplexed data during the period in which the output of the circuit 38 is "1". The output of the comparator 35 is a minimum value calculation for calculating the minimum value of the character multiplexed data in the period of "1". A circuit 21 for calculating the minimum value of the character multiplexed data during the period when the output of the AND circuit 38 is "1"; and 24, the output of the maximum value calculation circuit 20, the output of the maximum value calculation circuit 21, and the minimum value calculation An averaging circuit that calculates the averaging of the output of the circuit 22 and the output of the minimum value calculating circuit 23 and outputs the result as a slice value, 26 is a slice value output terminal, and 25 is a terminal in the period when the output of the comparator 35 is “1”. An averaging circuit 251 for averaging data is an output terminal for a slice value 2 output from the averaging circuit 25.

In the present invention, in detecting the maximum value / minimum value / slice value of the CRI unit, the timing control signal is set to the pulse width of the CRI unit / 2, and the first half of the period when CRIG is "1" (the output of the AND circuit 38). ) And the latter half (the output of the comparator 35), the maximum value and the minimum value are calculated, and the averaging of the maximum value and the minimum value is calculated so that erroneous detection of the slice value due to noise is suppressed.

FIG. 5 shows an example of the data extracting circuit 4. In the data extracting circuit 4, as shown in FIG. 5, the character multiplexed data is sampled by the clock generated by the clock generating circuit 12, and then the slice value calculated by the CRI part maximum value / minimum value / slice value detection circuit 1 is obtained. And binarized to output as character data output.

If the text multiplexed data is sampled with the clock generated by the clock generation circuit 12 after the binarization, the distortion of the data becomes large. Therefore, the configuration shown in FIG. 5 improves the reception performance of the text multiplex broadcast.

FIG. 7 shows an example of the clock generation circuit. FIG. 12 shows the principle. 8f generated by frequency divider
From the clock of sc, the clock of (8/10) fsc is changed to 8f
10-phase clocks CLK1, C shifted in phase by sc
LK2 CLK9 and CLK10 are input to the clock generation circuit, and the character multiplexed signal 2 is sampled and added by each clock as shown in FIG. 12 while CRIG2 is "1".

The clock having the maximum addition result is used as a clock for character data. Also in this addition, in order to suppress erroneous detection due to noise, the period of "1" of CRIG2 is divided into the first half and the second half by a clock control signal, and a maximum value is calculated for each of the first half and the average thereof, and the average is calculated. Select the clock that has the addition result closest to.

With the above-described circuit configuration, it is possible to extract text multiplex broadcast data only by hardware without using a CPU.

(Embodiment 2) FIG. 2 is a block diagram of a teletext broadcast data extracting circuit according to Embodiment 2.

In FIG. 2, reference numeral 1 denotes a character multiplexed signal 1 input terminal, 2 denotes an AD conversion circuit for converting the character multiplexed signal 1 into digital data, and 3 denotes a CRI unit maximum / minimum / slice value detection circuit 1. The delay circuits 1 and 4 for outputting the character multiplexed signal 2 whose data has been delayed by the detection time are provided by the character multiplexed signal 2.
A data extraction circuit that extracts character data from
Reference numeral 5 denotes a slice value used for slicing character data in a data extraction circuit and a slice value 2 used for clock generation.
The CRI unit maximum value / minimum value / slice value detection circuits 1 and 6 are used to input a horizontal synchronizing signal used to generate a reference pulse used for extracting character data, and 7 is a character data vertical direction. An input terminal of a vertical synchronizing signal used to generate a reference pulse, 8 is a detection control signal input terminal for controlling the detection timing by the CRI section maximum value / minimum value / slice value detection circuit 1, and 9 is a character data input terminal. A clock input terminal for inputting a burst locked 8 fsc clock used for sampling, a frequency divider circuit 10 for generating a clock whose phase is shifted by 8 fsc from a (8/5) fsc clock from the 8 fsc clock, 11 CRI
A timing pulse generating circuit for generating a pulse for gating a portion indicating a portion, a clock generating circuit 12 for selecting a clock suitable for extracting character data from the five-phase clock of the frequency dividing circuit 10, and a extracting circuit 13 for extracting character data. A character data output signal output terminal for outputting a signal, 14 is a character data clock output terminal, and 15 is a clock control input terminal for controlling a pulse width for detecting the phase of the CRI unit when generating a clock.

The second embodiment improves the performance of the clock generation circuit of the first embodiment. FIG. 8 shows the second embodiment.
1 shows an example of the clock generation circuit. FIG. 13 shows the principle.

Five-phase clocks CLK1, CLK2, CLK3, which are obtained by shifting the phase of (8/5) fsc by 8 fsc from the 8 fsc clock generated by the frequency dividing circuit.
CLK4 and CLK5 are input to the clock generation circuit,
While RIG2 is "1", the data input signals are sampled and added at each clock as shown in FIG.

FIG. 8 is different from FIG. 7 in that a circuit for subtracting the slice value 2 from the clock data is added. By calculating the absolute value of the circuit, the result is as shown in FIG. 13, which is twice as large as that of FIG. Since sampling becomes possible, the accuracy of clock selection can be doubled.

Here, similarly to the first embodiment, the clock having the maximum addition result is used as the clock for character data. Also in this addition, in order to suppress erroneous detection due to noise, the period of "1" of CRIG2 is divided into the first half and the second half by a clock control signal, and a maximum value is calculated for each of the first half and the average thereof, and the average is calculated. Select the clock that has the addition result closest to.

The slice value 2 from the maximum / minimum value / slice value detection circuit 1 of the CRI section needs to be the center value of the CRI section. Since the average value is calculated by the calculation, the value becomes smaller than the center value depending on the state of character data input and the phase of CRIG, and there is a problem that an optimum clock cannot be selected.

Therefore, in the CRI section maximum value / minimum value / slice value detection circuit 1, the CRI section is provided separately from the slice value.
The slice value 2 obtained by calculating the averaging of the character data is output only in the latter half of G.

(Third Embodiment) In the third embodiment, the reception performance of teletext broadcasting is improved by using the data extracting circuits of the first and second embodiments as shown in FIGS.

In FIG. 6, 40 is a character multiplexed signal 2 input terminal, 441 is a slice value 2 input terminal, and 46 is a character multiplexed signal 2 by comparing the character multiplexed signal 2 with the above slice value 2.
The comparator 45 outputs 1 when is larger, and 45 is a comparator 46
If the output is 1 in response to the output of
A switch that outputs 0 when it is 0, a flip-flop 47 that samples the output of this switch with a clock for character data, and 48 that compares the output of the flip-flop 47 with the slice value and sets 0 if the slice value is larger than the slice value. Is a comparator for outputting the character data.
FIG. 14 is an explanatory diagram of the third embodiment. In FIG. 14, a character multiplexed signal 1 is a character multiplexed signal with a ghost,
As can be seen from the CRI section and the FC section, the waveform is such that the valley does not completely fall to the end. Here, if the CRIG is behind the CRI of the character data, there is no problem in slicing only with the slice value (slice value slice value 2), but if the CRIG phase comes before the CRI of the character data (slice). Value <slice value 2) In some cases, the slice level becomes too small and data of 0 is sliced with 1 to cause erroneous detection. Therefore, character data with a slice value of 2 or less used for clock generation is set to 0.
By replacing with, the character multiplex receiving performance can be improved.

(Embodiment 4) FIG. 3 is a block diagram of a teletext broadcast data extracting circuit according to Embodiment 4.

In FIG. 3, reference numeral 1 denotes a character multiplexed signal 1 input terminal, 2 denotes an AD conversion circuit for converting the character multiplexed signal 1 into digital data, and 3 denotes a CRI section maximum value / minimum value / slice value detection circuit 1. The delay circuits 1 and 4 for outputting the character multiplexed signal 2 whose data has been delayed by the detection time are provided by the character multiplexed signal 2.
A data extraction circuit that extracts character data from
Reference numeral 5 denotes a slice value used for slicing character data and a slice value 2 used for clock generation in a data extraction circuit.
The CRI unit maximum value / minimum value / slice value detection circuits 1 and 6 are used to input a horizontal synchronizing signal used to generate a reference pulse used for extracting character data, and 7 is a character data vertical direction. An input terminal of a vertical synchronizing signal used to generate a reference pulse, 8 is a detection control signal input terminal for controlling the detection timing by the CRI section maximum value / minimum value / slice value detection circuit 1, and 9 is a character data input terminal. A clock input terminal for inputting a burst locked 8 fsc clock used for sampling, a frequency divider circuit 10 for generating a clock whose phase is shifted by 8 fsc from a (8/5) fsc clock from the 8 fsc clock, 11 CRI
A timing pulse generating circuit for generating a pulse for gating a portion indicating a portion, and a timing pulse generating circuit for optimizing the timing pulse by using an output signal of a data extracting circuit; A clock generation circuit for selecting a clock suitable for extracting character data from a character data output signal output terminal for outputting a signal extracted from character data;
Is an output terminal for a clock for character data, and 15 is a clock control input terminal for controlling a pulse width for detecting the phase of the CRI unit when generating the clock.

In the fourth embodiment, the first embodiment, the second embodiment,
The CRIG in the third embodiment is detected by detecting the phase of the signal from which character data has been extracted and the CRIG, and shifting the CRIG to an optimum position (hereinafter, this pulse is referred to as CRIG3).
It is written. ) To generate a more optimal clock for character data and extract data.

FIG. 10 shows an example of the timing pulse generation circuit according to the fourth embodiment. FIG. 15 is an explanatory diagram of the principle. In FIG. 10, reference numeral 73 denotes a vertical synchronization pulse input terminal, and reference numeral 80 denotes a vertical pulse period in which a period in which character multiplexed data is superimposed is set to "1" (hereinafter referred to as TXG) in conjunction with a decoding circuit 81. The counters 3 and 74 which are generated by a terminal for inputting a clock of 8 fsc, 75
Is a terminal for inputting a horizontal synchronizing pulse, and 78 is a pulse CRIG indicating the CRI portion of the character multiplex signal (the period of "1" is CR
1 and 82 are output terminals for outputting CRGI, and 83 is a C terminal.
A differentiation circuit 84 for differentiating the rising edge of the RIG has a character multiplex signal C 84 for generating a character data clock.
Counters 2 for generating a pulse in which the 6 clock periods at the center of the RI section are set to "1" in conjunction with the decoding circuit 85, 86 are output terminals for outputting CRIG2, and 76 are character data output signals of the data extraction circuit. A character data output signal input terminal for input, 77 is a timing control signal input terminal, 88 is a CRI using a character data output signal as a clock.
The counters 3 and 89 that count up during the G period
A flip-flop latches the output of the counter 3 at the falling edge of I, and a CRGI start position setting circuit 90 sets a CRIG start position in accordance with the output of the flip-flop.

In FIG. 15, CRIG3 is a CRIG pulse optimized by the above circuit.

In this case, when CRIG3 is "1",
When the character multiplexed signal 2 is counted as a clock, the count becomes 8.

FIG. 15 shows the respective count values when the phase relationship between the character multiplexed signal and CRIG3 changes from (A) to (G). From this figure, when the phase of CRIG3 is shifted from front to rear with respect to the character multiplexed data, the count value increases to 0, 1, 2, 3, 4, 5, 6, 7, 8, and 8, and the optimal position is set. Focusing on this change, which goes down to 8, 7, 7 after passing, the position of the CRIG is optimized. The CRI unit maximum value / minimum value / slice value detection circuit 1
It is considered that the performance is improved when the CRIG used in the above is slightly delayed from the CRIG3 because the minimum value is calculated and the portion before the CRI unit is not detected.

As a result, the calculation accuracy of the clock generation circuit and the calculation accuracy of the slice level are improved, and the reception performance of teletext broadcasting can be improved without the intervention of the CPU.

[0046]

According to the data multiplex broadcasting data extracting circuit according to the present invention, character data can be extracted without the intervention of a CPU, so that a CPU and a memory are not required as compared with the prior art, and the cost can be reduced by reducing the circuit scale. This has the effect of eliminating the need for software development.

In the present invention, the setting of the timing generation circuit and the clock frequency dividing circuit is made variable, so that the present invention can be applied not only to teletext broadcasting in Japan but also to terrestrial data broadcasting such as closed captioning and NABTS in North America. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a teletext broadcast data extracting circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a teletext broadcast data extracting circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a teletext broadcasting data extracting circuit according to a fourth embodiment of the present invention;

FIG. 4 is a block diagram of a CRI unit maximum / minimum / slice value detection circuit according to the present invention;

FIG. 5 is a block diagram of a data extracting circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a data extracting circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a clock generation circuit according to the first embodiment of the present invention.

FIG. 8 is a block diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram of a timing pulse generation circuit according to the first embodiment of the present invention.

FIG. 10 is a block diagram of a timing pulse generation circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing explanatory diagram in the first embodiment of the present invention.

FIG. 12 is an explanatory diagram of a clock generation circuit according to the first embodiment of the present invention.

FIG. 13 is an explanatory diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 14 is an explanatory diagram of a data extracting circuit according to a third embodiment of the present invention.

FIG. 15 is an explanatory diagram of a timing pulse generation circuit according to a fourth embodiment of the present invention.

FIG. 16 is an explanatory view of a conventional example.

FIG. 17 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Character multiplexed signal 1 input terminal 2 A / D converter 3 Delay circuit 1 4 Data extraction circuit 5 CRI section maximum / minimum / slice value detection circuit 1 6 Horizontal synchronization pulse input terminal 7 Vertical synchronization pulse input terminal 8 Detection control signal input Terminal 9 Burst lock 8 fsc input terminal 10 Divider circuit 11 Timing pulse generation circuit 12 Clock generation circuit 13 Character data output signal output terminal 14 Character data clock output signal output terminal 15 Clock control signal input terminal 19 Data signal input terminal 20 Maximum value detection Circuit 21 Maximum value detection circuit 22 Minimum value detection circuit 23 Minimum value detection circuit 24 Addition and averaging circuit 25 Addition and averaging circuit 251 Slice value 2 output terminal 26 Slice value output terminal 28 Clock input terminal 29 CRIG input terminal 30 Timing control signal input terminal 33 Counter 5 Comparator 38 AND circuit 40 Character multiplex signal 2 input terminal 43 Character data clock input terminal 44 Slice value input terminal 441 Slice value 2 input terminal 45 Switch 46 Comparator 47 Flip-flop 48 Comparator 49 Clock generation data 50 Character data output terminal 51 Clock data input terminal 52 Slice value input terminal 53 Subtractor 54 Absolute value circuit 551 Maximum value calculation circuit 552 Maximum value calculation circuit 55 Maximum value detection circuit 56 Counter 57 Comparator 58 Clock input terminal 59 CRIG2 input terminal 60 Clock control signal Input terminal 61 AND circuit 62 Maximum value detection circuit 63 Maximum value detection circuit 64 Maximum value detection circuit 65 Maximum value detection circuit 66 Clock selection circuit 67 CLK1 input terminal 68 CLK2 input terminal 69 CLK3 input terminal 70 CL 4 input terminal 71 CLK5 input terminal 691 CLK8 input terminal 701 CLK9 input terminal 711 CLK10 input terminal 72 Character data clock output terminal 73 Vertical synchronization pulse input terminal 74 Burst lock clock 8fsc input terminal 75 Horizontal synchronization pulse input terminal 78 Counter 1 79 Decoding circuit 1 80 Counter 3 81 Decoding circuit 3 82 CRIG output terminal 83 Differentiating circuit 84 Counter 2 85 Decoding circuit 2 86 CRIG2 output terminal 88 Counter 4 89 Flip-flop 90 CRIG start position setting circuit 91 Character multiplexed signal 1 input terminal 92 AD conversion circuit 93 Clock input terminal 94 Synchronization separation circuit 95 Transversal filter 96 Input register 97 Tap register 98 Timing register 99 Output register 100 Data Data interpolation circuit 101 correlation phase detection circuit 102 timing generation circuit 103 character data output signal output terminal 104 character data clock output signal 105 CPU

Claims (4)

[Claims] A character multiplexed signal 1 terminal; an AD conversion circuit for converting the character multiplexed signal 1 into digital data;
A CRI unit maximum value / minimum value / slice value detection circuit 1 which is connected to a conversion circuit, detects a maximum value and a minimum value of the CRI unit of the text multiplex broadcast, and calculates a slice value used when extracting character data; A delay circuit 1 that delays the output signal of the conversion circuit by the detection time of the maximum / minimum / slice value detection circuit 1 of the CRI unit and outputs a character multiplexed signal 2
And sampling the character multiplexed signal 2 with the character data clock output signal from the clock generation circuit and then slicing the character multiplexed data into binary values using the slice value calculated by the CRI part maximum value / minimum value / slice value detection circuit 1. A data extracting circuit for extracting character data by using a pulse (CRIG) which becomes "1" for a CRI section period of a character multiplexed signal used for extracting character data and a CRIG for which only the center 6 clock period is set to "1". C of multiplexed signal 2
A pulse (TX) in which the period in which the pulse (CRIG2) whose phase is adjusted to the RI section and the text multiplex broadcasting are superimposed is “1”
G), an input terminal of a horizontal synchronization signal used in the timing pulse generation circuit, an input terminal of a vertical synchronization signal used in the timing pulse generation circuit, and a maximum / minimum value of the CRI unit. / Slice value detection circuit 1 uses CRI to suppress erroneous detection due to noise.
A detection control signal input terminal for inputting a detection control signal used for detecting a maximum value / minimum value and calculating an average by dividing a G pulse into a first half and a second half of a CRI unit, and a detection control for controlling timing A signal input terminal, a clock input terminal for inputting a burst-locked 8 fsc clock used for extracting character data, and a 10-phase clock obtained by shifting the (8/10) fsc clock by 8 fsc from the 8 fsc clock And a 10-phase clock from the frequency dividing circuit, and calculate the maximum value of the character multiplexed signal 2 during the period when CRIG2 is "1" in each clock in each of the first half and the second half of CRIG2 The clock with the operation result closest to the average value is selected as a clock suitable for extracting character data, and is used as a character data clock output signal. A clock generation circuit for outputting, CR in order to suppress erroneous detection due to noise in the clock generation circuit
A clock control signal input terminal for inputting a clock control signal used for calculating an average by detecting the maximum value by dividing the IG2 pulse into the first half and the second half of the CRI section, and extracting character data from the character multiplex signal A character multiplex broadcast data extraction circuit, comprising: a character data output signal output terminal for outputting a signal; and an output terminal for outputting a character data clock generated by a clock generation circuit. 2. A character multiplexed signal 1 output terminal, an AD conversion circuit for converting the character multiplexed signal 1 into digital data,
A maximum value / minimum value of a CRI portion connected to a conversion circuit for detecting a maximum value and a minimum value of a CRI portion of a teletext broadcast and calculating a slice value used for extracting character data and a slice value 2 used for clock generation. / Slice value detection circuit 1
A delay circuit 1 for delaying the output signal of the AD conversion circuit by the detection time of the maximum value / minimum value / slice value detection circuit 1 of the CRI unit and outputting a character multiplexed signal 2; Data for sampling the character data clock output signal from the generation circuit and then extracting character data by slicing the character multiplexed data into two values using the slice value calculated by the CRI maximum / minimum value / slice value detection circuit 1. The sampling circuit and the pulse (CRIG) which becomes the CRI part period "1" of the character multiplex signal used in the character data sampling and the CRIG becomes "1" only in the center six clock period, and the phase becomes the CRI part of the character multiplex signal 2 (CRIG2) and a pulse (TXG) that sets the period in which teletext broadcasting is superimposed to “1”. Input terminal of the horizontal synchronizing signal used in the timing pulse generating circuit, input terminal of the vertical synchronizing signal used in the timing pulse generating circuit, and noise in the CRI section maximum value / minimum value / slice value detecting circuit 1. CRIG pulse to reduce erroneous detection due to
A detection control signal input terminal for inputting a detection control signal used for detecting the maximum value / minimum value and calculating the averaging by dividing into a first half and a second half of the RI unit, and a detection control signal input terminal for controlling timing And a clock input terminal for inputting a burst-locked 8 fsc clock used for extracting character data, and (8/5)
A frequency dividing circuit that generates a five-phase clock whose phase is shifted by 8 fsc from the fsc clock, and a five-phase clock from the frequency dividing circuit, and the character multiplexed signal 2 in a period in which CRIG2 is “1” with each clock After subtracting the slice value 2 calculated by the CRI part maximum value / minimum value / slice value detection circuit 1 from the above, the maximum value of the signal obtained by calculating the absolute value is CRIG2.
A clock generation circuit that calculates in each of the first half and the second half and selects the clock that is the operation result closest to the average value as a clock suitable for extracting character data and outputs it as a character data clock output signal, and noise in the clock generation circuit A clock control signal input terminal for inputting a clock control signal used for calculating the average by detecting the maximum value by dividing the CRIG2 pulse into the first half and the second half of the CRI section in order to suppress erroneous detection due to the multiplexing; A character data output signal output terminal for outputting a signal obtained by extracting character data from a signal, and an output terminal for outputting a character data clock generated by a clock generation circuit. circuit. 3. A character multiplexed signal 1 output terminal, an AD conversion circuit for converting the character multiplexed signal 1 into digital data,
A maximum value / minimum value of a CRI portion connected to a conversion circuit for detecting a maximum value and a minimum value of a CRI portion of a teletext broadcast and calculating a slice value used for extracting character data and a slice value 2 used for clock generation. / Slice value detection circuit 1
A delay circuit 1 for delaying the output signal of the AD conversion circuit by the detection time of the maximum value / minimum value / slice value detection circuit 1 of the CRI unit and outputting a character multiplexed signal 2; When the value of the slice value is smaller than the slice value 2 calculated by the partial maximum value / minimum value / slice value detection circuit 1, the data after the data is set to a value smaller than the slice value 2 (for example, 0 level) is output from the clock generation circuit. After sampling with the data clock output signal, the maximum value of the CRI part /
A data extraction circuit for extracting character data by slicing character multiplexed data into two values with a slice value calculated by the minimum value / slice value detection circuit 1, and a CRI section period of a character multiplexed signal used when extracting character data “1”
And the pulse (CRIG2) whose phase is matched to the CRI part of the text multiplex signal 2 and the period in which the text multiplex broadcast is superimposed is "1". A pulse (TXG) to be generated, an input terminal of a horizontal synchronization signal used in the timing pulse generation circuit, an input terminal of a vertical synchronization signal used in the timing pulse generation circuit, and a maximum value of the CRI unit In order to suppress erroneous detection due to noise in the / minimum value / slice value detection circuit 1, the CRIG pulse is divided into the first half and the second half of the CRI unit, and the maximum value / minimum value is detected and the detection control used when calculating the averaging is used. A detection control signal input terminal for inputting a signal, a detection control signal input terminal for controlling timing, and a burst buffer used for extracting character data. A clock input terminal for inputting a clock click has been 8 fsc, the clock of 8 fsc (8
/ 5) A frequency dividing circuit for generating a five-phase clock whose phase is shifted by 8 fsc from the fsc clock, and a five-phase clock from the frequency dividing circuit is input and each of the clocks generates a CRIG signal.
After subtracting the slice value 2 calculated by the CRI maximum / minimum / slice value detection circuit 1 from the character multiplexed signal 2 during the period when 2 is “1”, the maximum value of the signal obtained by performing the absolute value operation is calculated as the CRI.
A clock generation circuit that calculates the clock in the first half and the second half of G2 and has the operation result closest to the average value as a clock suitable for extracting character data, and outputs the selected clock as a character data clock output signal; and a clock generation circuit. A clock control signal input terminal for inputting a clock control signal used for calculating the average by detecting the maximum value by dividing the CRIG2 pulse into the first half and the second half of the CRI unit in order to suppress erroneous detection due to noise; Character multiplex broadcast data, comprising: a character data output signal output terminal for outputting a signal obtained by extracting character data from a multiplex signal; and an output terminal for outputting a character data clock generated by a clock generation circuit. Sampling circuit. 4. A character multiplexed signal 1 output terminal, an AD conversion circuit for converting the character multiplexed signal 1 into digital data,
A maximum value / minimum value of a CRI portion connected to a conversion circuit for detecting a maximum value and a minimum value of a CRI portion of a teletext broadcast and calculating a slice value used for extracting character data and a slice value 2 used for clock generation. / Slice value detection circuit 1
A delay circuit 1 for delaying the output signal of the AD conversion circuit by the detection time of the maximum value / minimum value / slice value detection circuit 1 of the CRI unit and outputting a character multiplexed signal 2; When the value is smaller than the slice value 2 calculated by the partial maximum value / minimum value / slice value detection circuit 1, the data after the data is set to a value smaller than the slice value (for example, 0 level) is the character data from the clock generation circuit. A data extracting circuit for extracting character data by slicing character multiplexed data into two values with a slice value calculated by the CRI part maximum value / minimum value / slice value detection circuit 1 after sampling with a clock output signal; A character data output signal from the data sampling circuit is a pulse (CRIG) which becomes "1" during the CRI section of the character multiplex signal used in sampling. Of the pulse (CRIG3) in which the pulse position of the CRIG is optimized by detecting the phase of the signal and a pulse in which the phase is adjusted to the CRI part of the character multiplexed signal 2 by setting only the center 6 clock period to "1" in the CRIG3 (CRIG2) and a timing pulse generation circuit for generating a pulse (TXG) that sets the period in which teletext broadcasting is superimposed to “1”; an input terminal of a horizontal synchronization signal used in the timing pulse generation circuit; The input terminal of the vertical synchronizing signal used in the generation circuit and the CRI unit maximum value / minimum value / slice value detection circuit 1 divide the CRIG pulse into the first half and the second half of the CRI unit in order to suppress erroneous detection due to noise. / Detection control signal input terminal for inputting a detection control signal to be used when detecting the minimum value and calculating the averaging, and performs timing control An output control signal input terminal, a clock input terminal for inputting a burst locked 8 fsc clock used for extracting character data, and a five phase phase shift of the (8/5) fsc clock from the 8 fsc clock by 8 fsc. And a five-phase clock from the frequency dividing circuit, and detecting the maximum value / minimum value / slice value of the CRI part from the character multiplexed signal 2 during the period when CRIG2 is "1" with each clock. The maximum value of the signal obtained by subtracting the slice value 2 calculated by the circuit 1 and then performing the absolute value calculation is calculated in each of the first half and the second half of the CRIG2, and the clock having the calculation result closest to the average value is suitable for extracting character data. Clock generation circuit that selects the selected clock and outputs it as a character data clock output signal, and erroneous detection due to noise in the clock generation circuit A clock control signal input terminal for inputting a clock control signal used for calculating the average by detecting the maximum value by dividing the CRIG2 pulse into the first half and the second half of the CRI part to suppress the signal, and character data from the character multiplex signal A character data output signal output terminal for outputting a signal extracted from the character data, and an output terminal for outputting a character data clock generated by a clock generation circuit.