JP2000012793A - Self-breaking semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely stop falsifying action on memories contents in a semiconductor integrated circuit. SOLUTION: A volatile memory 2, where very important confidential data are stored, and an initialization circuit 8 are provided to the same semiconductor board 9 with a semiconductor integrated circuit. A memory content stored in the volatile memory 2 is so set as to be held by an electric power which is fed from a power supply source 6. When the power supply source 6 is detached, a voltage change is detected by a voltage change detection circuit 5, and when the voltage change detection circuit 5 outputs the detected signals, a control circuit or element 4 is turned off, the volatile memory 2 is shut off from an electric power, and the volatile memory 2 is initialized by the initialization circuit 8 by the electric power stored in a backup capacitor 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device employing a semiconductor integrated circuit for storing and processing highly confidential and important information. It is about security technology.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (Large-Scale Integrat)
In order to analyze the function, operation method, circuit method, circuit pattern, stored data, etc. of the integrated circuit of the semiconductor device on which the ed circuit (LSI) is formed, the semiconductor device is conventionally provided in the semiconductor device as shown in FIG. There is a method in which a search power supply is connected to the external connection electrode pads 7 (7-1 to 7-8), an electric signal is supplied, and the input / output of terminal signals is measured by an LSI tester or the like.

In order to analyze them, the circuit block configuration and the circuit pattern itself are observed using a shape recognition device such as an optical microscope from the surface of the semiconductor device, and the process proceeds one step further using an electron beam tester or the like. Electrode pad 7
There is a method of observing a potential signal that does not appear on the wiring inside the integrated circuit. Therefore, in the current IC card 13, it is possible to open and dissect the IC module 11, read out the information inside the IC chip 12, analyze the contents of the memory, and falsify it, which is a problem from the viewpoint of security. .

[0004] FIG.
3A shows a configuration example of a C module 11, in which FIG. 3A is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on an IC card 13, FIG. 3B is a cross-sectional view, and FIG. It is sectional drawing which shows the example of mounting a module. As shown in FIG. 7C, a hot melt adhesive 34 is applied to the IC card 13 having a card thickness of 0.76 mm.
An IC module 11 is mounted. In this case, IC
The module 11 includes a glass epoxy substrate 3 on which a contact pattern 35 corresponding to an electrode of a contact type IC card is formed.
6, the IC chip 12 is die-bonded, the lead electrode pad 7 and each contact pattern 35 are wire-bonded by gold wires 37, and then sealed with a mold resin 38.

[0005] As shown in FIG.
A data memory (comprising an EEPROM or a ferroelectric memory element) 14 for storing particularly important information such as an encryption code and an authentication code and a voltage boosting circuit for writing / erasing the data memory Peripheral circuit 1 to start
5, read-only program memory (comprising ROM etc.) 16, central processing unit (CPU) for performing calculations and controls
17, a random access memory (RAM) 18 as a temporary storage memory, and a security authentication microprocessor (MPU) 19 are formed. A data bus and power supply electrode wiring (not shown) are provided around these components.

A total of eight external connection electrode pads 7 (7-1 to 7-8) made of a metal such as aluminum are formed near the ends of two opposite sides of the IC chip 12. . The electrode pad 7 is connected to the contact pattern 35 (35-1 to 35-35) on the card surface by the gold wire 37.
8). The supply of the power supply voltage to the IC chip 12 and the exchange of signals with the outside are performed via the electrode pads 7.

FIG. 8 shows a typical system architecture of the IC chip 12. In this example, of the eight external connection electrode pads 7 that are actually used, the electrode pads 7-1, 7-2, 7-3, 7-5, and 7-7 are actually used.
The five. The electrode pad 7-1 is a power supply terminal, the electrode pad 7-2 is a reset signal (RST) terminal, and the electrode pad 7
-3 is a clock signal (CLK) terminal, electrode pad 7-5
Are used as ground (GND) terminals, and the electrode pads 7-7 are used as data transmission terminals. Also, the electrode pads 7-4,
7-8 are reserved terminals, and the electrode pads 7-6 are unused terminals.

In the system architecture of a conventional IC card, an electrode pad 7 connected to a reader / writer is used.
-1 and 7-5 provide the power supply voltage Vcc and GND,
Further, a clock signal CLK for synchronizing the CPU 17 is input from the electrode pad 7-3. When the CPU 17 starts, the operating system stored in the program memory 16 is loaded. The CPU 17 has a RAM 18
While the data is being developed, various arithmetic processes are performed in accordance with the transfer data input from the electrode pads 7-7, and the final arithmetic result is stored in the nonvolatile data memory 14.
The data memory 1 mounted on such an IC card 13
4 and the program memory 16 and the MPU 19 for authentication,
Various important information such as a protocol required for communication, a number code for authentication, an amount of money used, and a remaining frequency are stored as they are.

Next, FIG. 9 shows a system architecture of an IC chip in which security is improved with respect to the configuration of FIG. In this configuration, the data stored in the data memory 14 or the program memory 16 is once encrypted by the coprocessor 3 for encryption processing and then stored in each memory. In this case, secret key information for encryption or decryption is also stored in the data memory 1 which is a nonvolatile memory.
4 is stored. By the way, in any of the secret key cryptosystem and the public key cryptosystem introduced to improve security, if the secret key information is clarified by a third party, the cryptosystem and the system itself based on it are broken. Therefore, these codes and data,
Furthermore, it is necessary to prevent information such as circuit blocks and circuit patterns constituting the semiconductor device from being read by a third party from the viewpoint of preventing forgery or falsification of the IC card.

However, in the IC card as shown in FIG. 7, the circuit configuration blocks, the data memory 14, the program memory 16, the authentication microprocessor 19, and the coprocessor 3 (see FIG. 7 (not shown) can be seen,
In addition, by probing measurement using an electron beam,
It was possible to easily read the contents of the memory element, to cause the authentication microprocessor 19 to run out of control as a trigger and malfunction, thereby skipping the authentication process itself.

Therefore, conventionally, a sensor (optical sensor, solar cell, or the like) for detecting opening of the main body case, a switching circuit that is turned on in response to the sensor detection signal, and a switching circuit for the semiconductor integrated circuit. A self-destructive IC module using an integrated circuit destruction battery connected to the opposite polarity through a circuit has been proposed (Japanese Patent Laid-Open No. Hei 2 (1994)).
-71345). According to the above configuration, in principle, when the main body case is opened to falsify the memory contents of the integrated circuit, this is detected by the sensor, and the switching signal is turned on by the detection signal. Along with this, a reverse bias is applied to the integrated circuit from the integrated circuit destruction battery, and the integrated circuit is destroyed, making tampering impossible.

[0012]

However, in such a conventional semiconductor device, when an optical sensor or a solar cell is used as a sensor, there is only a light source in a wavelength range to which these sensors do not respond (in the case of photographic development). If such an operation is performed in a dark room, the function of the sensor can be substantially stopped, and there has been a problem that tampering cannot be reliably prevented. In addition, as a sensor for detecting the dissection, a fine conductive path is provided in a winding structure on the inner wall of the container constituting the IC module, and the container is broken or damaged.
Although a form for detecting disconnection due to penetration has been proposed (Japanese Patent Application Laid-Open No. 63-78250, etc.), it is necessary to constantly supply a current to such a sensor, and the capacity density of a thin battery that can be mounted on an IC card It is difficult to operate for a long time.

If a thin power supply for destruction is short-circuited in advance by a stapler (staple) or the like, dissection can be performed without destruction of the semiconductor integrated circuit portion. In addition, when an integrated circuit, particularly a memory, is configured by the complementary MOS circuit technology, the destruction of the IC does not necessarily occur even if the reverse polarity voltage is applied. This is because the destruction occurs only in the input / output I / O-related transistors having a relatively large area, and the memory portion composed of the small-area cells is hardly destroyed.

Furthermore, when a thin lithium battery that can be mounted on an IC card is used, the internal resistance of the lithium battery is very high. There is also a problem that a required voltage cannot be obtained due to a voltage drop. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide a self-destructive semiconductor device that can reliably prevent the analysis and falsification of particularly important memory contents of a semiconductor integrated circuit.

[0015]

A self-destructive semiconductor device according to the present invention has a power supply source having connection leads for a positive electrode and a negative electrode and stores important information. A volatile memory element, and an initialization circuit that initializes the volatile memory element when a detection signal is input,
It monitors the voltage between the backup capacitor for storing charge for driving the initialization circuit, the connection terminals provided for the positive and negative electrodes of the power supply source, and the connection terminals for the positive and negative electrodes. A voltage change detection circuit that outputs a detection signal in response to the voltage drop; and, during normal operation, supplies power to the volatile memory element and accumulates electric charge in the backup capacitor. A control circuit or an element that connects the non-volatile memory element and the backup capacitor to the power supply source, and disconnects the connection when a detection signal is output from the voltage change detection circuit, on the semiconductor substrate, The power supply source is connected to the connection terminal and arranged.
The power supply source is, for example, a positive electrode current collector, a positive electrode, a solid electrolyte,
It is a thin power supply configured by stacking a negative electrode and a negative electrode current collector. The control circuit or element is composed of one or more capacitance-terminated semiconductor elements or micromechanical switches. The voltage change detection circuit includes a series connection of a first capacitor, a second capacitor, and a first resistor, and divides a connection terminal voltage applied to both ends of the voltage from a connection point of the first and second capacitors. A voltage divider for outputting, a field-effect transistor in which a divided output of the voltage divider is connected to a gate electrode and a backup capacitor or a driving capacitor is connected to a source electrode, and the field-effect transistor And a voltage change detection section comprising a second resistor connected to the drain electrode of the transistor. In a steady state, a voltage at which the field effect transistor is turned off is output from the voltage division section to reduce the connection terminal voltage. In response to the voltage division output, the voltage at which the field-effect transistor is turned on is divided and output, and a backup capacitor is provided according to the turning-on of the field-effect transistor. Supplies charge from the drive capacitor to the second resistor, and outputs a detection signal in response to an increase in the second voltage across the resistor. In the present invention, particularly important information is stored in a volatile memory, and the memory contents of the volatile memory are held by power from a power supply source. Further, a large-capacity backup capacitor is provided to avoid a voltage drop due to an internal resistance of a power supply source due to a current at the time of rewriting of the volatile memory and to drive an initialization circuit. Read the contents of the memory of a semiconductor integrated circuit, analyze it, and try to tamper with it.
When an attempt is made to disconnect the power supply, a voltage drop is detected by the voltage change detection circuit. The control circuit or element is turned off by this detection signal, the power supply source is disconnected from the volatile memory, and the volatile memory is initialized by the initialization circuit. Therefore, particularly important information stored in the volatile memory of the integrated circuit to be analyzed, dissected, and tampered is surely destroyed, and tampering is impossible.

Further, the power supply source is disposed on an interlayer insulating film formed on the semiconductor integrated circuit so as to optically shield an important part of the semiconductor integrated circuit. It is made to be done.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit block diagram of a self-destructive semiconductor device according to a first embodiment of the present invention. FIG. 2A is a plan view showing an example of the arrangement of the self-destructive semiconductor device in FIG.
(B) is a cross-sectional view of the self-destructive semiconductor device, and the same components as those in FIG. 7 are denoted by the same reference numerals.

On the semiconductor substrate 9, as a semiconductor integrated circuit 1 necessary for an original IC card function, a nonvolatile data memory (comprising an EEPROM or a ferroelectric memory element) 14 and its write / erase data are stored. Circuit 15 including a voltage booster circuit for reading, a read-only program memory (comprising a ROM or the like) 16, a central processing unit (CPU) 17 for performing calculations and controls, and a memory for temporary storage during data processing Random access memory (RA
M) 18 and a security authentication microprocessor (MPU) 19.

According to the present invention, in addition to the above configuration, a complementary MOS static RAM for storing important information (an encryption code, an authentication code, or secret key information important in a public key cryptosystem or a secret key cryptosystem). And a coprocessor (Co-Pro) for performing arithmetic processing for decrypting a cipher based on secret key information
3 and an initialization circuit 8 for initializing the memory information of the volatile memory 2 are added to the semiconductor integrated circuit 1. Further, on the semiconductor substrate 9, a control circuit or element 4, a voltage change detection circuit 5, and a backup capacitor 30 are formed.

As shown in FIG. 2B, a thin power supply source 6 for backing up the volatile memory 2 includes a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, The negative electrode current collector / terminal plate 25 is formed in a laminated structure, and the periphery thereof is thermally sealed by a sealing material 26.
The power supply source 6 is provided with connection leads 28 for the positive electrode and the negative electrode.

On the other hand, the semiconductor substrate 9 has eight external connection electrode pads 7 necessary for operation as an IC card.
In addition, two (contact pairs) electrode pads 10 for the positive electrode and the negative electrode for connection to the power supply source 6 are newly added.

In the present invention, a large-capacity backup capacitor 30 is formed on the semiconductor substrate 9 to avoid a voltage drop due to the internal resistance of the power supply source 6 and to drive the initialization circuit 8. I have. In the normal operation state,
The power of the power supply 6 is supplied to the backup capacitor 30.
Is used to store the bit information stored in the volatile memory 2 as well as to store the electric charge. At this time, the standby current of the volatile memory 2 is extremely small as described later, and can be sufficiently supplied by the battery capacity of the power supply source 6.

However, when the important information is written to the volatile memory 2 only once before the shipment of the IC card,
Since a relatively large current flows, a capacitor 30 is connected between the power line and the ground line of the volatile memory 2 and the initialization circuit 8 in order to avoid a voltage drop due to the internal resistance of the power supply source 6 at this time. Keep it.

The voltage change detection circuit 5 monitors the voltage of the electrode pad pair including one electrode pad 10 for each of the positive electrode and the negative electrode, that is, the output voltage of the power supply source 6 as needed. The control circuit or the element 4 has a switch that uses a detection signal output from the voltage change detection circuit 5 as a control input. This switch operates in a normal operation when there is no detection signal output from the voltage change detection circuit 5. In the state, it is turned on.

Thus, in the normal operation state, the positive electrode of the power supply source 6 is connected to the power supply line of the volatile memory 2 and one end of the capacitor 30 via the positive electrode pad 10, the control circuit or the element 4. . Power supply source 6
Is always connected to the ground line of the volatile memory 2 and the other end of the capacitor 30 via the electrode pad 10 for the negative electrode.

The IC chip 12a as described above is mounted on a glass epoxy board, as in FIG. The power supply source 6 is mounted on the element forming side surface of the IC chip 12a (semiconductor substrate 9) by an adhesive film 20 in order to prevent optical surface observation of the IC chip 12a. Then, the connection lead 28 of the power supply source 6 and the IC chip 12
The power supply source connection electrode pad 10 a is connected by a bump 27.

The external connection electrode pad 7 of the IC chip 12a is connected to a contact pattern corresponding to an electrode terminal of the IC card by a gold wire, as in FIG. The mounted IC module is sealed with the mold resin and mounted on the plastic case of the IC card by hot melt adhesive.

The power supply source 6 is a volatile memory 2,
The semiconductor integrated circuit 1 for supplying power to the control circuit or element 4, the voltage change detection circuit 5, and the backup capacitor 30, excluding the volatile memory 2 and the initialization circuit 8.
Is supplied with power from the outside via a power supply terminal of the external connection electrode pad 7.

A third party for falsification of the IC chip 12a first removes the IC module from the plastic case, and then removes the mold resin using a chemical. When the power supply source 6 is removed, the voltage change is detected by the voltage change detection circuit 5. When the voltage change detection circuit 5 detects a voltage change and outputs a detection signal, the detection signal is given to the control input of the control circuit or the switch of the element 4. As a result, the switch is turned off, and the connection between the volatile memory element 2 and the backup capacitor 30 and the power supply source 6 is cut off.

On the other hand, the initialization circuit 8 driven by the electric power stored in the backup capacitor 30 starts the initialization operation in response to the detection signal output from the voltage change detection circuit 5, and completes the operation of the volatile memory 2. Bit is "1" or "0"
Rewrite to Thus, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1, particularly, the important information stored in the volatile memory 2, is erased and destroyed.

IC chip 1 employing the structure of the present invention
FIG. 3 shows the system architecture of 2a. Of the eight external connection electrode pads 7 provided, those actually used are the electrode pads 7-1, 7-2, 7-3, 7-.
5, 7-7. The power supply voltage Vcc and GN are obtained from the electrode pads 7-1 and 7-5 connected to the reader / writer.
D is provided, and the CPU 17 is further provided from the electrode pad 7-3.
Are synchronized.

When the CPU 17 starts, the operating system stored in the program memory 16 is loaded. The CPU 17 performs various arithmetic processes according to the transfer data input from the electrode pads 7-7 while developing the data in the RAM 18, and stores the final arithmetic result in the nonvolatile data memory 14. In this configuration, data stored in the data memory 14 and the program memory 16 is stored after being once encrypted by the coprocessor 3 for encryption processing.

Further, in this case, the secret key information for encryption or decryption is stored in the volatile memory 2 backed up by the power supply source 6 so that a third party can decrypt the contents. When the power supply source 6 blocking the volatile memory 2 is removed, the power supply to the volatile memory 2 is cut off, and at the same time, all bits of the volatile memory 2 are initialized by the initialization circuit 8. Therefore, the secret key information stored in the volatile memory 2 is deleted.

If the power supply source 6 is removed at room temperature without the initialization circuit 8, the information in the memory 2 is instantaneously erased when the power supply to the volatile memory 2 is stopped. This cannot be read, but if the power supply 6 is removed at a low temperature, the volatile memory 2
Is held for several hours, so that the information in the memory 2 can be read. In order to prevent such illegal reading, the control circuit or element 4 disconnects the connection between the electrode pad 10 and the volatile memory 2 at the same time that the voltage change is read by the voltage change detecting circuit 5, and the initialization circuit 8 All bits of the volatile memory 2 are rewritten to “1” or “0” using the power of 30.

The feasibility of the present invention will now be outlined. In any of the public key cryptosystem and the secret key cryptosystem, if the secret key information is decrypted by a third party, the cryptosystem itself breaks down. In the currently used encryption method, the key data length is at most 1
It is about k to 2k bits. CMOS static RA
M is used as the volatile memory 2 of the current 0.5 μm CMOS.
When formed by technology, the power consumption during data retention is
It is about 3 μA at the maximum in a 64-kbit SRAM operating at 3.3 V. Therefore, in 1 k to 2 k bit conversion, the standby current at the time of holding the data is at most about 100 nA.

In addition, with the current 0.5 μm CMOS technology,
When a k-bit static RAM is configured, its occupied area is about 620 μm ² . On the IC chip, a RAM 18 of about 2 k to 4 k bits is originally mounted as a work memory area for temporary storage, which occupies the same area as the volatile memory 2. Therefore, even when the configuration of the present invention in which the secret key information is stored in the volatile memory 2 backed up by the power supply source 6 is used, the area of the additional memory 2 is almost equal to the occupied area of the original RAM 18. It is.

On the other hand, when the current thin lithium primary battery having a thickness of 0.3 mm is used as the power supply source 6, the output voltage 3
V and the battery capacity is 3 mAh / cm ² , the memory retention life of the 2 kbit volatile memory 2 is 30,000 hours (=
About three and a half years), and it is quite possible to keep the information for the life of the card. When an ultra-thin 0.1 mm thick thin lithium primary battery is used, the output voltage is 3 V and the battery capacity is 1.5 mAh, which is about half that of the 0.3 mm thick battery.
/ Cm ^2, it is necessary to increase the area of the battery approximately twice in order to ensure the same memory retention life.

[Second Embodiment] In the first embodiment,
The power supply source 6 is connected to the IC chip 12a as shown in FIG.
Although mounted on the element forming side surface of the (semiconductor substrate 9), as shown in FIG. 4, it may be arranged in parallel with the IC chip 12a. However, it is needless to say that the structure of the first embodiment is desirable to prevent the surface observation of the IC chip 12a.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. In the present invention, the output voltage of the power supply source 6 must be constantly monitored by the voltage change detection circuit 5. But,
When a thin lithium battery is mounted as the power supply source 6, its capacity density is 3 mAh / cm ² (single-stage cell, 0.1 mAh / cm ² ).
3 mm), the battery life becomes extremely short in a circuit configuration in which a large current is continuously supplied.

Therefore, the configuration of the voltage change detection circuit 5 is indispensable to have a capacitively coupled circuit configuration such that a leak path does not match a current path involved in its operation. FIG. 5 shows an example of such a capacitively-coupled voltage change detection circuit. In this embodiment, a MOS field effect transistor is used as the voltage change detecting element.

The output voltage of the power supply source 6 is divided by the voltage dividing capacitors C ₁ and C ₂ and the resistor R _1, and from the connection point of the voltage dividing capacitors C ₁ and C ₂ to the voltage change detecting transistor 31. Input to the gate. Since the power consumption of the voltage change detection transistor 31 is very small, the voltage stored in the backup capacitor 30 can be used as the drive voltage, or a large-capacity drive circuit provided separately from the capacitor 30 can be used. The voltage stored in the capacitor may be used.

When a third party for the purpose of falsifying the IC card disconnects the power supply 6, the capacitance-divided voltage set near the threshold voltage of the transistor 31 fluctuates. Turns on. Accordingly, current flows between the source and the drain of the transistor 31, a voltage drop occurs between the resistor R ₂ terminals.
This voltage drop is output as a detection signal to the control circuit or element 4 via the post-amplifier circuit.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIG. Because the capacity of the thin power supply 6 to be mounted is limited,
It is desirable that the switch in the control circuit or the element 4 consumes as little power as possible. Usually, this switch is generally a semiconductor switch configured by combining transistors. In this case, however, it is a major problem to reduce power consumption due to sub-threshold current leakage when the switch is off.

In the present invention, as such a switch with low power consumption, it is also possible to use a micromechanical switch which is a kind of micro mechanical element having a movable portion and opens and closes contacts using electrostatic attraction. . FIG. 6 shows an example of a micro-mechanical switch that opens and closes contacts using such electrostatic attraction. In the figure, (a) is a sectional view,
(B) is a plan view.

As shown in FIG. 6A, the movable suction electrode 4
7 is installed through the support beam 48 and the connection electrode 49a. When no voltage is applied to the fixed suction electrode 50, the movable contact electrode 51 has the elastic force (upward) of the support beam 48.
As a result, they are pressed against the fixed contact electrodes 52b and 52c.

As a result, the COMM input terminal 53 is electrically connected to the output 2 terminal 54b. The fixed contact electrode 52
The b and 52c are supported by the contact electrode support 55, and are electrically connected to the COMM input terminal 53 and the output 2 terminal 54b via the connection electrodes 49b and 49c, respectively. The movable contact electrode 51 is electrically insulated from the support beam 48 by the insulating film 57 and is mechanically fixed to the support beam 48.

When a voltage is applied from the movable contact operating power supply terminal 56 to the fixed suction electrode 50, the support beam 48 is generated by electrostatic attraction acting between the fixed suction electrode 50 and the movable suction electrode 47.
Goes down. Then, the movable contact electrode 51 becomes the fixed contact electrode 5
2b, 52c, the fixed contact electrode 52 on the opposite side
a, 52d. As a result, the COMM input terminal 53 becomes the output 1 terminal 5 via the movable contact electrode 51.
4a.

When the application of the voltage to the fixed suction electrode 50 is stopped, the movable contact electrode 51 moves upward by the elastic force of the support beam 48. As a result, the movable contact electrode 51 is again pressed against the fixed contact electrodes 52b and 52c, and the COMM
The input terminal 53 conducts with the output 2 terminal 54b. In this way, the on / off of the micro mechanical switch is performed.

When the micromechanical switch as shown in FIG. 6 is used as the control circuit or the element 4, the output of the voltage change detection circuit 5 is connected to the movable contact operating power supply terminal 56, and the electrode pad 10 is connected to the COMM input terminal 53. , And the power supply line of the volatile memory 2 and one end of the capacitor 30 may be connected to the output 2 terminal 54b.

[0050]

According to the present invention, a volatile memory for storing particularly important information and an initialization circuit are provided on the same semiconductor substrate as a semiconductor integrated circuit, and the memory contents of the volatile memory are supplied from a power supply source. And hold it with the power of
When the power supply source is removed, the control circuit or the element is turned off by a detection signal from the voltage change detection circuit, power supply to the volatile memory is cut off, and at the same time, the volatile memory is initialized by the initialization circuit. With this configuration, particularly important information stored in the volatile memory can be surely erased, and the decipherment and falsification of the memory content can be reliably prevented.

Further, since the power supply source is arranged so as to shield an important part of the semiconductor integrated circuit, optical observation can be avoided. In particular, for surface observation, it is necessary to remove the power supply source used for shielding from the semiconductor integrated circuit. Such an action is performed by the semiconductor integrated circuit to be falsified as described in detail above. Because it erases important information stored in volatile memory,
Decoding and falsification of the memory contents of the semiconductor integrated circuit can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block configuration diagram of a self-destructive semiconductor device according to a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG.

FIG. 3 is a diagram illustrating an example of a system architecture of an IC card.

FIG. 4 is a plan view showing an example of an arrangement configuration of a self-destructive semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration example of a voltage change detection circuit according to a third embodiment of the present invention.

6A and 6B are a cross-sectional view and a plan view illustrating a configuration example of a control circuit or an element according to a fourth embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a configuration example of a general IC card.

FIG. 8 is a diagram showing a system architecture of a conventional IC card.

FIG. 9 is a diagram showing a system architecture of a high security IC card.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Volatile memory, 3 ... Coprocessor, 4 ... Control circuit or element, 5 ... Voltage change detection circuit,
6 power supply source, 7 external connection electrode pad, 8 initialization circuit, 9 semiconductor substrate, 10 power supply connection electrode pad, 12a IC chip, 14 data memory, 1
5: Peripheral circuit, 16: Program memory, 17: Central processing unit, 18: Random access memory, 19: Microprocessor for authentication, 20: Adhesive film, 21: Positive electrode current collector and terminal plate, 22: Positive electrode, 23 ... Solid electrolyte, 2
4: negative electrode, 25: negative electrode current collector / terminal plate, 26: sealing material,
27: bump, 28: connection lead, 30: backup capacitor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Aoyama 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Shintaro Shibata 3- 192-1 Nishishinjuku, Shinjuku-ku, Tokyo No. Nippon Telegraph and Telephone Corporation F-term (reference) 5F083 BS00 EP00 GA30 ZA11 ZA13 ZA14 ZA20 ZA23

Claims (2)

[Claims] 1. A semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate, wherein connection leads for a positive electrode and a negative electrode are provided. A volatile memory element for storing important information, an initialization circuit for initializing the volatile memory element when a detection signal is input, and a driving circuit for driving the initialization circuit. A backup capacitor that accumulates the electric charge of the power supply, a connection terminal provided for the positive and negative electrodes of the power supply source, and a voltage between the terminals of the positive and negative connection terminals is monitored, and a detection signal is generated in response to the voltage drop. And a voltage change detection circuit that outputs a signal during normal operation in order to supply power to the volatile memory element and accumulate charge in the backup capacitor.
A control circuit or element that connects the volatile memory element and the backup capacitor to the power supply via the connection terminal and cuts off the connection when a detection signal is output from the voltage change detection circuit, A self-destructive semiconductor device provided on a semiconductor substrate, wherein a power supply source is connected to the connection terminal and arranged. 2. The self-destructive semiconductor device according to claim 1, wherein the power supply source is an interlayer insulating film formed on the semiconductor integrated circuit so as to optically shield an important part of the semiconductor integrated circuit. A self-destructive semiconductor device, which is disposed thereon.