JP2000011678A - Switching circuit and sample-and-hold circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching circuit which restrains a delay when current sources are changed over in a high-speed switching operation, and to provide a sample-and-hold circuit which uses the switching circuit. SOLUTION: A sample-and-hold circuit is provided with a current-source switching part 10, in which a transistor Q11 and a transistor Q12 switch a current source I11 and a current source I12 according to the logic state of S/H pulses with reference to a threshold voltage Vth. In the sample-and-hold circuit, a control circuit 30 which controls the threshold voltage Vth so as to be lowered temporarily at the rise transition timing of the S/H pulses is installed. A delay is suppressed in the changeover of the current sources I11, I12 when a sample period is shifted to a hold period by the action of the control circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit and a sample-and-hold circuit using the same, and more particularly to a switching circuit requiring high-speed switching and a sample-and-hold circuit suitable for shaping the output signal of a solid-state image sensor. About.

[0002]

2. Description of the Related Art A sample-and-hold circuit is, for example,
CCD (Charge Coupled Device) type image sensor (hereinafter, C
In a signal processing system for processing an output signal of a solid-state image pickup device such as a CD image pickup device, an IC is formed together with peripheral circuits such as an auto gain control circuit (hereinafter, referred to as an AGC circuit), and an output signal of the solid-state image pickup device is output. Used for waveform shaping.

FIG. 4 shows an example of the configuration of a conventional sample-and-hold circuit. The sample and hold circuit according to the conventional example is roughly composed of a current source switch unit 50 and a signal transfer unit 60.

The current source switch section 50 includes PNP transistors Q51 and Q52 whose emitters are connected in common, current sources I51 and I52 connected between the collectors of the transistors Q51 and Q52 and the ground, and transistors Q51 and Q52. Q52 emitter common connection point and power supply VCC
A resistor R51 connected between the power supply VCC and the base of the transistor Q52,
It comprises a resistor R52 connected between the base of the transistor Q52 and the ground.

In the current source switch section 50, a sample / hold pulse (hereinafter referred to as an S / H pulse) input from the outside is applied to the base of a transistor Q51.
The voltage divided by the resistors R51 and R52, that is, ΔR52 /
Threshold voltage Vth determined by (R51 + R52)｝ × VCC is applied to the base of transistor Q52. Then, with respect to the threshold voltage Vth,
S / H pulse is high level (hereinafter referred to as “H” level)
Or low level (hereinafter, referred to as “L” level), the current sources I51 and I52 are switched.

That is, when the S / H pulse is at the "L" level, it is a sampling period. In this sampling period, the transistor Q51 is turned on, so that the current source I
51 becomes active, and a sample current Isample1 flows to the current source I51. The "H" level of the S / H pulse is a hold period. In this hold period, the transistor Q52 is turned on to activate the current source I52, and a hold current Ihold1 flows to the current source I52. .

On the other hand, the signal transfer unit 60 includes NPN transistors Q61 and Q62 whose emitters are connected in common, and P collectors whose collectors are connected to the collectors of the transistors Q61 and Q62 and whose bases are connected in common.
NP transistors Q63 and Q64, resistors R61 and R62 connected between the emitters of these transistors Q63 and Q64 and power supply VCC, and transistors Q61 and Q64.
A current source I61 connected between the emitter common connection point of the transistor 62 and the ground; a current source I62 connected between the emitter of the transistor Q64 and the ground;
A hold capacitor C61 connected between the base of the transistor 62 and the ground, an NPN transistor Q65 having a base connected to the transistor Q62 in common and a collector connected to the power supply VCC, and connected between the emitter of the transistor Q65 and the ground. Current source I63.

In the signal transfer section 60 having the above configuration, NP
N transistor Q62 and PNP transistor Q63
Are diode-connected in which the base and the collector are connected in common. In addition, transistors Q63 and Q6
Reference numeral 4 denotes a current mirror circuit. The current source I61 and the current source I51 of the current source switch unit 50 and I62 form a current mirror circuit with the current source I52 of the current source switch unit 50, respectively. The input signal Vin is used as the base input of the transistor Q61,
An output signal Vout is derived from 65 emitters.

In the signal transfer section 60, since the sample current Isample1 flows to the current source I51 of the current source switch section 50 during the sample period, the sample current Isample2 having the same current value flows to the current source I61.
The input signal Vin is transferred. At this time, a current corresponding to the input signal Vin flows through the hold capacitor C61 as a charging current. Thereby, the hold capacitor C
61 is charged to the potential (Vin) to be held, and this is derived as an output signal Vout via the transistor Q65.

During the hold period, the hold current Ihold1 having the same current value as the hold current Ihold1 flows through the current source I52 of the current source switch unit 50.
Flows to the current source I62 via the resistor R62, and the current source I
Since no current flows through 61, the input signal Vin is not transferred. At this time, the output signal Vout is held by the potential stored in the hold capacitor C61.

By the way, a sample-and-hold circuit used for shaping the waveform of an output signal of a CCD image pickup device is required to have high-speed performance. Therefore, in this type of sample and hold circuit, as described above, the signal transfer unit 60 having the buffer amplifier configuration is connected to the current sources I51 and I51 of the current source switch unit 50.
The control is performed by switching I52.

[0012]

However, in the conventional sample-hold circuit having the above-mentioned structure, the S / H pulse "H" level /
Since the switching is performed only by switching the “L” level (single operation), when switching from the “L” level (sample) to the “H” level (hold), the current on the sample side is limited due to the circuit characteristics. Since there is a delay in the time when the current source I52 on the hold side is turned on compared to the time when the source I51 is turned off, there is a problem that a step occurs in the waveform of the output signal Vout of the signal transfer unit 60 due to this delay. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a switching circuit that suppresses a delay when switching a current source during high-speed switching, and a sample-and-hold circuit using the same. Is to provide.

[0014]

A switching circuit according to the present invention comprises a first and a second current sources, a pulse signal applied to one base, and a predetermined threshold voltage applied to the other base. First and second transistors for selectively turning on the first and second current sources in accordance with the logical state of the pulse signal; and temporarily changing the threshold voltage in synchronization with the transition timing of the pulse signal. And a control circuit for performing a control to change.

In the switching circuit having the above configuration, the first and second transistors switch the first and second current sources in accordance with the logic state of the pulse signal with respect to the threshold voltage. At this time, the control circuit performs control to temporarily lower (or raise) the threshold voltage at the transition timing of the rising (or falling) of the pulse signal. As a result, a delay at the time of switching (switching) of the current source can be suppressed.

In the sample and hold circuit according to the present invention, the S / H pulse is supplied to the first and second current sources and one of the bases.
A predetermined threshold voltage is applied to the other base, respectively, and first and second transistors for selectively operating the first and second current sources in accordance with the logic state of the S / H pulse for this threshold voltage A current source switch unit having a control circuit for performing a control for temporarily changing the threshold voltage in synchronization with the transition timing of the S / H pulse; and a hold capacitor, wherein the first current source is in an operating state. A signal that charges the hold capacitor in accordance with the input signal during the sample period, holds the charge of the hold capacitor during the hold period when the second current source is in the operating state, and derives the potential of the hold capacitor as an output signal. And a transfer unit.

In the sample and hold circuit having the above configuration, the first and second transistors of the current source switch section are
The first and second current sources are switched according to the logic state of the S / H pulse with respect to the threshold voltage. At this time, the control circuit performs control to temporarily lower (or raise) the threshold voltage at the transition timing of the rising (or falling) of the S / H pulse. Thus, a delay in switching the current source in the current source switch unit can be suppressed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a sample and hold circuit according to one embodiment of the present invention. The sample and hold circuit according to the present embodiment is roughly composed of a current source switch unit 10 and a signal transfer unit 20.

The current source switch section 10 includes PNP transistors Q11 and Q12 having emitters connected in common, and current sources I11 and Q11 connected between the collectors of the transistors Q11 and Q12 and ground (first power supply). I1
2, a current source I13 connected between the common emitter connection point of the transistors Q11 and Q12 and the power supply VCC (second power supply), a resistor R11 connected between the power supply VCC and the base of the transistor Q12, In addition to the configuration including the resistor R12 connected between the base of the transistor Q12 and the ground, a control circuit 30 that performs control to temporarily change the base potential of the transistor Q12 in synchronization with the S / H pulse transition timing is provided. Configuration.

In the current source switch section 10, an externally input S / H pulse is applied to the base of the transistor Q11, and is determined by the voltage divided by the resistors R11 and R12, ie, {R12 / (R11 + R12)} × VCC. Threshold voltage Vth is applied to the base of transistor Q12. Then, the threshold voltage Vth
S / H pulse is at "H" level or "L"
Switching (switching) for selectively setting the current sources I11 and I12 to an operation state is performed depending on the level.

That is, the "L" level of the S / H pulse is a sample period, and in this sample period, the transistor Q11 is turned on, so that the current source I
11 becomes active, and a sample current Isample1 flows to the current source I11. The "H" level of the S / H pulse is a hold period. In this hold period, the transistor Q12 is turned on to activate the current source I12, and a hold current Ihold1 flows to the current source I12. .

The control circuit 30 includes a capacitor C3 connected in series between the base of the transistor Q11 and the ground.
1 and a resistor R31, and an NPN transistor (hereinafter referred to as a saturation transistor) connected between the base of the transistor Q12 and the ground, and having a base connected to the output terminal of the differentiator 31, ie, a CR connection point. Q31 and an NPN transistor Q32 connected between the base of the saturation transistor Q31 and the ground and the base is also connected to the ground.

In the control circuit 3, when the S / H pulse rises at the time of transition from the sample period to the hold period, the base voltage of the saturation transistor Q31 rises due to the differential output of the differentiation circuit 31, and becomes higher than the ground level. When the voltage rises by 1 Vf (Vf is the voltage between the base and the emitter of the transistor), the saturation transistor Q31
Is turned on. Since the saturation transistor Q31 is connected between the base of the transistor Q12 and the ground, when it is turned on, the base voltage of the transistor Q12, that is, the threshold voltage Vth
Temporarily to near ground level.

As a result, the switching becomes a differential operation, and the base voltage of the transistor Q12 is temporarily reduced to near the ground level at the moment of the rise of the S / H pulse, whereby the transistor Q12 is quickly turned from the off state to the on state. The delay at the time of switching between the current source I11 on the sample side and the current source I12 on the hold side is reduced, and the switching speed between the current sources I11 and I12 is increased.

On the other hand, when shifting from the hold period to the sample period, the base voltage of the saturation transistor Q31 is changed to the ground level by the differential output of the differentiating circuit 31 at the moment of the rise of the S / H pulse, contrary to the above. Of the transistor Q32
Is limited to the ground level -1 Vf. At this time, since the saturation transistor Q31 is kept off, the threshold voltage Vth does not change, and the switching becomes a single operation.

The transistor Q32 is provided as a limiter for preventing the voltage applied between the emitter and the base of the saturation transistor Q31 from exceeding the reverse breakdown voltage between the emitter and the base of the saturation transistor Q31.
When shifting from the sample period to the hold period, the saturation transistor Q31 also functions as a limiter for protecting the transistor Q32.

The time constant of the CR of the differentiating circuit 31 is set so as to optimize the period during which the saturation transistor Q31 is on in consideration of the frequency and duty of the input S / H pulse. I do.

On the other hand, the signal transfer section 20 has NPN transistors Q21 and Q22 whose emitters are connected in common, and P collectors whose collectors are connected to the collectors of these transistors Q21 and Q22 and whose bases are connected in common.
NP transistors Q23 and Q24, resistors R21 and R22 connected between the emitters of the transistors Q23 and Q24 and the power supply VCC, and transistors Q21 and Q24.
22, a current source I21 connected between the emitter common connection point of the transistor Q24 and the ground, a current source I22 connected between the emitter of the transistor Q24 and the ground,
22, a hold capacitor C21 connected between the base and the ground, an NPN transistor Q25 whose transistor Q22 and the base are connected in common and a collector connected to the power supply VCC, and a connection between the emitter of the transistor Q25 and the ground. Current source I23.

In the signal transfer unit 20 having the above configuration, NP
N transistor Q22 and PNP transistor Q23
Are diode-connected in which the base and the collector are connected in common. Further, the transistors Q23 and Q2
Reference numeral 4 denotes a current mirror circuit. The current source I21 and the current source I11 of the current source switch unit 10 and the current source I22 of the current source switch unit 10 constitute a current mirror circuit. Then, the input voltage Vin is used as the base input of the transistor Q21,
The output voltage Vout is derived from the 25 emitters.

In the signal transfer section 10, during the sample period when the S / H pulse is at the "L" level, the sample current Isample1 flows through the current source I11 of the current source switch section 10, so that the sample having the same current value as the sample current Isample1. Current I
sample2 flows to the current source I21. At this time, when the input voltage Vin is applied to the base of the transistor Q21, the transistor Q21 is turned on, so that the sample current Isample2 flows through the transistor Q23.

A current having the same value also flows through the transistor Q23 and the transistor Q24 which forms a current mirror circuit. At this time, since the base potential of the transistor Q22 is low and the transistor Q22 is off, the transistor Q24 Flows through the hold capacitor C21 as a charging current. The hold capacitor C21 is charged by the charging current, and the base potential of the transistor Q22 increases accordingly.

At this time, since the transistors Q21 and Q22 operate so that the respective base potentials are balanced, the hold capacitor C21 is charged to the voltage (Vin) to be held. That is, the sample current Isamp is supplied to the current source I21.
The input voltage Vin is transferred by the flow of le2, and as a result, the voltage across the hold capacitor C21 (potential difference between both ends) becomes equal to the input voltage Vin. The voltage across the hold capacitor C21 is derived as an output voltage Vout via the transistor Q25.

Next, during the hold period in which the S / H pulse is at the "H" level, the current source I1 of the current source switch section 10 is turned on.
2, the hold current Ihold1 having the same current value flows through the resistor R22 to the current source I22. At this time, no current flows to the current source I21, and the transistors Q21 and Q22 are both off, so that the transfer of the input voltage Vin is not performed. In this state, if the input impedance of the transistor Q25 is close to infinity and the leakage of the base current or the like is sufficiently small, the voltage sampled by the hold capacitor C21 is held at a constant voltage.

The above-described series of sample and hold operations are repeatedly executed in the cycle of the S / H pulse, so that the output voltage Vout obtained by shaping the waveform of the input voltage Vin is output from the emitter of the transistor Q25. Derived.

As described above, in the sample-and-hold circuit used for the purpose of shaping the waveform of the input signal, the S / S / S
By providing the control circuit 30 that performs control to temporarily lower the threshold Vth in synchronization with the rising timing of the H pulse, a delay in switching between the current source I11 on the sample side and the current source I12 on the hold side is reduced. As a result, the switching speed of the current source I11 and the current source I12 is increased, so that a more ideal output waveform can be obtained as the output voltage Vout.

In the above-described embodiment, the switching operation is performed at the timing when the S / H pulse rises, but the NPN of the control circuit 30 of the current source switch section 10 is switched.
As shown in FIG. 2, transistors Q31 and Q32 are
In place of NP transistors Q33 and Q34, power supply VCC
By using the control circuit 30 ′ configured to be connected to the
Differential operation at the timing when the / H pulse falls is also possible.

That is, in the current source switch section 10, a differentiating circuit 32 including a capacitor C32 and a resistor R32 connected in series between the base of the transistor Q11 and the power supply VCC, and a differential circuit 32 connected between the base of the transistor Q12 and the power supply VCC. And a PNP transistor Q whose base is connected to the output terminal of the differentiating circuit 32, that is, the CR connection point.
33, the base of the transistor Q33 and the power supply VCC.
And the base is also connected to the power supply VCC.
The control circuit 30 'is constituted by the NP transistor Q34.

Regarding the configuration of the current source switch section 10,
The differential pair transistors Q11 and Q12 are not limited to PNP transistors, but can be similarly configured by using NPN transistors. Furthermore, the configuration of the signal transfer unit 20 is not limited to the circuit configuration of FIG.

In the above embodiment, the case where the switching circuit according to the present invention is used as the current source switch section 10 of the sample and hold circuit has been described. However, the present invention is not limited to the application to the sample and hold circuit.
The present invention can be applied to all switching circuits requiring high-speed switching.

The sample hold circuit according to the present embodiment is, for example, a signal processing system for processing an output signal of a solid-state image pickup device represented by a CCD image pickup device. It is suitable for use in The sample and hold circuit used for shaping the waveform of the output signal of the CCD image sensor requires high-speed performance.

FIG. 2 shows an example of the configuration of the signal processing system of the CCD image pickup device. In this example, a sample-and-hold circuit according to the present invention is incorporated in a head amplifier IC 42 for driving an A / D converter 43 based on an analog signal from a CCD image sensor 41. Head amplifier IC42
Has an input terminal 44 and an output terminal 45. The input terminal 44 is connected to the output terminal of the CCD image sensor 41, and the output terminal 45 is connected to the input terminal of the A / D converter 43. .

The head amplifier IC 42 has a sample-and-hold (S / H) circuit 46 for shaping the waveform by sampling and holding an analog signal from the CCD image pickup device 41 input via the input terminal 44, An AGC circuit 47 for automatically adjusting the output signal level of the hold circuit 46 and a driver 48 for driving the subsequent A / D converter 43 based on the output signal of the AGC circuit 47 are built in. Then, the sample and hold circuit shown in FIG. 1 is used as the sample and hold circuit 46.

As described above, by using the sample and hold circuit according to the present invention for shaping the waveform of the output signal of the solid-state image pickup device represented by the CCD image pickup device, it is possible to sufficiently cope with high-speed switching. Since there is no delay when switching the sources and the switching speed of the current source is fast, the output signal of the solid-state imaging device can be shaped into a signal having a waveform closer to ideal.

[0045]

As described above, according to the present invention,
In a switching circuit that switches a current source in accordance with a logic state of a pulse signal with respect to a threshold voltage or a sample and hold circuit using the same, the threshold voltage is temporarily lowered at a transition timing of rising (or falling) of the pulse signal ( Or increase), it is possible to suppress a delay in switching the current source.

As a result, in a sample-and-hold circuit used for shaping the output signal of a CCD image sensor, for example, which requires high-speed performance, a delay in switching the current source can be suppressed. Since the resulting inconvenience can be improved, an output waveform closer to the ideal can be obtained as the waveform shaping output.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a sample and hold circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modification of one embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a configuration of a signal processing system of a CCD imaging device to which the present invention is applied.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

10, 50 ... current source switch unit, 20, 60 ... signal transfer unit, 30, 30 '... control circuit, 31, 32 ... differentiation circuit,
41: CCD imaging device, 42: Head amplifier IC, 46
... Sample hold (S / H) circuit

Claims (6)

[Claims] A first current source; a first current source; a pulse signal applied to one base; and a predetermined threshold voltage applied to the other base. The pulse signal is applied to the base in accordance with a logic state of the pulse signal with respect to the threshold voltage. First and second first and second current sources are selectively activated.
A switching circuit comprising: a second transistor; and a control circuit that performs control to temporarily change the threshold voltage in synchronization with a transition timing of the pulse signal. 2. The control circuit is connected between a differentiating circuit for differentiating the pulse signal, a base of the first transistor to which the threshold voltage is applied, and a first or second power supply, and A third state which is turned on in response to a differential output of the differentiating circuit at a signal transition timing;
The switching circuit according to claim 1, further comprising: 3. The control circuit includes a fourth transistor connected between a base of the third transistor and a first or second power supply and having a base connected to an emitter of the third transistor. 3. The switching circuit according to claim 2, comprising: 4. A first and second current source, a sample and hold pulse applied to one base and a predetermined threshold voltage applied to the other base, respectively, according to a logic state of the sample and hold pulse with respect to the threshold voltage. And first and second transistors for selectively operating the first and second current sources, and control for temporarily changing the threshold voltage in synchronization with the transition timing of the sample and hold pulse. A current source switch unit having a control circuit; and a hold capacitor, wherein the hold capacitor is charged according to an input signal during a sample period in which the first current source is in an operating state, and the second current source is In the hold period in which the operation state is established, the charge of the hold capacitor is held, and the potential of the hold capacitor is reduced. Sample-and-hold circuit, characterized in that a signal transfer unit for deriving as a force signal. 5. The control circuit is connected between a differentiating circuit for differentiating the sample and hold pulse, a base of the first transistor to which the threshold voltage is applied, and a first or second power supply, 5. The sample and hold circuit according to claim 4, further comprising a third transistor that is turned on in response to a differential output of the differential circuit at a transition timing of the sample and hold pulse. 6. The control circuit includes a fourth transistor connected between a base of the third transistor and a first or second power supply and having a base connected to an emitter of the third transistor. 6. The sample-hold circuit according to claim 5, comprising: