JP2000011673A - Negative boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a negative boosting circuit which restrains the leakage and the substrate bias effect of a parasitic bipolar transistor and whose efficiency is good at a low voltage while the negative boosting circuit is constituted by using an N-channel MOS transistor. SOLUTION: When a negative boosting circuit is constituted by using N- channel MOS transistors 81 to 88 in a tripple well process, the substrate potential of the N-channel MOS transistors 81 to 88 is made to float. Thereby, a rise in the threshold of the transistors 81 to 88 due to a substrate bias effect is suppressed, and the collector current of a parasitic NPN transistor due to a forward current from a substrate caused by a boosting operation is suppressed. In addition, when the potential of a PW substrate in the start of the boosting operation is set at a ground potential by P-type MOS transistors 111 to 118, the substrate bias effect of the N-channel MOS transistors 81 to 88 is eliminated, and a boosting operation at 2 V or lower can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an efficient negative booster circuit which can be operated at a low voltage and is manufactured by a triple well process.

[0002]

2. Description of the Related Art Normally, a flash EEPROM (read only memory which is electrically erasable and programmable in a batch) is operated by a single power supply, and a negative high voltage required for a writing and erasing operation is generated from a low voltage power supply. Built-in booster circuit. In particular, with the lowering of the power supply voltage of mobile devices and the like, a highly efficient negative booster circuit has been demanded.

FIG. 5 shows a conventional charge pump type negative voltage generating circuit. In FIG. 5, reference numerals 41 to 48 denote N-channel MOS transistors constituting a negative booster circuit, each of which is independently connected to a substrate. Clocks for negative boosting are input from terminals 1 to 4. Its amplitude is the power supply voltage. The respective waveforms of these clock inputs 1 to 4 are shown in FIG. 61 to 68 are capacitances for boosting (hereinafter simply referred to as capacitances).

[0004] The operation of the negative voltage generating circuit configured as described above will be described. First, the charge generated by the clock 2 makes the potentials of the nodes 52 and 56 of the negative booster circuit negative. Thereafter, the gate potentials of the transistors 43 and 47 become positive by the clock 4, and the negative charges of the nodes 52 and 56 are transmitted to the nodes 54 and 58.

Next, nodes 54 and 5 are driven by clock 1.
The potential of 8 is further made negative. Thereafter, the gate potential of the transistors 41 and 45 becomes positive by the clock 3, and
The negative charge on node 54 is transmitted to node 56. As described above, the charge generated by the capacitive coupling of the clock is transmitted through the transistor, and more charge is accumulated, thereby generating a negative high voltage.

[0006]

However, when attention is paid to, for example, the transistor 43, it is understood that the parasitic bipolar transistor 49 as shown in FIG. 6 is formed. As shown by the hatched portion in FIG. 7, when the node 52, which is the drain of the transistor 43, has a negative potential due to the timing of the clock 2, the node 54 connected to the source of the transistor 43 has a positive potential with respect to the node 52. It has become. Therefore, PW, which is the substrate of transistor 43, also has a positive potential with respect to node 52. As a result, a forward current 75 is generated from the substrate to the drain as shown in FIG.
Base current. As a result, there is a drawback that the collector current 76 from the NT is induced, and the generated negative charges leak to the NT.

Further, in order to suppress the leakage of the parasitic bipolar transistor, a circuit configuration using a P-channel MOS transistor is possible. However, in the case of a P-channel MOS transistor, the substrate becomes an N-type, and thus a triple type is used. Even if a well process is used, it is impossible to lower the substrate potential below the ground level. Therefore, a substrate bias effect occurs for the boosted voltage, and a clock amplitude equal to or higher than the threshold value increased by the substrate bias effect is required. Therefore, the P-channel type MOS
The circuit configuration using transistors is not suitable for low-voltage operation.

In view of the above-mentioned conventional problems, the present invention suppresses the leakage of the parasitic bipolar transistor and the body bias effect, and has a low voltage and an efficient negative voltage. It is an object to provide a negative voltage generating circuit capable of boosting.

[0009]

A negative voltage generating circuit according to the present invention for achieving this object is constructed by using an N-channel MOS transistor in a triple well process, and sets the substrate potential of the N-channel MOS transistor to each. By independently setting the floating state, a rise in the threshold value of the transistor due to the substrate bias effect is suppressed, and a collector current of the parasitic NPN transistor due to a forward current from the substrate due to the boosting operation is suppressed.

Preferably, when the substrate potential of the N-channel MOS transistor is not operating, the P-channel MOS transistor is connected to the ground potential so that the threshold voltage of the transistor increases due to the substrate bias effect when the boosting operation is started. suppress.

[0011] According to the above configuration, a highly efficient negative booster circuit capable of operating at a low voltage by suppressing the leakage of the parasitic bipolar transistor and the body bias effect is realized.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a circuit diagram of a negative booster circuit according to a first embodiment of the present invention. In FIG. 1, reference numerals 11 to 18 denote N-channel MOS transistors constituting a negative booster circuit, each of which is independently connected to a substrate. 1-4
Is a clock input for negative boosting, and its amplitude is a power supply voltage. A timing chart of these clock inputs 1 to 4 is shown in FIG. Reference numerals 31 to 38 denote capacitors for boosting.

The operation of the negative voltage generating circuit configured as described above will be described. First, the electric charge generated by the clock 2 makes the potentials of the nodes 22 and 26 of the negative booster circuit negative. Thereafter, the gate potentials of the transistors 13 and 17 become positive by the clock 4, and the negative charges of the nodes 22 and 26 are transmitted to the nodes 24 and 28.

Next, clocks 1 cause nodes 24 and 2
The potential of 8 is further made negative. Then, the gate potential of the transistors 11 and 15 becomes positive by the clock 3, and
The negative charge on node 24 is transmitted to node 26. In this manner, the charge generated by the capacitive coupling of the clock is transmitted through the transistor, and more charge is accumulated, thereby generating a negative voltage.

Focusing on the transistor 13, it can be seen that a parasitic bipolar transistor 19 as shown in FIG. 4 is formed. As shown by hatching in FIG. 3, the node 22, which is the drain of the transistor 13, has a negative potential at the timing of the clock 2, and the node 24 connected to the source of the transistor 13 has a positive potential with respect to the node 22. The PW, which is the substrate of the transistor 13, is floating and has a potential higher by the built-in voltage of the node 24. PW substrate charge is PW
A forward current flows from the substrate to the drain, but does not induce a collector current.
There is no leak to T.

Although the PW substrate has a potential higher by the built-in voltage due to the node 24 connected to the source of the transistor 13 and the node 22 serving as the drain, it does not have a potential high enough to cause a back gate bias effect. Therefore, the threshold voltage of the transistor 13 does not change, and a boosting operation can be performed with a clock having an amplitude of about 2 V.

(Embodiment 2) FIG. 8 is a circuit diagram of a negative voltage generating circuit according to a second embodiment. In FIG. 8, 81
Reference numerals 88 denote N-channel MOS transistors constituting a negative booster circuit, the substrates of which are independently connected. 1 to
Reference numeral 4 denotes a negative boosting clock. Reference numerals 111 to 118 denote P-channel MOS transistors that set the potential of the PW substrate to the ground potential at the time of startup. The waveform of the negative boosting clock is shown in FIG. 2, and its amplitude is the power supply voltage. FIG. 9 shows P-channel MOS transistors 111 to 11
8 is a timing chart showing the relationship between the control of FIG. 8 and a clock. Reference numerals 101 to 108 denote capacitors for boosting.

When the negative booster circuit thus configured is started, the threshold value of the N-channel MOS transistor having a floating PW substrate may be increased due to the substrate bias effect when the substrate is depleted. There is. In this case, the operation is started by setting the amplitude of the clock input to the negative booster circuit to about 2 V or more at the time of startup. Then, the charge generated by the clock is supplied to the source and the drain of the N-channel MOS transistor via the capacitor through the capacitor, so that the depletion of the PW substrate is reduced.

For this reason, the potential of the PW substrate is set to the ground potential by the P-channel MOS transistors 111 to 118 as shown in FIG. It works even if there is. That is, the substrate bias effect of the N-channel MOS transistor is eliminated, and the boosting operation can be performed at a lower voltage.

[0020]

As described above, the negative booster circuit of the present invention
By using an N-channel MOS transistor having an independent substrate and a floating substrate, low-voltage operation is possible and efficient and excellent performance can be realized. Further, the PW substrate of the N-channel MOS transistor constituting the booster circuit is replaced with a P-channel MOS transistor.
By fixing the voltage to the ground potential at the time of starting the boosting by the transistor, the boosting operation can be performed more efficiently.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a negative booster circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a boosting clock in the negative boosting circuit of the present invention.

FIG. 3 is a timing chart of the potential of each node of the negative booster circuit of FIG. 1;

FIG. 4 is an N-channel type M constituting the negative booster circuit of FIG. 1;
Cross section of OS transistor

FIG. 5 is a circuit diagram of a conventional negative booster circuit;

6 is an N-channel type M constituting the negative booster circuit of FIG.
Cross section of OS transistor

FIG. 7 is a timing chart of the potential of each node of the negative booster circuit of FIG. 5;

FIG. 8 is a circuit diagram of a negative booster circuit according to a second embodiment of the present invention.

9 is a timing chart of a boosting clock of the negative boosting circuit of FIG. 8 and a control signal of a P-channel MOS transistor;

[Explanation of symbols]

1 to 4 Negative booster clock 11 to 18 N-channel MOS transistor 21 First-stage gate node of negative booster circuit 22 First-stage node of negative booster circuit 23 Second-stage gate node of negative booster circuit 24 Second-stage node of negative booster circuit 25 Third-stage gate node of negative booster circuit 26 Third-stage node of negative booster circuit 27 Fourth-stage gate node of negative booster circuit 28 4 of negative booster circuit First-stage nodes 31 to 38 Capacities constituting negative booster circuit 41 to 48 N-channel MOS transistor 49 Parasitic bipolar transistor of N-channel MOS transistor 51 First-stage gate node of negative booster circuit 52 Negative booster circuit 1 Node 53 of the second stage Gate node of the second stage of the negative booster circuit 54 Node of the second stage of the negative booster circuit 55 Gate of the third stage of the negative booster circuit 56 Third-stage node of negative booster circuit 57 Node of fourth-stage gate of negative booster circuit 58 Fourth-stage node of negative booster circuit 61-68 Capacitance 75 Base current of parasitic bipolar transistor 76 Parasitic bipolar Transistor collector current 81-88 N-channel MOS transistor 91 First-stage gate node of negative booster circuit 92 First-stage node of negative booster circuit 93 Second-stage gate node of negative booster circuit 94 Negative booster circuit 95 The third-stage gate node of the negative booster circuit 96 The third-stage node of the negative booster circuit 97 The fourth-stage gate node of the negative booster circuit 98 The fourth-stage node of the negative booster circuit 101-108 Capacitance constituting negative booster circuit 111-118 P-channel MOS transistor

Claims (2)

[Claims] 1. A charge pump type negative booster circuit for generating a negative high voltage from a low voltage, comprising a triple well process using an N-channel MOS transistor. By independently setting the substrate potentials in a floating state, it is possible to suppress a rise in the threshold value of the transistor due to the substrate bias effect and to suppress the collector current of the parasitic NPN transistor due to the forward current from the substrate due to the boosting operation. Characteristic negative booster circuit. 2. When the substrate potential of the N-channel MOS transistor is not operating, the P-channel MOS transistor is connected to the ground potential so that the threshold voltage of the transistor increases due to the substrate bias effect when the boosting operation is started. 2. The negative booster circuit according to claim 1, wherein the voltage is suppressed.