JP2000002892A - Liquid crystal display device, matrix array substrate, and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix array substrate improved in a manufacturing yield by reducing the necessary number of masks required for manufacture and simplifying the manufacturing process. SOLUTION: After scanning lines 26, signal lines 33, a 1st gate insulating film 28, a 2nd gate insulating film 29, a semiconductor coating 41, a channel protective coating, a low-resistance semiconductor coating 44, and Mo/Al/Mo laminated film 47 have been formed, an array substrate 21 is to be formed in block with a source electrode 48, a drain electrode 9, a signal line 33, a semiconductor film 39, and a low-resistance semiconductor film 40 by patterning using the same mask pattern. Moreover, the upper surfaces of the source electrode 48, drain electrode 49, semiconductor film 39, scanning lines pad 30, and signal conductor pad 34 are to be covered with picture element electrodes 35. Moreover, the outlines of the source electrode 48, the low-resistance semiconductor film 40 and the semiconductor film 39 are approximately matched with each other, and the outlines of the drain electrode 49, low-resistance semiconductor film 40, and semiconductor film 39 are approximately matched with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a matrix array substrate used for a liquid crystal display device, a flat display device and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, a CRT (Cathord Ray) has been developed.
A flat-panel display device that replaces a Tube) display has been actively developed. Among them, a liquid crystal display device is superior in terms of lightness, thinness, low power consumption, and the like.
Especially attracting attention.

For example, an active matrix type liquid crystal display device in which a switch element is disposed for each display pixel will be described as an example. A liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. It has a structure. The array substrate is composed of signal lines and scanning lines arranged in a grid on a transparent insulating substrate such as glass or quartz, and switch elements arranged near intersections of these signal lines and scanning lines.
For example, TFT (Thin Film Transist)
or the active layer of the TFT is formed of a semiconductor thin film such as amorphous silicon (a-Si: H).

A gate electrode of a TFT is connected to a scanning line, a drain electrode is connected to a signal line, and a source electrode is a transparent conductive material, for example, an ITO film (Indium Tin Ox).
ide).

[0005] The counter substrate has a counter electrode made of an ITO film formed on a transparent insulating substrate. In order to enable color display, for example, a color filter layer is provided between the counter electrode of the counter substrate and the insulating substrate.

FIG. 13 is a diagram showing a cross-sectional structure of a matrix array substrate used in a conventional liquid crystal display device, and FIGS.
FIG. 5 is a view illustrating a conventional array substrate manufacturing process.
FIGS. 14 and 15 show a cross-sectional structure of the TFT region and the scanning line pad region on the array substrate. Hereinafter, based on these drawings, a conventional process of manufacturing an array substrate will be described step by step.

First, as shown in FIG. 14A, a gate electrode 2 on a glass substrate 1, a gate electrode 2, and a scan which includes a scan line pad region at an end and is electrically connected to the gate electrode 2 Form line 3. Next, as shown in FIG. 14B, after forming the gate insulating film 4 on the upper surface of the substrate, the semiconductor layer 5 made of a-Si: H or the like is formed on the upper surface. Next, after an insulating film 6 acting as an etch stopper layer is formed on the upper surface of the semiconductor layer 5, the insulating film 6 is patterned.

Next, as shown in FIG. 14C, n ⁺ a
After forming the low-resistance semiconductor layer 7 such as -Si: H, the semiconductor layer 5 and the low-resistance semiconductor layer 7 are patterned. next,
As shown in FIG. 14D, the pixel electrode 8 is formed.

Next, as shown in FIG. 15A, a contact hole 9 is formed in the gate insulating film 4 on the pad region of the scanning line 3. Next, as shown in FIG. 15B, a source electrode 10 and a drain electrode 11 are formed. Next, FIG.
As shown in FIG. 5C, the substrate is covered with the protective film 12 except for the pixel electrode on the upper surface and the pad region.

[0010]

In the conventional manufacturing process shown in FIGS. 14 and 15, the exposure and development patterning of the photoresist are required at least seven times as described above, and the manufacturing is troublesome and the photolithography is troublesome. There is a problem that the production cost is increased due to the large amount of the resist and the constituent materials used.

Japanese Patent Application Laid-Open No. Hei 5-190571 discloses a manufacturing process in which a TFT having an etch stopper layer (hereinafter referred to as a channel protection type TFT) is used to reduce the number of times of patterning. . Japanese Patent Application Laid-Open No. 61-161664 discloses a TFT having no etch stopper layer (hereinafter referred to as a back channel cut type TFT).
Called. ) Discloses a manufacturing process in which the number of times of patterning is reduced.

However, in each of the above publications, only the TFT portion is disclosed, and how to reduce the total man-hour is not sufficiently studied.

The present invention has been made in view of the above points, and has as its object to reduce the number of masks required at the time of manufacturing to simplify the manufacturing process and to increase the manufacturing yield without lowering the manufacturing yield. An object of the present invention is to provide a liquid crystal display device, a matrix array substrate, and a method for manufacturing the same, which can ensure productivity.

[0014]

According to a first aspect of the present invention, there is provided a scanning line including a gate electrode portion disposed on an insulating substrate, and a scanning line including a gate electrode portion of the scanning line. A semiconductor film disposed via an insulating film, a signal line electrically connected to the semiconductor film via a drain electrode, a source electrode electrically connected to the semiconductor film, and a A pixel electrode that is electrically connected;
A matrix array substrate comprising: a counter substrate disposed to face the matrix array substrate; and a liquid crystal layer held between the matrix array substrate and the counter substrate via an alignment film. In the liquid crystal display device, the alignment film is arranged on at least the pixel electrode and the signal line of the matrix array substrate, in direct contact with the pixel electrode and the signal line.

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising: a scanning line including a gate electrode portion disposed on an insulating substrate; and a semiconductor film disposed on the gate electrode portion of the scanning line via an insulating film. A signal line electrically connected to the semiconductor film via a drain electrode, a source electrode electrically connected to the semiconductor film, and a pixel electrode electrically connected to the source electrode. Matrix array substrate,
The signal line includes a first signal line layer mainly composed of aluminum, and tantalum, titanium,
At least one selected from tungsten and vanadium
And a second signal line layer made of two materials. Claim 10
The described invention provides a scanning line disposed on a substrate, an insulating film disposed on the scanning line, a semiconductor film disposed on the insulating film, and a source electrode electrically connected to the semiconductor film. A thin film transistor device having a drain electrode, a signal line electrically connected to the drain electrode, and a pixel electrode electrically connected to the source electrode;
A method of manufacturing a matrix array substrate comprising: a first step of sequentially depositing a semiconductor film and a channel protective film on the insulating film; and a second step of patterning the channel protective film to form a channel protective film. A third step of forming openings in the semiconductor film and the insulating film corresponding to pads for externally connecting the scanning lines; and depositing a first conductive layer on an upper surface of the substrate to form the thin film transistor device. The first conductive layer and the semiconductor film are patterned using the same mask pattern corresponding to locations, and the lower conductive layers of the source electrode, the drain electrode, and the signal line are collectively formed. And a fourth step of forming the semiconductor film, and patterning after forming a second conductive layer on the upper surface of the substrate, and forming the second conductive layer on the lower conductive layer. In the fifth step and the method of manufacturing a matrix array substrate, characterized in that it comprises forming the pixel electrode to form the conductive layer.

The invention according to claim 11 is a semiconductor device, comprising: a scanning line disposed on a substrate; an insulating film disposed on the scanning line; a semiconductor film disposed on the insulating film; A matrix array substrate comprising: a thin film transistor device having a source electrode and a drain electrode electrically connected to each other; a signal line electrically connected to the drain electrode; and a pixel electrode electrically connected to the source electrode. A first step of sequentially depositing a semiconductor film and a channel protective film on the insulating film; a second step of patterning the channel protective film to form the channel protective film; A third step of forming a first conductive layer on the upper surface of the channel protective film, and the first conductive layer and the Fine said semiconductor film is patterned using the same mask pattern, the source electrode, the fourth forming said semiconductor film so as to form collectively a lower conductive layer of the drain electrode and the signal line
A step of forming an opening in the insulating film corresponding to a pad for externally connecting the scanning line; and forming a second conductive layer on the upper surface of the substrate and then patterning the lower conductive layer. Forming an upper conductive layer disposed on the layer and forming the pixel electrode. 6. A method for manufacturing a matrix array substrate, comprising:

According to still another aspect of the present invention, a scanning line disposed on a substrate, an insulating film disposed on the scanning line, a semiconductor film disposed on the insulating film, and an electric A matrix array substrate comprising: a thin film transistor device having a source electrode and a drain electrode electrically connected to each other; a signal line electrically connected to the drain electrode; and a pixel electrode electrically connected to the source electrode. In the manufacturing method, the first step of forming a semiconductor film on the insulating film, the second step of forming a first conductive layer on the upper surface of the semiconductor film, A semiconductor coating and the first
Patterning the conductive film using the same mask pattern, forming the source electrode, the drain electrode and the lower conductive layer of the signal line collectively, and forming the semiconductor film; A fourth step of forming an opening in the semiconductor film and the insulating film corresponding to a pad for externally connecting a scanning line; and forming a second conductive layer on the upper surface of the substrate and then patterning the lower layer. A fifth step of forming an upper conductive layer disposed on the conductive layer and forming the pixel electrode.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A matrix array substrate according to one embodiment of the present invention, a method for manufacturing the same, and a liquid crystal display device using the matrix array substrate will be specifically described with reference to the drawings. The following matrix array substrates are all used for liquid crystal display devices,
Needless to say, it can be used for other purposes such as for an imaging device.

(First Embodiment) FIG. 1 is a layout diagram of a first embodiment of a matrix array substrate, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG. FIG.

As shown in FIG. 2, the liquid crystal display device according to the present embodiment comprises an array substrate 21 and a counter substrate 22 which are aligned with an alignment film 2.
The liquid crystal layer 23 has a structure in which the liquid crystal layer 23 is interposed therebetween so as to sandwich the liquid crystal layer 23 therebetween. The liquid crystal layer 23 is made of twisted nematic liquid crystal, and the alignment film 24 is subjected to an alignment process in directions orthogonal to each other. A polarizing plate 25 is attached to the outer surfaces of the array substrate 21 and the counter substrate 22.

As shown in FIGS. 1 and 2, the array substrate 21 includes a first scanning line 26 formed on the glass substrate 1 and a first silicon oxide (SiO ₂ ) film formed on the upper surface of the scanning line 26. It has a gate insulating film 28 and a second gate insulating film 29 made of a silicon nitride (SiNx) film formed on the upper surface of the first gate insulating film 28. The silicon oxide (SiO ₂ ) film serving as the first gate insulating film 28 ensures etching selectivity in various processes to be described later, and the silicon nitride (SiNx) film serving as the second gate insulating film 29 is used as a semiconductor layer. To form a good interface.

The scanning lines 26 are, for example, 8
00 are formed. Each scanning line 26 is connected to a connection end 26b drawn out to one end side of the glass substrate 1 via a scanning line diagonal wiring portion 26a, and a scanning line pad 30 shown in FIG. 1 is formed on the connection end 26b. .

The scanning line 26 has an auxiliary capacitance section 27 and a gate electrode section. Further, as shown in FIG. 3, the scanning line diagonal wiring portion 26a includes a first conductive layer 26a 'and a second conductive layer 26a.
a ″ and the third conductive layer 26A. Similarly, the scanning line pad 30 also includes the first conductive layer 30a and the second conductive layer 30b.
And a third conductive layer 30c. First conductive layer 26
a ′ and 30a are made of, for example, a Mo / Al / Mo laminated film, and the second conductive layers 26a ″ and 30b are made of the same material (for example, an ITO film) as the pixel electrode.
0c is formed by extending the scanning line 26.

The array substrate 21 has signal lines 33 arranged in a direction substantially orthogonal to the scanning lines 26 on the glass substrate 1.
Having. The signal line 33 is, for example, 10
24 × 3 are formed. Each signal line 33 is connected to a connection end 33b drawn out to one end side of the glass substrate 1 via a signal line diagonal wiring portion 33a, and a signal line pad 34 is formed on the connection end 33b.

The signal line 33, the signal line oblique wiring portion 33a, and the signal line pad 34 also have first, second, and third conductive layers, like the scanning line pad 30 and the like.

A TFT 20 for displaying a pixel is formed near the intersection of the scanning line 26 and the signal line 33. TFT2
The gate electrode portion of 0 is formed integrally with the scanning line 26, and the pixel electrode 35 is connected to its source electrode.

On the other hand, the opposing substrate 22 opposing the array substrate 21 has a resin light-shielding film 36 formed in a matrix on the glass substrate 100 as shown in FIG. The light-shielding film 36 is for shielding the region where the TFT 20 is formed, the signal line 33 and the gap between the scanning line 26 and the pixel electrode 35 from light. In addition, red (R), green (G) and blue (B) color filters 37 are arranged in regions facing the pixel electrodes 35, respectively. A counter electrode 38 made of a film is provided.

In the present embodiment, when forming a contact hole in the signal line pad 34, the outline of the signal line 33
The respective outlines of the semiconductor film 39 and the low-resistance semiconductor film 40 formed on the lower surface thereof are substantially matched. More specifically, the end face of the signal line 33 is set at 0. 0 from the end face of the semiconductor film 39.
The inner wall of the contact hole is formed in a tapered shape by being formed inside of 5 to 2 μm.

Since the signal line 33 and the source electrode and the drain electrode of the TFT 20 each have the second conductive layer made of the same material as the pixel electrode 35, the disconnection defect is reduced and the signal line 33 forming the signal line 33 is formed. An impurity such as an oxide of Mo, which is a material of the one conductive layer, is prevented from diffusing into the liquid crystal layer 23 to cause display failure. This second conductive layer is
The conductive layer is disposed so as to completely cover the conductive layer, but may be disposed on a part of the conductive layer. However, it is desirable that the signal line portion covers about 20% or more of the first conductive layer. From the viewpoint of preventing an undesired short circuit with the pixel electrode 35, it is desirable that the width of the second conductive layer is slightly smaller than that of the first conductive layer.

FIGS. 4 and 5 are views showing the steps of manufacturing the array substrate 21 of this embodiment. Hereinafter, the manufacturing process of the array substrate 21 of the present embodiment will be described in order with reference to FIGS. First, Al-N is formed on a glass substrate 1 by sputtering.
A d alloy film and a Mo film are sequentially formed. The thicknesses of the Al—Nd alloy film and the Mo film are about 200 nm and about 30 nm, respectively. Instead of this Al-Nd alloy film, another Al alloy film or an Al film can be used. Mo film is made of Al
It suppresses hillocks generated on the film or the Al alloy film and realizes good taper processing. A film thickness of 10 to 100 nm is sufficient. A resist is applied thereon, dried, exposed using a first mask pattern, developed, patterned, and
As shown in (a), the first of the 800 scanning lines 26, the scanning line diagonal wiring part 26a and the signal line diagonal wiring part 33a.
A conductive layer and first conductive layers of the pad portions 30 and are formed.

Next, as shown in FIG. 4B, a first gate insulating film 28 made of a silicon oxide film having a thickness of about 300 nm and a second gate made of a silicon nitride film having a thickness of about 50 nm are formed by low pressure plasma CVD. An insulating film 29, a semiconductor film 41 of about 50 nm thick a-Si: H,
Channel protective film 4 made of a 0-nm-thick silicon nitride film
2 is continuously formed without being exposed to the atmosphere. The silicon oxide film forming the first gate insulating film 28 includes two film forming steps. After the first layer is formed by the low pressure plasma CVD method, the surface is washed once, and then the second layer is formed again. It is formed by forming a film by a low pressure plasma CVD method. Thereby, interlayer short-circuit is greatly reduced. As the semiconductor film 41, various silicon-based semiconductors such as polycrystalline Si and microcrystalline Si can be used in addition to a-Si: H.

Next, a resist is applied thereon and dried, and as shown in FIG. 4C, the substrate is exposed from the back surface of the substrate using the scanning lines 26 as a mask, and a second mask pattern disposed on the substrate is provided. After exposing and developing using, the channel protective film is patterned to form an island-shaped channel protective film 43 only at the location where the TFT 20 is to be formed.

Next, as shown in FIG. 4D, the exposed surface of the semiconductor film 41 is treated with hydrofluoric acid so that a good ohmic contact can be obtained.
According to the D method, an n-type semiconductor having a thickness of about 30 nm containing phosphorus as an impurity is formed.
^A low resistance semiconductor film 44 made of ⁺ a-Si: H is deposited.

Next, a resist is applied thereon and dried,
As shown in FIG. 5A, exposure and development are performed by using the third mask pattern, and the first region corresponding to the connection end 26b of the scanning line 26 and the first region of the region corresponding to the connection end 33b of the signal line 33 are formed. Then, the contact holes 45 and 46 are formed by removing the second gate insulating films 28 and 29, the semiconductor film 41, and the low-resistance semiconductor film 44. At this time, in order to remove the semiconductor film 41 and the low-resistance semiconductor film 44, CDE (Chemical Dry Etching) is performed.
Alternatively, dry etching such as PE (Plasma Etching) is performed to form the first and second gate insulating films 2.
In order to remove 8, 29, wet etching is performed using BHF (buffered hydrofluoric acid) or the like. As described above, by using both dry etching and wet etching, the contact holes 45 and 46 are formed in a relatively good tapered shape.

Next, as shown in FIG.
Mo (molybdenum) layer, Al thickness about 350 nm
A laminated film 47 composed of an (aluminum) layer and a Mo layer having a thickness of about 50 nm is formed by a sputtering method. This lower Mo layer is for obtaining a good ohmic contact with the low-resistance semiconductor film 44, and can be replaced with another refractory metal. The upper Mo layer suppresses the surface reflection of the Al layer and the generation of hillocks generated in the Al layer. An Al alloy such as an Al-Nd alloy may be used instead of Al.

Next, a resist is applied thereon and dried,
As shown in FIG. 5C, exposure and development are performed using the fourth mask pattern, the mixed acid is used with phosphoric acid, nitric acid, acetic acid and water, and the etching time is further adjusted to adjust the side etching amount. Then, the Mo / Al / Mo laminated film 47 is etched. Further, by controlling the etching selectivity between the second gate insulating film 29 made of a silicon nitride film and the channel protective film 43, the low-resistance semiconductor film 44 and the semiconductor film 41 are collectively patterned by the plasma etching method. Thereby, the semiconductor film 39 forming the active layer of the TFT 20, the low-resistance semiconductor film 40 for obtaining a good ohmic contact, and the source electrode 4
8 and a first conductive layer 48 constituting a part of the drain electrode 49
a, 49a, and the first conductive layers 30b, 34b constituting a part of the scanning line pad 30 and the signal line pad 34 are collectively formed.

Next, as shown in FIG. 5D, in an Ar gas atmosphere to which H ₂ O, H ₂ , or O ₂ gas is added on the upper surface of the substrate, for example, in this example, an Ar atmosphere to which H ₂ O is added. An ITO film of an amorphous phase having a thickness of about 40 nm is deposited by sputtering in the inside, and exposure, development and patterning are performed using a fifth mask pattern. As an etchant for the ITO film, a solution that does not etch Al, for example, an oxalic acid aqueous solution is used. In addition, RIE (Reactive) of HI gas system or CH ₄ / H ₂ gas system
e Ion Etching) is also effective.

Thus, even if a pinhole or the like exists in the gate insulating film, the first conductive layer of the scanning line 26, the scanning line oblique wiring portion 26a and the signal line oblique wiring portion 33a, and the first conductive layer of the pad portions 30 and 34 Corrosion of one conductive layer and disconnection are prevented. The amorphous phase ITO film is reduced in resistance by performing a heat treatment in a later step. This IT
Instead of the O film, IZO (Indium Zinc Ox)
ide) films can also be used, which eliminates the need for a heat treatment step.

Thus, the scanning line 26 and the signal line 33
The pixel electrode 35 is formed between them. The patterned ITO film becomes a second conductive layer that constitutes each of the signal line 33, the source electrode 48, and the drain electrode 49. In FIG. 5D, reference numerals 30a and 34a denote second conductive layers constituting a part of the scanning line pad 30 and the signal line pad 34.
Thus, the second conductive layers forming part of the source electrode 48 and the drain electrode 49 are denoted by reference numerals 48b and 49b.

Next, as shown in FIG. 2, an alignment film 23 made of polyimide and having a thickness of 50 nm after drying is formed on the upper surface of the array substrate. Similarly, the opposing substrate 22 having the alignment film 23 formed on the upper surface of the substrate is disposed to face with a predetermined gap via a sealing material (not shown), and the liquid crystal layer 24 is injected between the two substrates and sealed. Further, the polarizing plates 25 are arranged on the outer surfaces of the substrates, respectively, to complete the liquid crystal display device.

When comparing the manufacturing process of the array substrate 21 of the first embodiment shown in FIGS. 4 and 5 with the manufacturing process of the conventional array substrate 21 shown in FIGS. Before the pixel electrode 35 made of the ITO film is formed, contact holes 45 and 46 are formed at the connection ends 30a and 32a of the scanning line 30 and the signal line 33, respectively, and then Mo as a material of the source electrode 48 and the like is formed. / Al / Mo laminated film 47
Is formed, patterning is performed, and a semiconductor film 39 and a low-resistance semiconductor film 40 and a first conductive layer constituting each part of the source electrode 48, the drain electrode 49, and the signal line 33 are collectively formed. This is different from the conventional manufacturing process.

By adopting such a manufacturing process, the required number of mask patterns can be reduced from the conventional seven to five. Further, since the signal line 33 and the source electrode 48 and the drain electrode 49 of the TFT 20 are formed of the first conductive layer and the second conductive layer, which is the same material as the material forming the pixel electrode, the signal line 33 Disconnection failure can be prevented.

Further, the contours of the source electrode 48, the low-resistance semiconductor film 40 and the semiconductor film 39, and the drain electrode 4
9, the outline of the low-resistance semiconductor film 40 and the outline of the semiconductor film 39 are matched with each other.
9. Since the contour is finely reduced in the order of the low-resistance semiconductor film 40 and the electrode, when the second conductive layer is formed on the upper surface of the substrate in a subsequent step, a defect such as disconnection of the second conductive layer due to a step is caused. Is less likely to occur.

In the first embodiment, a-
Although the example in which the semiconductor film 39 is formed using Si: H as a material has been described, the semiconductor film 39 may be formed using polycrystalline Si as a material. Further, a drive circuit may be integrally formed in a peripheral region on the array substrate 21.

Further, even if the scanning line 26 is made of Al or an alloy of Al (for example, Al—Nd or Al—Y), the gate insulating film is made only of a silicon nitride film, and the contact hole is etched only by dry etching. Good.

FIG. 5D shows an example in which the pixel electrode 35 and the second conductive layer are formed of an ITO film. However, the pixel electrode 3 is formed by using an IZO film which is an alloy of In, Zn and O as a material.
5 or a second conductive layer may be formed. Since the IZO film can be formed in an amorphous state and can be etched with a weak oxalic acid, even if a low-resistance metal layer such as Al is formed under the IZO film, the metal layer can be etched by an etchant. Does not cause electrolytic corrosion or oxidation.

In the array substrate of this embodiment, the upper surfaces of the scanning line pads 30 and the signal line pads 34 are formed of an ITO film, which is the same material as the pixel electrodes 35, and are harder than those formed of Al or the like. Therefore, even if the material is undesirably scratched at the time of connection with an external circuit or the like, a short circuit failure between adjacent pads hardly occurs.

Further, according to the first embodiment described above,
Although the number of masks is small, it is possible to directly connect a layer forming a signal line and a layer forming a scanning line by, for example, a low-resistance metal wiring forming a signal line. For this reason,
As a measure against static electricity, the signal line and the scanning line can be electrically connected with a low contact resistance via a protection diode or the like.

In this embodiment, the ITO film forming the second conductive layer constituting each part of the source electrode 48 and the drain electrode 49 is formed of the source electrode 48 and the drain electrode 4.
9 covers the first conductive layer constituting each part. Accordingly, a short circuit between the source electrode 48 and the drain electrode 49 due to undesired conductive particles such as Mo oxide is reduced.

(Second Embodiment) The second embodiment differs from the first embodiment in the timing of forming contact holes 45 and 46 at the connection ends 26b and 31b of the scanning line 26 and the signal line 33. It is characterized by the following.

FIG. 6 is a cross-sectional view of the second embodiment of the array substrate 21 and shows a schematic cross-sectional structure of a channel protection type TFT portion, as in the first embodiment. FIG. 7 is a manufacturing process diagram of the second embodiment of the array substrate 21.
Hereinafter, based on FIG. 7, the manufacturing process of the second embodiment of the array substrate 21 will be described step by step.

First, an Al alloy film having a thickness of about 300 nm is deposited on an insulating substrate, for example, a glass substrate 1 by a sputtering method. This Al alloy film is, for example, an Al alloy film containing 2% of Nd atoms as in the above-described embodiment.
It is a film in which the generation of hillocks is sufficiently reduced in the thermal process. Then, as shown in FIG. 7A, the Al alloy film is patterned by photolithography using a first mask pattern to form a gate electrode portion, an auxiliary capacitance portion, and an oblique wiring portion drawn out to one end side (see FIG. 7A). (Not shown), and a scanning line 26 including a connection end 26b connected to the oblique wiring portion is formed. Although not shown, at the same time as the formation of the scanning lines 26, an Al alloy film is formed as a lower wiring on the oblique wiring portion and the pad portion of the signal line.

Next, as shown in FIG. 7B, a gate insulating film 51 made of a silicon nitride film having a thickness of about 300 nm and a-Si having a thickness of about 50 nm are formed by a low pressure plasma CVD method.
A semiconductor film 41 made of H and a channel protective film made of a silicon nitride film having a thickness of about 200 nm are continuously formed without being exposed to the air. The gate insulating film 51 may be replaced with a first gate insulating film made of a silicon oxide film having a thickness of about 300 nm and a second gate insulating film made of a silicon nitride film having a thickness of about 50 nm as in the first embodiment. Absent.

Next, the channel protective film 44 is patterned using the second mask pattern in the same manner as in the above-described embodiment to form the channel protective film 43, and after performing a pretreatment, the source / drain electrodes 48 are formed. , 49, an n ⁺ a of about 30 nm thick containing phosphorus as an impurity.
-Si: H low-resistivity semiconductor coating is applied to reduced-pressure plasma C
It is deposited by the VD method. Subsequently, the M
A laminated film consisting of three layers of o / Al / Mo is deposited.

Next, as shown in FIG. 7C, the laminated film is patterned by photolithography using a third mask pattern, and each of the signal line 33, the source electrode 48 and the drain electrode 49 is partially patterned. First conductive layer 4 constituting
8a and 49a are formed. Also, using the same mask pattern, the semiconductor film 41 is formed by a plasma etching method.
Then, the semiconductor film 39 and the low-resistance semiconductor film 40 are formed by patterning the low-resistance semiconductor film 44. Thereby, the signal line 33, the source electrode 48, the drain electrode 49,
Scanning line diagonal wiring part 26a and signal line diagonal wiring part 33
A conductive layer on the upper layer side of a is formed.

Next, as shown in FIG. 7D, the gate insulating film 51 in the region where the scanning line pad 30 is to be formed is plasma-etched using a fluorine-based gas using the fourth mask pattern. A contact hole 45 is formed by etching using a method.

Next, as shown in FIG. _{7 (e), H 2 O} ,
Ar gas added with H ₂ or O ₂ gas, for example, H
By depositing the amorphous phase ITO film to a thickness of 50 nm on the upper surface of the substrate by sputtering while maintaining the substrate temperature at a relatively low temperature by a sputtering method in an Ar atmosphere containing 2O, based on the fifth mask pattern, The pixel electrode 35 and the second conductive layer 4 forming each part of the signal line 33, the source electrode 48 and the drain electrode 49 are patterned.
8b and 49b, and the upper layer of the signal line 33 and the pad of the scanning line 26 are formed. The etching solution for the ITO film is A
A liquid that does not etch l, for example, an aqueous solution of oxalic acid is used. As another method of patterning the pixel electrode 35 or the second conductive layer, HI gas based or CH ₄ / H ₂ gas based RIE is also effective.

Next, similarly to the first embodiment, an alignment film is directly arranged to complete a liquid crystal display device.

As described above, in the second embodiment, after the source electrode 48, the drain electrode 49, the low-resistance semiconductor film 40, and the semiconductor film 39 are collectively patterned using the same mask pattern, the scanning line pad 30 is formed. And a point for forming a contact hole for the signal line pad 34, that is,
It is manufactured in the same manner as in the first embodiment except that the timing for forming the contact holes is different from that in the first embodiment. Therefore, similarly to the first embodiment, an array substrate can be manufactured with a smaller number of masks than in the related art. In addition, by using an IZO film instead of the ITO film as a material of the pixel electrode 35 and the second conductive layer, the scanning line and the signal line 33 are formed.
Is the same as the first embodiment in that a low-resistance metal such as Al can be used as the material of the first embodiment.

Further, the mask pattern used for patterning the ITO film shown in FIG.
The pixel electrode 35 may be formed without patterning the source electrode 48 and the drain electrode 49 by patterning the ITO film as shown in FIG. For example, when the wiring width of the laminated film (first conductive layer) composed of three layers of Mo / Al / Mo constituting the signal line 33 is 5 μm, the wiring width of the second conductive layer disposed thereon is 2 μm. And Thus, even if a mask shift of the second conductive layer with respect to the first conductive layer occurs, since the second conductive layer is always located in the first conductive layer, disconnection of the signal line 33 is prevented. In addition, since a gap between the pixel electrode and the second conductive layer patterned with the same mask can be sufficiently maintained, undesired conduction between the pixel electrode and the second conductive layer is prevented.

In this case, a part of the ITO film is replaced with the conductive layer 49b.
It is desirable to dispose on the signal line 33 (see FIG. 1) in order to prevent disconnection of the signal line 33.

(Third Embodiment) Next, another embodiment of the present invention will be described with reference to the drawings. In this embodiment, the pixel electrode positions are different from those in the second embodiment. FIG. 8B is a diagram showing a cross-sectional structure of the third embodiment of the array substrate, and FIG. 9 is a diagram showing a manufacturing process thereof.

In the third embodiment, FIGS.
After the steps (FIGS. 9A and 9B) up to (b),
An n ⁺ -type a-Si: H low-resistance semiconductor film of about 5
It is formed to a thickness of 0 nm by low pressure plasma CVD. Thereafter, CDE is performed using a mixed gas of CF ₄ and O ₂ to pattern the semiconductor film 41 and the low-resistance semiconductor film. More specifically, patterning is performed based on the third mask pattern so that the semiconductor film 41 and the low-resistance semiconductor film 44 remain in the TFT formation region and the signal line formation region.

Next, an ITO film is deposited by a sputtering method. More specifically, using a sintered ITO film target having a weight ratio% of In ₂ O ₃ and SnO ₂ of 90:10, A
Sputtering is performed with an r partial pressure of 0.4 Pa or more. In this case, good results can be obtained even if Kr is used instead of Ar. The H ₂ O partial pressure is, for example, 3.4 × 10 −3P
is set to a. Further, O ₂ may be used instead of H ₂ O. The substrate temperature is set to room temperature. That is, the temperature of the plate (susceptor) supporting the substrate is set to, for example, 60 ° C. This susceptor temperature is 2
Until the temperature reaches 00 ° C., the film quality of the ITO film is sufficiently amorphous.

The power density of the ITO film is 7.0 W / cm
^{The number of} reciprocations of the magnet is ^two or more, and the number of reciprocations of the magnet is one or more from the start of the sweep to the end of the sweep returning to the original position. In addition, ITO
The thickness of the film is desirably less than 80 nm. Further, it is desirable that the film formation time is completed between 20 seconds and 60 seconds in order to suppress the promotion of the ITO film to be crystallized.

Next, using the fourth mask pattern, the IT
The O film is patterned. Specifically, after applying a resist on the upper surface of the ITO film in order to pattern the ITO film, the outside of the pattern area is coated with a wet etching solution in which (HCOOH) ₂ is mixed at least 1% or more by 3.4% by weight. Is removed, and the resist is stripped with a strong alkaline solution (FIG. 9C).

Next, the patterned ITO film 35
Is heat-treated for the purpose of increasing the transmittance of the film on average.
The atmosphere conditions in this case are atmospheric pressure in nitrogen gas.
For example, if the substrate temperature is set to 230 ° C. or more and the processing time is set to 5 minutes or more, the transmittance sufficiently exceeds 80% to satisfy practicality.

Next, the contact hole 45 is formed by exposing, developing, and removing the gate insulating film 51 in the pad portion by plasma etching using a fluorine-based gas using the fifth mask pattern (FIG. 9).
(D)).

Next, the Mo layer is formed to a thickness of about 25n by sputtering.
m thickness. And 2.0 atom% in aluminum
Target mixed with neodymium, Ar gas and K
The gas pressure was adjusted to 1.3 Pa or less and the power to 40 kW or less using r gas, and the Al-Nd alloy layer was reduced to about 35
It is deposited to a thickness of 0 nm by a sputtering method. Mo on the top
The layer is formed to a thickness of about 50 nm by a sputtering method. At this time, Al, Al-Y, or Al-Gd may be used instead of the Al-Nd alloy layer. The shape of the taper of the wiring portion after the etching process changes depending on the combination of the material to be formed by sputtering and the film thickness.

Next, the resist is exposed and developed based on the sixth mask pattern, and the above laminated film is patterned by wet etching using a mixed acid of phosphoric acid, nitric acid and acetic acid, and a signal line (not shown) is formed. Then, the source and drain electrodes 48 and 49 are processed. At the same time, the channel protective film 4
The low-resistance semiconductor film on 3 is removed by a plasma etching method or the like using the source electrode 48 and the drain electrode 49 as a mask. An array substrate is formed by the above steps (FIG. 9E).

As described above, by preventing the ITO film from being formed on the upper surface of the source electrode 48 and the upper surface of the drain electrode 49, a problem that the ITO film is disconnected due to the step between the source electrode 48 and the drain electrode 49 occurs. As a result, the drain electrode 49 and the pixel electrode 35 can be reliably conducted.

Fourth Embodiment In the first to third embodiments, a laminated film 47 of Mo / Al / Mo is used as a material of a lower conductive layer of a source electrode 48 and a drain electrode 49 of a TFT. The material of the uppermost layer of the laminated film 47 is Mo (molybdenum). Mo has the property of easily dissolving in an alkaline solution or water, becoming an oxide, and re-adhering.
Mo oxide MoO ₂ is about 88 μm in bulk state.
It has a resistivity of Ω · cm and is conductive. Therefore,
When a voltage is applied to an electrode using Mo as the uppermost layer for a long time, the source electrode 48 and the drain electrode 49 are partially short-circuited via the oxide of Mo, and a leak current is generated between the source electrode 48 and the drain electrode 49. Will occur.

In the fourth and fifth embodiments described below, the source electrode 48 and the drain electrode 4 of the TFT are used.
The leakage current between the source electrode 48 and the drain electrode 49 is suppressed by using a metal having a high oxide resistivity, for example, V (vanadium) as the uppermost layer of the laminated film 47 which is the constituent material of No. 9. .

Hereinafter, a fourth embodiment will be described with reference to FIG. 9 according to the third embodiment.

First, an MoW film having a thickness of about 300 nm is deposited on the transparent glass substrate 1 on which the SiOx film is formed by the plasma CVD method, by the sputtering method. Subsequently, exposure, development, and first patterning are performed based on the first mask pattern. CD using CF ₄ + O ₂ mixed gas
E (chemical dry etching) is performed, and the MoW film is processed so as to form a taper of 35 degrees or less to form the gate electrode 26 (FIG. 9A).

Next, a pressure reduction plasma CVD method is used for about 30 minutes.
A silicon oxide film having a thickness of 0 nm and a silicon nitride film having a thickness of about 50 nm are deposited as a gate insulating film 51. Furthermore, SiH
50 nm by glow discharge of ₄ gas and hydrogen gas
A semiconductor film 41 made of a thick a-Si: H film, about 300
A channel protective film (not shown) made of a silicon nitride film having a thickness of nm is deposited continuously in four layers without being exposed to the air.
Then, the channel protection film is patterned by back exposure and second patterning to form a channel protection film 43 above the gate electrode 26 as in the above embodiment (FIG. 9B). Next, a low-resistance semiconductor film made of n ⁺ -type a-Si: H is reduced to about 50 nm thick by low-pressure plasma CVD by glow discharge of a hydrogen gas containing SiH ₄ gas and PH _3.
Is formed. Thereafter, CDE is performed using a mixed gas of CF ₄ and O ₂ to pattern the low-resistance semiconductor film. More specifically, patterning is performed so that the low-resistance semiconductor film 44 remains in the TFT formation region and the signal line formation region.

Next, an ITO film is deposited by a sputtering method. More specifically, using a sintered ITO film target having a weight ratio% of In ₂ O ₃ and SnO ₂ of 90:10, A
Sputtering is performed with an r partial pressure of 0.4 Pa or more. In this case, good results can be obtained even if Kr is used instead of Ar. The H ₂ O partial pressure is, for example, 3.4 × 10 −3P
is set to a. Further, O ₂ may be used instead of H ₂ O. The substrate temperature is set to room temperature. That is, the temperature of the plate (susceptor) supporting the substrate is set to, for example, 60 ° C. This susceptor temperature is 2
Until the temperature reaches 00 ° C., the thickness of the ITO film is sufficiently amorphous.

The power density of the ITO film is 7.0 W / cm
^{The number of} reciprocations of the magnet is ^two or more, and the number of reciprocations of the magnet is one or more from the start of the sweep to the end of the sweep returning to the original position. In addition, ITO
Desirably, the thickness of the film is less than 800 angstroms. Further, it is desirable that the film formation time is completed between 20 seconds and 60 seconds in order to suppress the promotion of the ITO film to be crystallized.

Next, using the third mask pattern, the IT
The O film is patterned. Specifically, after applying a resist on the upper surface of the ITO film in order to pattern the ITO film, the outside of the pattern area is removed with a wet etching solution in which (HCOOH) 2 is mixed at 3.4% by weight. The peeling is performed with a strong alkaline solution (FIG. 9)
(C)).

Next, the patterned ITO film 35
Is heat-treated for the purpose of increasing the transmittance of the film on average.
The atmosphere conditions in this case are atmospheric pressure in nitrogen gas.
For example, if the substrate temperature is set to 230 ° C. or more and the processing time is set to 5 minutes or more, the transmittance sufficiently exceeds 80% to satisfy practicality.

Next, the gate insulating film 51 in the pad portion is removed by using the fourth mask pattern to remove the contact hole 4.
5 is formed (FIG. 9D).

Next, the Mo layer is formed to a thickness of about 25n by sputtering.
m thickness. And 2.0 atom% in aluminum
Target mixed with neodymium, Ar gas and K
The gas pressure was adjusted to 1.3 Pa or less and the power to 40 kW or less using r gas, and the Al-Nd alloy layer was reduced to about 35
It is deposited to a thickness of 0 nm by a sputtering method. A vanadium layer is formed to a thickness of about 50 nm on the upper surface by sputtering using an Ar gas or a Kr gas with a gas pressure of 1.3 Pa or less and a power of 15 kW or less, using vanadium as a target. At this time, Al, Al-Y, or Al-Gd may be used instead of the Al-Nd alloy layer, and V as the material of the lowermost layer of the laminated film instead of Mo.
May be used. The shape of the taper of the wiring portion after the etching process changes depending on the combination of the material to be formed by sputtering and the film thickness.

Next, the resist is exposed and developed based on the fifth mask pattern, and the above-mentioned laminated film is patterned by wet etching using a mixed acid of phosphoric acid, nitric acid and acetic acid, and a signal line (not shown) is formed. Then, the source and drain electrodes 48 and 49 are processed. At the same time, the channel protective film 4
The low-resistance semiconductor film on 3 is removed by a plasma etching method or the like using the source electrode 48 and the drain electrode 49 as a mask. An array substrate is formed by the above steps (FIG. 9E).

As described above, in the fourth embodiment, since the uppermost layer 47c of the source electrode 48 and the drain electrode 49 of the TFT is formed of vanadium, a leak current flowing between the source electrode 48 and the drain electrode 49 can be suppressed. The electrical characteristics of the TFT are improved. Further, the vanadium can prevent aluminum and the like in the lower conductive layer from diffusing into the liquid crystal layer 23.

(Fifth Embodiment) In the fifth embodiment, the I
The order of forming the TO film 35 is different from that of the fourth embodiment, and the source electrode 48 and the drain electrode 49 of the TFT are different.
Is covered with an ITO film 35.

FIG. 10 is a view showing the manufacturing process of the fifth embodiment of the array substrate. Hereinafter, the manufacturing process of the fifth embodiment of the array substrate will be described with reference to FIG.

After the MoW film is formed on the transparent glass substrate 1 on which the SiOx film is adhered, the MoW film is processed into a tapered shape by patterning based on the first mask pattern to form the gate electrode 26 (FIG. 10 ( a)). Next, a gate insulating film 51 is deposited on the upper surface (FIG. 10).
(B)).

Next, a semiconductor film 41 is formed on the upper surface of the gate insulating film 51, and a silicon nitride layer is formed on the upper surface thereof as a channel protective film. Next, the channel protection film is patterned based on the second mask pattern to form the channel protection film 43 (FIG. 10C).

The above steps are the same as in the fourth embodiment. In the fifth embodiment, a low-resistance semiconductor film and a Mo / Al-Nd / V laminated film are formed on the upper surface, and then the laminated film, the low-resistance semiconductor film, and the semiconductor film are formed by patterning based on a third mask pattern. 41 are collectively patterned (FIG. 10D).

Thereafter, the gate insulating film 51 in the pad portion is removed based on the fourth mask pattern to form a contact hole 45 (FIG. 10E), and then an ITO film is deposited by a sputtering method. The pixel electrode 35 is formed by performing patterning based on the mask pattern of FIG.
0 (f)).

As described above, in the fifth embodiment, the TFT
Since the upper surfaces of the source electrode 48 and the drain electrode 49 are covered with the ITO film 35, both electrodes can be protected by the ITO film 35, and a passivation film for protection is not required, and the manufacturing process can be simplified. Since the uppermost layer 47c of the lower conductive layer of the source electrode 48 and the drain electrode 49 is formed of vanadium as in the fourth embodiment, a part of the lower conductive layer is diffused into the liquid crystal layer 23. And the leakage current flowing between the source electrode 48 and the drain electrode 49 can be suppressed.

(Sixth Embodiment) In the first to fifth embodiments, a channel protective film is disposed above a gate electrode.
Although a matrix array substrate using a so-called channel protective film type TFT has been described, the number of times of patterning can be further reduced by employing a back channel cut type TFT as a switch element of the matrix array substrate.

FIG. 11 is a view showing the manufacturing process of the sixth embodiment of the array substrate. Hereinafter, the manufacturing process of the sixth embodiment of the array substrate will be described with reference to FIG.

First, a MoW alloy film having a thickness of about 230 nm is laminated on the glass substrate 1 by a sputtering method, and is exposed, developed and first patterned by using a first mask pattern. 480 scanning lines 26 and 480 auxiliary capacitance lines 26 'including the connection ends drawn out on the side are formed (FIG. 11A).

Next, a low pressure plasma CVD method is used
After depositing a first gate insulating film 28 made of a 50 nm thick silicon oxide film, a second gate insulating film 29 made of a silicon nitride film having a thickness of about 50 nm is further formed.
(B)). Next, a semiconductor film of about 250 nm thick a-Si: H and a low-resistance semiconductor film of about 50 nm thick n ⁺ a-Si: H containing phosphorus as an impurity are formed.
The film is formed by a CVD method without being continuously exposed to the atmosphere. Thereafter, each has a thickness of 25 nm, 350 nm, 50
Mo / Al / Mo laminated films 47a, 47b, 47 having a thickness of nm
c is deposited by a sputtering method.

Next, the Mo / Al / Mo laminated films 47a, 47
7b, 47c, a low-resistance semiconductor film, a semiconductor film,
The second gate insulating film 29 made of a silicon nitride film is collectively processed by patterning using a second mask pattern, and the signal line region and the TFT region are patterned in an island shape (FIG. 11C). ). Specifically, Mo / Al
/ Mo laminated film 47 is wet-etched with a mixed acid of phosphoric acid, nitric acid, and acetic acid, and then plasma-etched using SF ₆ / O ₂ / HCl gas to form a low-resistance semiconductor film,
The semiconductor film and the gate insulating film 29 are collectively patterned to form a low-resistance semiconductor film 40 and a semiconductor film 39.
To form

Next, after exposing and developing using the third mask pattern, third patterning is performed by wet etching using BHF to form a contact hole 45 on the scanning line pad (FIG. 11 ( d)).

Next, the substrate temperature is reduced to 150 ° C. or lower, and H ₂
While introducing O, I of about 40 nm thickness is sputtered.
A TO film is formed on the upper surface of the substrate. Next, after performing exposure and development using a fourth mask pattern, fourth patterning is performed to form a source electrode 48 and a drain electrode 49 of the TFT and a pixel electrode 35, and thereafter, wet etching or the like is performed. As a result, the source electrode 48 and the drain electrode 49 are separated, and at the same time, the low-resistance semiconductor film is etched to form the back channel portion 50. (FIG. 11 (e)).

For etching the ITO film 35, 3% oxalic acid containing a surfactant is used. Further, in the back channel portion 50 of the TFT, after the Mo / Al / Mo laminated film 47 is removed by etching with a mixed acid of phosphoric acid, nitric acid and acetic acid, the low-resistance semiconductor film is etched with SF ₆ / HCl to form a source electrode. 48 and the drain electrode 49 are separated.

Next, by performing a heat treatment at about 230 ° C. for about 30 minutes, the ITO film 35 is changed from an amorphous state to a polycrystalline state, and at the same time, the TFT characteristics are stabilized. At the same time, a signal line connection pad 34 that is electrically connected to the signal line 33 and made of the same material as the pixel electrode 35 is formed at a position where the contact hole 45 is formed.

After patterning the ITO film 35, the resist is peeled off, and the ITO film is changed from an amorphous state to a microcrystalline state by heat treatment, and the Mo / Al / Mo laminated film 47 is formed using the ITO film as a mask. And patterning of the low-resistance semiconductor film.

Next, the alignment film 24 is formed on the upper surface of the ITO film 35 to complete the array substrate. Next, the completed array substrate is bonded to a counter substrate having an alignment film formed on the upper surface with a liquid crystal layer interposed therebetween, thereby completing a liquid crystal display device as shown in FIG. Thus, in the seventh embodiment,
The Mo / Al / Mo laminated film, the low-resistance semiconductor film, and the semiconductor film are collectively patterned to form a signal line region and T
By forming an FT region and eliminating the need for a protective film,
The number of times of exposure and patterning can be reduced to four times, and the manufacturing process can be simplified.

Further, by reducing the number of times the mask pattern is used, a mask shift is less likely to occur, and variations in the parasitic capacitance of the signal line, the scanning line, and the TFT portion can be suppressed.
Therefore, a liquid crystal display device having a high resolution and a high aperture ratio can be obtained.

(Seventh Embodiment) The seventh embodiment is a modification of the sixth embodiment, and is an array substrate using a back channel cut type TFT, and has a source electrode 48 and a drain electrode of the TFT. The material of the uppermost layer 47c of 49 is vanadium.

With such a configuration, in the seventh embodiment, as in the fourth and fifth embodiments, the uppermost layer 47c of the source electrode 48 and the drain electrode 49 of the TFT is formed of vanadium. A leak current flowing between the source electrode 48 and the drain electrode 49 can be suppressed.

The Mo layer or the V layer which is the uppermost layer of the above-mentioned signal line, source electrode and drain electrode is made of tantalum (T
a), titanium (Ti), or tungsten (W). For example, when the uppermost layer 47c of the source electrode 48 and the drain electrode 49 is made of tantalum, the Mo / Al / Ta laminated film 47 is formed by a sputtering method, and then unnecessary by using CDE or a mixed acid of acetic acid, phosphoric acid and nitric acid. Tantalum is removed by wet etching.

The conditions for CDE include, for example, O ₂ and C
The gas ratio of F ₄ 1: 1 and then, the etching time to 60 seconds. The wet etching is performed, for example, at a liquid temperature of 35 ° C. and an etching time of 200 seconds.

On the other hand, the source electrode 48 and the drain electrode 49
When the uppermost layer 47c is made of titanium, the Mo / Al / Ti laminated film 47 is formed by the sputtering method, and then the EDT is formed.
A wet etching using A or wet etching using a mixed acid of nitric acid, acetic acid, hydrochloric acid and water is performed.

The conditions for the etching by EDTA are, for example, that the liquid temperature is 25 ° C. and the etching time is 12 hours.
Set to 5 seconds. The conditions for etching with the mixed acid include, for example, a liquid temperature of 35 ° C. and an etching time of 200 seconds.

As described above, by forming the uppermost layer 47c of the lower conductive layer of the source electrode 48 and the drain electrode 49 from a material such as tantalum, titanium, or tungsten, the leakage between the source electrode 48 and the drain electrode 49 can be improved. The current can be suppressed.

[0111]

As described above in detail, according to the present invention, since the alignment film is arranged in direct contact with the pixel electrodes and the signal lines on the matrix array substrate, the passivation film for protection is provided in the final step of the process. There is no need to form them, and the manufacturing process can be simplified. In addition, a plasma CVD apparatus for forming a passivation film is not required, and the manufacturing cost can be reduced.

The signal line has a two-layer structure, and the upper second
By manufacturing the signal line layer in the same process as the pixel electrode,
Further, the manufacturing process can be simplified.

Further, the signal line and the source electrode and the drain electrode of the thin film transistor device are connected to the first and second electrodes.
Since each of the conductive layers is formed and the second conductive layer is formed of the same material as that of the pixel electrode, disconnection failure of the signal line can be prevented. Further, when the present invention is applied to a liquid crystal display device, by forming a second conductive layer on the upper surface of the first conductive layer, the constituent material of the first conductive layer diffuses into the liquid crystal layer, resulting in display failure. Such a problem is solved.

Further, according to the present invention, since the source electrode, the drain electrode and the semiconductor film are collectively formed by patterning using the same mask pattern, the mask pattern necessary for manufacturing the array substrate is formed. The number can be reduced more than before, and the manufacturing cost and the number of manufacturing steps can be reduced.

Further, by reducing the number of times the mask pattern is used, a mask shift is less likely to occur, and variations in the parasitic capacitance of the signal line, the scanning line, and the TFT portion can be suppressed.
Therefore, a liquid crystal display device having a high resolution and a high aperture ratio can be obtained.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a first embodiment of an array substrate.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a manufacturing process diagram of the first embodiment of the array substrate.

FIG. 5 is a manufacturing process diagram following FIG. 4;

FIG. 6 is a sectional view of a second embodiment of the array substrate.

FIG. 7 is a manufacturing process diagram of the second embodiment of the array substrate.

FIG. 8 shows a modification of the second embodiment of the array substrate and a third embodiment.
The figure which shows the cross-section of embodiment of FIG.

FIG. 9 is a manufacturing process diagram of the fourth embodiment of the array substrate.

FIG. 10 is a manufacturing process diagram of the fifth embodiment of the array substrate.

FIG. 11 is a manufacturing process diagram of a sixth embodiment of an array substrate.

FIG. 12 is a sectional view of a liquid crystal display device having an array substrate according to a sixth embodiment.

FIG. 13 is a diagram showing a cross-sectional structure of a conventional array substrate.

FIG. 14 is a manufacturing process diagram of a conventional array substrate.

FIG. 15 is a manufacturing process diagram following FIG. 14;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Scanning line 4 Gate insulating film 5 Semiconductor layer 6 Insulating film 7 n ⁺ a-Si layer 21 Array substrate 22 Opposite substrate 23 Liquid crystal layer 24 Alignment film 25 Polarizer 26 Scanning line 27 Storage capacitance line 28 First gate insulating film 29 Second gate insulating film 30 Scan line pad 33 Signal line 34 Signal line pad 35 Pixel electrode 36 Light shielding film 37 Color filter 38 Counter electrode 39 Semiconductor film 40 Low resistance semiconductor film 41 Semiconductor film 42 Channel protective film 43 Channel protective film 44 low-resistance semiconductor film 45, 46 contact hole 47 laminated film 48 source electrode 49 drain electrode 26a ', 30a, 48a, 49a first conductive layer 26a ", 30b, 48b, 49b second conductive layer 26A, 30c 3 conductive layers

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiko Machida 50, Kamiyobe, Yobe-ku, Himeji-shi, Hyogo Prefecture Inside the Higashishiba Himeji Plant (72) Inventor Shigeyuki Motogawa 50, Kamiyobe, Himeji-shi, Hyogo Inside the Toshiba Himeji Plant (72) Inventor Takaaki Uemura 50 in the upper part of Yobe-ku, Himeji City, Hyogo Prefecture Inside the Toshiba Himeji Plant (72) Inventor Kiyoshi Tsuguuchi 50 in the upper part of Himeji-shi, Hyogo Prefecture Inside the Toshiba Himeji Factory (72) Inventor Tomoki Miyaji 50 inside the Himeji City, Hyogo Prefecture

Claims (16)

[Claims] A scanning line including a gate electrode portion disposed on an insulating substrate; a semiconductor film disposed on the gate electrode portion of the scanning line via an insulating film; and a drain electrode on the semiconductor film. A matrix array substrate comprising: a signal line electrically connected to the source electrode; a source electrode electrically connected to the semiconductor film; and a pixel electrode electrically connected to the source electrode; A liquid crystal display device comprising: a counter substrate disposed to face an array substrate; and a liquid crystal layer held between the matrix array substrate and the counter substrate via an alignment film. A liquid crystal display device, wherein the alignment film is disposed at least on the pixel electrode and the signal line in direct contact with the pixel electrode and the signal line. 2. The method according to claim 1, wherein the signal line includes a first signal line layer and the first signal line layer.
2. The liquid crystal display device according to claim 1, further comprising a second signal line layer laminated on the signal line layer and manufactured in the same step as the pixel electrode. 3. The liquid crystal display device according to claim 2, wherein at least 20% of the surface of the first signal line layer is covered with the second signal line layer. 4. The signal line layer includes a first layer mainly composed of aluminum, and a second layer disposed on the first layer, wherein the second layer includes tantalum, titanium, The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed of at least one material selected from tungsten and vanadium. 5. The liquid crystal display device according to claim 4, wherein said second layer is made of vanadium. 6. The pixel electrode is formed of a material mainly composed of an IZO film which is an alloy of indium (In), zinc (Zn) and oxygen (O), and the scanning line is made of a metal material mainly composed of aluminum. 2. The method according to claim 1, wherein
The liquid crystal display device as described in the above. 7. A scanning line including a gate electrode portion disposed on an insulating substrate, a semiconductor film disposed on the gate electrode portion of the scanning line via an insulating film, and a drain electrode on the semiconductor film. A signal line electrically connected to the semiconductor film, a source electrode electrically connected to the semiconductor film, and a pixel electrode electrically connected to the source electrode. The wire includes a first signal line layer mainly composed of aluminum, and a second signal line layer disposed on the first signal line layer and formed of at least one material selected from tantalum, titanium, tungsten, and vanadium. A matrix array substrate comprising: 8. The matrix array substrate according to claim 7, wherein said second signal line layer is made of vanadium. 9. The signal line includes a third signal line layer disposed on the second signal line layer, and the third signal line layer is formed of the same material and in the same process as the pixel electrode. The matrix array substrate according to claim 7, wherein: 10. A scanning line disposed on a substrate, an insulating film disposed on the scanning line, a semiconductor film disposed on the insulating film, a source electrode electrically connected to the semiconductor film, and A method for manufacturing a matrix array substrate, comprising: a thin film transistor device having a drain electrode; a signal line electrically connected to the drain electrode; and a pixel electrode electrically connected to the source electrode. A first step of sequentially depositing a semiconductor film and a channel protection film thereon, a second step of patterning the channel protection film to form a channel protection film, and a pad for externally connecting the scanning line. A third step of forming an opening in the semiconductor film and the insulating film; and depositing a first conductive layer on an upper surface of the substrate to form the thin film transistor device. The first conductive layer and the semiconductor film are patterned using the same mask pattern to form the source electrode, the drain electrode, and the lower conductive layer of the signal line at one time. And a fourth step of forming the semiconductor film together with forming a second conductive layer on the upper surface of the substrate and then patterning to form an upper conductive layer disposed on the lower conductive layer and to form the pixel electrode. A fifth step, and a method for manufacturing a matrix array substrate, the method comprising: 11. A scanning line disposed on a substrate, an insulating film disposed on the scanning line, a semiconductor film disposed on the insulating film, a source electrode electrically connected to the semiconductor film, and A method for manufacturing a matrix array substrate, comprising: a thin film transistor device having a drain electrode; a signal line electrically connected to the drain electrode; and a pixel electrode electrically connected to the source electrode. A first step of sequentially depositing a semiconductor film and a channel protection film thereon; a second step of patterning the channel protection film to form the channel protection film; and a second step of forming a channel protection film on the upper surfaces of the semiconductor film and the channel protection film. 1
A third step of forming a conductive layer; and patterning the first conductive layer and the semiconductor film using the same mask pattern in correspondence with the formation location of the thin film transistor device, thereby forming the source electrode and the drain electrode. And a fourth step of simultaneously forming the lower conductive layer of the signal line and forming the semiconductor film, and forming an opening in the insulating film corresponding to a pad for externally connecting the scanning line. A fifth step of forming a second conductive layer on the upper surface of the substrate and then patterning to form an upper conductive layer disposed on the lower conductive layer and form the pixel electrode. A method for manufacturing a matrix array substrate. 12. The method according to claim 11, wherein in the sixth step, the upper conductive layer is formed only on a part of the upper surface of the source electrode and the drain electrode. 13. A low-resistance semiconductor film is formed prior to the third step, and the first conductive layer, the low-resistance semiconductor film, and the semiconductor film are formed in the fourth step in accordance with a location where the thin film transistor device is formed. Patterning using the same mask pattern to collectively form the source electrode, the drain electrode, and the lower conductive layer of the signal line, and form the semiconductor film. A manufacturing method of the matrix array substrate described in the above. 14. A scanning line disposed on a substrate, an insulating film disposed on the scanning line, a semiconductor film disposed on the insulating film, and a source electrode electrically connected to the semiconductor film. A method for manufacturing a matrix array substrate, comprising: a thin film transistor device having a drain electrode; a signal line electrically connected to the drain electrode; and a pixel electrode electrically connected to the source electrode. A first step of forming a semiconductor film thereon; a second step of forming a first conductive layer on an upper surface of the semiconductor film; and the semiconductor film and the first conductive film corresponding to a formation location of the thin film transistor device. Is patterned using the same mask pattern, and the lower conductive layer of the source electrode, the drain electrode and the signal line is formed collectively, A third step of forming the serial semiconductor film, in correspondence with the pads for external connection to the scanning line, the fourth to form an opening in the semiconductor film and the insulating film
And a fifth step of forming a second conductive layer on the upper surface of the substrate and then patterning to form an upper conductive layer disposed on the lower conductive layer and to form the pixel electrode. A method for manufacturing a matrix array substrate. 15. The method according to claim 14, wherein the first conductive layer is mainly composed of aluminum. 16. The first conductive layer is a laminated film containing aluminum, and the uppermost layer of the laminated film is made of at least one material selected from tantalum, titanium, tungsten and vanadium. Claim 15
A manufacturing method of the matrix array substrate described in the above.