IN2014CH01654A - - Google Patents

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Publication number
IN2014CH01654A
IN2014CH01654A IN1654CH2014A IN2014CH01654A IN 2014CH01654 A IN2014CH01654 A IN 2014CH01654A IN 1654CH2014 A IN1654CH2014 A IN 1654CH2014A IN 2014CH01654 A IN2014CH01654 A IN 2014CH01654A
Authority
IN
India
Prior art keywords
several
data process
processing
data
egress
Prior art date
Application number
Inventor
Bhat Vinayak
Kulkarni Likhit
Kumar Srivastava Anuj
Kashyap Sachin
Das Abhijit
Kumaraswamy Ravishankar
Original Assignee
Tejas Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tejas Networks Ltd filed Critical Tejas Networks Ltd
Priority to IN1654CH2014 priority Critical patent/IN2014CH01654A/en
Priority to US14/670,384 priority patent/US10044614B2/en
Publication of IN2014CH01654A publication Critical patent/IN2014CH01654A/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/50—Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7452—Multiple parallel or consecutive lookup operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The embodiments of the present invention provide a system and method for providing multi-processor data plane architecture. The method for comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units is selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, like DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.
IN1654CH2014 2014-03-28 2014-03-28 IN2014CH01654A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN1654CH2014 IN2014CH01654A (en) 2014-03-28 2014-03-28
US14/670,384 US10044614B2 (en) 2014-03-28 2015-03-26 System and method for dynamic and configurable L2/L3 data—plane in FPGA

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN1654CH2014 IN2014CH01654A (en) 2014-03-28 2014-03-28

Publications (1)

Publication Number Publication Date
IN2014CH01654A true IN2014CH01654A (en) 2015-10-09

Family

ID=54191972

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1654CH2014 IN2014CH01654A (en) 2014-03-28 2014-03-28

Country Status (2)

Country Link
US (1) US10044614B2 (en)
IN (1) IN2014CH01654A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10230810B1 (en) * 2016-03-18 2019-03-12 Barefoot Networks, Inc. Storing packet data in mirror buffer
US10949199B1 (en) 2017-09-14 2021-03-16 Barefoot Networks, Inc. Copying packet data to mirror buffer
US10608939B1 (en) 2018-02-13 2020-03-31 Barefoot Networks, Inc. Identifying congestion in a network
CN108920097B (en) * 2018-06-11 2021-04-13 北京理工雷科雷达技术研究院有限公司 Three-dimensional data processing method based on interleaving storage
US20220247719A1 (en) * 2019-09-24 2022-08-04 Pribit Technology, Inc. Network Access Control System And Method Therefor
JP2022187578A (en) 2021-06-08 2022-12-20 富士通株式会社 Communication control device, communication control system, and communication control method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782853B2 (en) * 2002-12-06 2010-08-24 Stmicroelectronics, Inc. Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine
US7539199B2 (en) * 2003-02-21 2009-05-26 Gireesh Shrimali Switch fabric scheduling with fairness and priority consideration
US7583588B2 (en) * 2004-11-30 2009-09-01 Broadcom Corporation System and method for maintaining a layer 2 modification buffer
US7809009B2 (en) * 2006-02-21 2010-10-05 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
WO2011078812A1 (en) * 2009-12-22 2011-06-30 Bazlamacci Cuneyt F Systolic array architecture for fast ip lookup
WO2012024699A1 (en) * 2010-08-20 2012-02-23 Mosys, Inc. Data synchronization for circuit resources without using a resource buffer
US9086878B2 (en) * 2012-06-29 2015-07-21 Broadcom Corporation Oversubscribing to a packet processing device to adjust power consumption
US20140156941A1 (en) * 2012-11-30 2014-06-05 Advanced Micro Devices, Inc. Tracking Non-Native Content in Caches

Also Published As

Publication number Publication date
US20150281131A1 (en) 2015-10-01
US10044614B2 (en) 2018-08-07

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