IN2013CH05362A - - Google Patents

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Publication number
IN2013CH05362A
IN2013CH05362A IN5362CH2013A IN2013CH05362A IN 2013CH05362 A IN2013CH05362 A IN 2013CH05362A IN 5362CH2013 A IN5362CH2013 A IN 5362CH2013A IN 2013CH05362 A IN2013CH05362 A IN 2013CH05362A
Authority
IN
India
Prior art keywords
gat
data
group size
additional
smaller
Prior art date
Application number
Inventor
Sivasankaran Vijay
Shivhare Vivek
Manohar Abhijeet
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Priority to IN5362CH2013 priority Critical patent/IN2013CH05362A/en
Priority to US14/261,925 priority patent/US9971514B2/en
Publication of IN2013CH05362A publication Critical patent/IN2013CH05362A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A memory system or flash card may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space may be organized with a large logical group size for sequential data. For fragmented data, the GAT may reference an additional GAT page or additional GAT chunk that has a smaller logical group size.
IN5362CH2013 2013-11-21 2013-11-21 IN2013CH05362A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN5362CH2013 IN2013CH05362A (en) 2013-11-21 2013-11-21
US14/261,925 US9971514B2 (en) 2013-11-21 2014-04-25 Dynamic logical groups for mapping flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN5362CH2013 IN2013CH05362A (en) 2013-11-21 2013-11-21

Publications (1)

Publication Number Publication Date
IN2013CH05362A true IN2013CH05362A (en) 2015-05-29

Family

ID=53174475

Family Applications (1)

Application Number Title Priority Date Filing Date
IN5362CH2013 IN2013CH05362A (en) 2013-11-21 2013-11-21

Country Status (2)

Country Link
US (1) US9971514B2 (en)
IN (1) IN2013CH05362A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160070920A (en) * 2014-12-10 2016-06-21 에스케이하이닉스 주식회사 Memory system including semiconductor memory device and controller having map table and operating method thereof
TWI563510B (en) * 2015-07-24 2016-12-21 Phison Electronics Corp Mapping table accessing method, memory control circuit unit and memory storage device
US9811284B2 (en) 2015-12-20 2017-11-07 Apple Inc. One-pass programming in a multi-level nonvolatile memory device with improved write amplification
KR102340094B1 (en) * 2017-03-31 2021-12-17 에스케이하이닉스 주식회사 Memory system and operating method thereof
US10565123B2 (en) * 2017-04-10 2020-02-18 Western Digital Technologies, Inc. Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module
US10635584B2 (en) 2017-06-29 2020-04-28 Western Digital Technologies, Inc. System and method for host system memory translation
US10437734B2 (en) * 2017-08-31 2019-10-08 Micron Technology, Inc. Memory constrained translation table management
US10901912B2 (en) 2019-01-28 2021-01-26 Western Digital Technologies, Inc. Flash translation layer table for unaligned host writes
US11010057B2 (en) 2019-05-29 2021-05-18 Western Digital Technologies, Inc. Storage system and method for storage system calibration
US10997081B2 (en) 2019-05-29 2021-05-04 Western Digital Technologies, Inc. Host and method for storage system calibration
US11556249B2 (en) 2020-09-01 2023-01-17 Western Digital Technologies, Inc. Delaying random data relocation for reducing write amplification in storage devices
CN115079957B (en) * 2022-07-20 2023-08-04 阿里巴巴（中国）有限公司 Request processing method, device, controller, equipment and storage medium

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8452912B2 (en) 2007-10-11 2013-05-28 Super Talent Electronics, Inc. Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read
US7139864B2 (en) * 2003-12-30 2006-11-21 Sandisk Corporation Non-volatile memory and method with block management system
US7433993B2 (en) * 2003-12-30 2008-10-07 San Disk Corportion Adaptive metablocks
US7509471B2 (en) * 2005-10-27 2009-03-24 Sandisk Corporation Methods for adaptively handling data writes in non-volatile memories
US8959280B2 (en) 2008-06-18 2015-02-17 Super Talent Technology, Corp. Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear
TWI385527B (en) 2009-02-10 2013-02-11 Phison Electronics Corp Multi level cell nand flash memory storage system, and controller and accessing method thereof
US8443167B1 (en) 2009-12-16 2013-05-14 Western Digital Technologies, Inc. Data storage device employing a run-length mapping table and a single address mapping table
US8316176B1 (en) 2010-02-17 2012-11-20 Western Digital Technologies, Inc. Non-volatile semiconductor memory segregating sequential data during garbage collection to reduce write amplification
JP5066241B2 (en) 2010-09-24 2012-11-07 株式会社東芝 Memory system
US8848445B2 (en) * 2011-05-17 2014-09-30 Sandisk Technologies Inc. System and method for minimizing write amplification while maintaining sequential performance using logical group striping in a multi-bank system
CN103688246A (en) 2011-05-17 2014-03-26 桑迪士克科技股份有限公司 A non-volatile memory and a method with small logical groups distributed among active SLC and MLC memory partitions
US9235502B2 (en) 2011-09-16 2016-01-12 Apple Inc. Systems and methods for configuring non-volatile memory
KR20130030640A (en) 2011-09-19 2013-03-27 삼성전자주식회사 Method of storing data to storage media, and data storage device including the same
US20130173842A1 (en) 2011-12-28 2013-07-04 King Ying Ng Adaptive Logical Group Sorting to Prevent Drive Fragmentation
US20140047159A1 (en) 2012-08-10 2014-02-13 Sandisk Technologies Inc. Enterprise server with flash storage modules

Also Published As

Publication number Publication date
US20150143029A1 (en) 2015-05-21
US9971514B2 (en) 2018-05-15

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