IL264939A - Circuitries and methods of preventing variable latencies caused by meta-stability - Google Patents

Description

- 1 - 264939/2 CIRCUITRIES AND METHODS OF PREVENTING VARIABLE LATENCIES CAUSED BY META-STABILITY TECHNOLOGICAL FIELD This specification is directed, in general, to electronic circuitries operating in different clock domains, and particularly to the exchange of signals across such clock domains.

BACKGROUND Signals transferred across digital systems having multiple clock domains must be synchronized to avoid meta-stability and synchronization failure. Meta-stability is defined as a third (meta-stable) state of bistable devices (e.g., flip-flops, memories) that typically occurs when triggering conditions of such devices are violated (e.g., input setup time, input hold time, slew rate and/or width of clock signals, and/or input power supply voltage). Good level of synchronization can be achieved in systems having multiple clock domains by using asynchronous first-in first-out (FIFO) memory device(s). However, asynchronous FIFO memories typically add delays of several clock cycles occurring because of the need to synchronize the input and output pointers of the FIFO memory across the clock domains through multiple flip-flops.

In digital systems that rely on constant latency, the introduction of asynchronous clock domains can have undesirable repercussions. It is generally accepted that transferring data across asynchronous clock domains results in uncertainty in the propagation time across the clock domain. This uncertainty is typically of the order of one to two clock cycles. The cause of the uncertainty is meta-stability at the output of flip-flops of the FIFO memory, which receive signals that toggle around the region of the rising edge of the clock input. Though asynchronous FIFOs can synchronize signals across different clock domains, the absolute propagation time through the asynchronous FIFO memory cannot be guaranteed to within a single clock cycle.

Some solutions related to synchronization of signals exchanged between different time/clock domains known from the patent literature are briefly described below. - 2 - 264939/2 In US Patent No. US 6,033,441 a transfer of data between first and second clock domains is synchronized in a situation in which the first clock signal in the first clock domain is generated from a source independent from the second clock signal in the second clock domain. The ratio of one frequency to another is determined along with the phase relationship between the two clock signals during a selected period of time.

Then, the phase relationship is predicted for a future period of time. This prediction of the relationship between the two clock signals serves as an input to a control mechanism, which prevents sampling of data and control signals when they are transitioned from one state to another.

US Patent No. US 9,740,236 describes systems and methods of dual window watchdog timer (DWWDT). In some embodiments, a method may include running a first counter in a first clock domain and a second counter in a second clock domain; generating an interrupt to a controller during a window open period, wherein the window open period begins in response to the first counter having reached a predetermined threshold; and at least one of: restarting the first counter if the controller restarts the second counter in response to the interrupt before the window open period ends; or issuing a system reset if the controller does not restart the second counter in response to the interrupt before the window open period ends.

GENERAL DESCRIPTION Techniques for determining timings of data transfers between first and second time/clock domains through a FIFO memory device are disclosed. One or more calibration procedures are carried out to determine phase relations between the clock signals of the time/clock domains that are suitable for carrying out the data transfers between the time/clock domains substantially, or entirely, without meta-stabilities. The calibration procedures are used to generate calibration data that can be used to determine timings for conducting data transfers with substantially constant and deterministic latency, and/or to determine timings that are prone to the occurrence of meta-stabilities, in which conduction of data transfers between the time/clock domains should be avoided. In some embodiments the generated calibration data is used to identify phase relations between the clock pulse signals of the time/clock domains that are most likely free of meta-stabilities and thus preferable for conducting the data transfers, and/or for altering at least one of the clock signals to impose a different/new - 3 - 264939/2 phase relation between the clock/time domains that is less, or not, prone to the occurrence of the meta-stabilities.

Additionally or alternatively, the calibration procedures can comprise determining based on the generated calibration data phase relations for carrying out the data transfers that are sufficiently remote (e.g., on a unit-circle phase plane) from the phase relations that are prone to the occurrence of meta-stabilities, and adding the determined (new) sufficiently remote phase relations to the calibration data. The new/remote phase relations are determined in some embodiments to be in a range defined about (e.g., ±5º, ±10º, or ±15º) a 180º phase shift relative to the phase relations that are prone to the occurrence of meta-stabilities. The new/remote calibration data can be similarly used to determine timings for carrying out data transfers between the clock/time domains when the phase relations between the clock signals of the time/clock domains can provide data transfers substantially, or entirely, without meta- stabilities, and/or for altering at least one of the clock pulse signals of the time/clock domains to impose such phase relation between the time/clock domains.

The calibration procedures are carried out in some embodiments using the FIFO memory device to conduct arbitrary data transfer operations between the time/clock domains in a (non-operational) calibration mode, under two or more different phase relations between the clock signals of the time/clock domains, and examining one or more flag indicators of the FIFO memory device during the data transfer operations to identify occurrence of meta-stabilities. A calibration circuitry is used in some embodiments to switch the FIFO memory device into the calibration mode.

Components of the calibration circuitry are located in the different time/clock domains, and can be linked by at least one synchronizer circuit, such as two or more serially connected flip-flop synchronizer. In some embodiments the calibration circuitry is configured to simulate data transfers between the time/clock domains in various different phase relationships of their clock pulse signals, without actually using the FIFO memory device to carry out data transfers operations during the calibration stages.

In possible applications one or more calibration procedures are carried out to determine phase relationships between clock pulse signals of first and second time/clock domains having a same clock pulse frequency, for conducting data transfers between the time/clock domains substantially, or entirely, without meta-stabilities. The calibration procedure can use a one-bit calibration signal generated in the first clock/time domain - 4 - 264939/2 that toggles on every rising edge of clock pulse signal of the first domain, used as a write enable of the FIFO memory device for crossing from the first clock/time domain to the second clock/time domain. The write data sample values supplied to the FIFO memory are not relevant for the calibration procedure, and can be set to zero ("0" logic state) for the duration of the calibration procedure. The FIFO memory device is read using clock pulse signal of the second time/clock domain whenever its empty flag is not asserted (i.e., when it is not in an empty state). In the absence of meta-stability, the empty flag of the FIFO memory device should substantially be a time-shift of the one- bit write-enable calibration signal i.e., a regular square wave. If meta-stability occurs during the calibration mode data transfers, the waveform of the Empty flag of the FIFO memory device will have an irregular duty cycle, which can be easily detected e.g., by identifying diversion in the duty cycle of the Empty flag, and/or by comparing the Empty flag to the one-bit write-enable calibration signal.

The calibration procedure can be repeated using an inverted version of the clock pulse signal of the second time/clock domain for reading the FIFO memory device. If meta-stability is detected using a certain clock phase, that clock phase should be rejected in favor of the opposite phase which is guaranteed not to generate meta- stability (as only one phase may violate setup/hold time).

In some possible applications one or more calibration procedures are carried out to determine phase relationships between clock pulse signals of first and second time/clock domains which clock pulse frequencies are related by a common fraction M/N (where M>0 and N>0 are integers), for conducting data transfers between the time/clock domains substantially, or entirely, without meta-stabilities. The calibration procedure utilizes a first counter having a period of M cycles in the first time/clock domain, a second counter having a period of N cycles in the second time/clock domain, a reference register or counter for storing a value between 0 to M in the first time/clock domain, a one-bit signal configured to toggle each time that the value of the first counter matches the value in the reference register or counter, a synchronizer circuit for passing the one-bit signal to the second time/clock domain and resetting the second counter.

During the calibration procedures the first and second counters are operated multiple times with their respective clock pulse signals and various different values stored in the reference register or counter. In the absence of meta-stability, subsequent - 5 - 264939/2 one-bit counter reset signals from the first time/clock domain should coincide with the value N-1 in the second counter. If the value of the second counter is different from N-1 when the one-bit reset signal is asserted by the synchronizer circuit in the second time/clock domain, this is regarded as an indication of meta-stability. This procedure can be repeated using all values between 0 to M for the reference register or counter. In some embodiments, after all values between 0 to M for the reference register or counter have been examined by the calibration circuitry, phase relation for conducting data transfers between the time/clock domains can be determined as a phase shift (e.g., of about 180º) of the value of the reference register or counter for which the greatest number of meta-stabilities been identified, so as to guarantee substantially meta-stability free data transfers between the time/clock domains.

This way, the start of active data transfer in operational mode across the time/clock domain crossing can be timed with the ideal offset value in the first counter.

For example, the value(s) of the reference register or counter (X) that results in meta- stability indicate in some embodiments the worst-case (WC) phase relationship scenario between the two time/clock domains. Since the reference register/counter value (X) is in a range of 0 to M-1, the value MS at which meta-stability (MS) is expected to be min minimized can be computed as follows – MSmin = (XWC + M/2) modulo M, where X is the value of the reference register/counter for which most meta-stability WC events been observed, and MSmin is the ideal offset value to be obtained in the first counter for commencing data transfer between the time/clock domains.

One inventive aspect disclosed herein relates to a method of detecting instabilities of a FIFO memory device in data transfers between first and second clock domains. The method comprises conducting first and second cyclical count processes in the first and second clock domains, respectively, issuing in the second clock-domain a reset signal when a value of the first cyclical count process equals a predetermined value, and issuing an instability detection signal if a value of the second cyclical count process is different from a maximal count value of the second cyclical count process while the reset signal is issued. Optionally, but in some embodiments preferably, a cycle of the first cyclical count process is proportional to a clock frequency of the first clock domain, and a cycle of the second cyclical count process is proportional to a clock frequency of the second clock domain. - 6 - 264939/2 Optionally, but in some embodiments preferably, the predetermined value is associated with a certain phase relation between clock signals of the first and second clock domains. The method can comprise determining an instability associated with the certain phase relation when at least one instability detection signal is issued after a first issuance of the reset signal in the second time domain. The first and second cyclical count processes can be continuously conducting to carry out a predefined number of cyclical counts corresponding to an average length, or to an expected maximal length, of a data transfer operation by the FIFO memory device, to thereby identify instabilities associated with the certain phase relation.

The issuing of the reset signal in the second clock-domain comprises in some embodiments synchronously passing the reset signal from the first clock-domain to the second clock-domain.

The method comprises in some embodiments selecting a new value of the predetermined value used for issuing the reset signal, and continuously conducting the first and second cyclical count processes for identifying instabilities associated with a certain phase relation between the clock domains associated with the selected new value. The method can accordingly comprise identifying instabilities associated with all possible phase relations between the clock domains corresponding to all possible values of the predetermined value ranging between minimal and maximal count values of the first cyclical count process.

In some possible embodiments the clock frequencies of the first and second clock domains are substantially equal. In such possible embodiments the count value of the first cyclical count process can be used as the reset signal, and/or the second cyclical count process can be implemented by an Empty flag of the FIFO memory device.

The method can comprise determining phase relations optimal for transferring data by the FIFO memory device between the clock domains with constant latency based on the identified instabilities. Optionally, but in some embodiments preferably, determining of the optimal phase relations comprises determining at least one phase relation that is relatively remote (e.g., in the phase plane) from at least one of the phase relations associated with an identified instability. For example, and without being limiting, the determined at least one phase relation can be a range defined about a 180º phase shift of at least one of the phase relations associated with an instability. The at least one of the - 7 - 264939/2 phase relations associated with an instability can be a phase relation for which a greatest number of meta-stabilities been identified/observed during the calibration process.

In some embodiments a ratio of the clock frequencies of the first and second clock domains substantially equals to a ratio of the count cycles of the first and second cyclical count processes.

Optionally, but in some embodiments preferably, clock frequencies of the first and second clock-domains are frequency-locked to a common reference.

A method of operating a FIFO memory device according to some possible embodiments comprises calibrating the FIFO memory device using any of the methods described hereinabove or hereinbelow to identify the phase relations associated with the instabilities and determining therefrom optimal phase relations for conducting the data transfers between the clock domains by said FIFO memory device, continuously conducting the first and second cyclical count processes in their respective clock domains, determining a phase relation between clock signal of the clock domains based on count values of the first and second cyclical count processes, and starting data transfer between the first and second clock domains by the FIFO memory device when the determined phase relation matches one of the optimal phase relations.

The method can comprise carrying out calibration of the FIFO memory device during startup of at least one the clock domains. The method can be used to perform data transfers between the first and second clock-domains with constant latency.

Another disclosed inventive aspect relates to calibration circuitry for determining phase relationships prone to instabilities in data transfers between first and second clock domains by a FIFO memory device. The calibration circuitry comprises a first cyclical counter operated in the first clock domain, a second cyclical counter operated in the second clock domain, a comparator configured to assert a reset signal for resetting the second counter whenever count value of the first counter equals a predetermined value, and an instability detector configured to assert an instable indication signal if count value of the second counter is different from a maximal count value of the second counter while the reset signal is asserted. A cycle of the first cyclical counter can be proportional to a clock frequency of the first clock domain and a cycle of the second cyclical counter can be proportional to a clock frequency of the second clock domain. - 8 - 264939/2 Optionally, but in some embodiments preferably, the predetermined value is associated with a certain phase relationship between clock signals of the first and second clock domains. The circuitry can be configured to operate the first and second counters to carry a predefined number of cyclical counts corresponding to an average, or maximal, length of data transfer operation for identifying instabilities associated with a certain phase relation between the clock domains. The circuitry can comprise either a reference memory cell or counter for holding the predetermined value associated with the certain phase relationship. The circuitry can be configured to store a new value in the reference memory cell, or to increment the reference counter, so as to set a new predetermined value for identifying instabilities associated with a certain phase relation between the clock domains associated with the new predetermined value.

In some embodiments the circuitry comprises a synchronizer for passing the reset signal from the first clock-domain to the second clock-domain. The instability detector can utilize a comparator configured to assert a signal when the count value of the second counter equals a maximal count value of the second counter. Optionally, but in some embodiments preferably, a ratio of the clock frequencies of the first and second clock domains substantially equals to a ratio of the cycles of the first and second cyclical counters.

In some embodiment the instability detector comprises a control unit configured and operable to monitor the reset signal and signals from the comparator of the instability detector, and determine instabilities associated with the certain phase relationship based thereon. The control unit can be configured and operable to operate the first and second counters to carry out a predefined number of cyclical counts corresponding to an average, or maximal, length of data transfer operation for identifying instabilities associated with the certain phase relation. Optionally, the control unit is configured and operable to store a new predetermined value in the reference memory cell, or to increment the reference counter, and to operate the first and second counters to carry out a predefined number of cyclical counts for identifying instabilities associated with a certain phase relation between the clock domains corresponding to the new value in the reference memory cell or counter. The control unit is configured and operable in some embodiments to identify instabilities associated with all possible phase relations between the clock domains. - 9 - 264939/2 In some possible embodiments the cycle of the first cyclical counter equals one, the cycle of the second cyclical counter equals one, and the count value of the first cyclical counter is used as the reset signal. Optionally, an empty-flag of the FIFO memory device is used to implement the second cyclical counter.

The control unit can be configured and operable to determine phase relations optimal for transferring data by the FIFO memory device between the clock domains with constant latency based on the identified instabilities. In some possible embodiments the control unit is configured and operable to determine the optimal phase relations by determining at least one phase relation that is relatively remote from at least one of the phase relations associated with an identified instability. Alternatively, or additionally, the control unit is configured and operable to determine at least one phase relation in a range defined about a 180º phase shift of at least one of the phase relations associated with an instability. Optionally, the at least one of the phase relations associated with an instability can be a phase relation for which a greatest number of meta-stabilities been identified.

The clock frequencies of the first and second clock-domains are frequency- locked to a common reference in some applications.

Yet another disclosed inventive aspect relates to a circuitry for operating a FIFO memory device to perform data transfers between first and second clock-domains. The circuitry comprises a calibration circuitry as described hereinabove or hereinbelow for calibrating the FIFO memory device to identify the instabilities phase relations and determining therefrom the optimal phase relations for data transfers, a timing module configured to continuously operate the first and second counters in their respective clock-domains for determining phase relation between the clock-domains based on count values of the first and second counters and asserting an enable signal for starting data transfer by the FIFO memory device when the determined phase relation matches one of the optimal phase relations.

The circuitry can comprise a calibration module configured and operable to calibrate the FIFO memory device during startup procedure of at least one the clock- domains. - 10 - 264939/2 BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the invention and to see how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings. Features shown in the drawings are meant to be illustrative of only some embodiments of the invention, unless otherwise implicitly indicated. In the drawings like reference numerals are used to indicate corresponding parts, and in which: Figs. 1A to 1C schematically illustrate a calibration technique according to some possible embodiments for calibrating time/clock domains operating with a same clock pulse frequency, wherein Fig. 1A is a block diagram of a calibration circuitry, Fig. 1B is a flowchart of a possible calibration procedure, and Fig. 1C exemplifies signal waveforms generated in the calibration circuitry of Fig. 1A during a possible calibration procedure; Figs. 2A to 2D schematically illustrate a calibration technique according to some possible embodiments for calibrating time/clock domains operating with clock pulse frequencies having some constant ratio, wherein Fig. 2A is a block diagram of a possible calibration circuitry, Fig. 2B is a flowchart of possible calibration procedures, Fig. 2C exemplifies signal waveforms generated using the calibration circuitry of Fig. 2A during a possible calibration procedure in which latency ambiguities are not detected, and Fig. 2D exemplifies signal waveforms generated using the calibration circuitry of Fig. 2A during a possible calibration procedure in which latency ambiguities are detected; and Fig. 3 exemplifies signal waveforms in a data transfer operation according to some possible embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS One or more specific embodiments of the present disclosure will be described below with reference to the drawings, which are to be considered in all aspects as illustrative only and not restrictive in any manner. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. Elements illustrated in the drawings are not necessarily to scale, or in correct proportional relationships, which are not critical. Emphasis instead being placed upon clearly illustrating the principles of the invention such that persons - 11 - 264939/2 skilled in the art will be able to make and use the invention, once they understand the principles of the subject matter disclosed herein. This invention may be provided in other specific forms and embodiments without departing from the essential characteristics described herein.

This invention in some embodiments thereof is aimed at applications that require multiple parallel digital paths to have a constant and deterministic latency in an environment with multiple clock domains. Techniques are disclosed for preventing variable latencies caused by meta-stability in data transfers between first (A) and second (B) time/clock domains using asynchronous FIFO memory device. The disclosed techniques are useful for synchronizing data transfers between time/clock domains which frequencies (F and F ) of their clock signal sources locked to a common A B reference, and having a same frequency (F =F ), or some constant fractional ratio of A B their frequencies (F /F = M/N, where M>0 and N>0 are integers). In general, A B calibration procedures are used in embodiments disclosed herein to determine phase relations between clock pulse signal sources of the first and second time/clock domains that exhibit meta-stability, and based thereon determine optimal phase difference(s) at which data transfers between the two domains should be started.

In some embodiments a calibration unit is used to carry out a calibration procedure of an asynchronous FIFO memory device upon system initiation, for determining the optimal phase difference(s) for data transfers between the time/clock domains via the asynchronous FIFO memory device. The calibration unit is configured to test data transfers sequences carried out by the asynchronous FIFO with multiple different phase differences, identify phase differences between the clock signals of the time/clock domains for which irregular latencies occur due to meta-stability during the data transfers, and select a phase shift with fixed, or without, latency (e.g., 180º phase shift) to carry out the data transfers during system operation. The calibration unit is configured in some embodiments to simulate the signal flow through the time/clock domains with the multiple different phase differences under which the asynchronous FIFO memory device is operated, and identify the phase differences for which the irregular latencies occur, without actually carrying out any data transfer via the asynchronous FIFO memory device during the calibration process.

In embodiments wherein the two clock/time domains have the same frequency, but unknown phase relationship, the calibration unit can utilize a PLL (phased locked - 12 - 264939/2 loop) to generate the clock signal of the second time domain (CLK_B) from the clock signal of the first time domain (CLK_A). Other techniques can be similarly used in the calibration unit to generate the clock signal of the second time domain (CLK_B). The calibration unit then tests data transfers sequences carried out by the asynchronous FIFO memory device with either the true or inverted output from the PLL generating the clock signal of the second time/clock domain (CLK_B). In this configuration the asynchronous FIFO memory device is written on alternate clock cycles (i.e., memory write is performed for each clock pulse signal in the first time domain, CLK_A) and read whenever it is not empty. If there are no meta-stability events during the data transfer sequences, the state of the empty flag of the asynchronous FIFO memory device should continuously toggle on alternate cycles. If the state of the empty flag does not continuously toggle throughout a certain data transfer sequence, this is attributed to meta-stability, and the control unit accordingly chooses 180° phase shift (i.e., the inversion) of clock signal used for the second time/clock domain (CLK_B) for carrying our data transfers. Optionally, but in some embodiments preferably, the duty cycles of the clock signals of the first and second time/clock domains is about 50%.

When the two clock domains are operated with different frequencies having constant fractional ratio F /F = M/N, the calibration unit utilizes a first counter A B (CNT_A), being a M cycle counter operated with the clock signal of the first time/clock domain, and a second counter (CNT_B), being a N cycle counter operated with the clock signal of the second time/clock domain, for determining the phase difference between the two time/clock domains for carrying out data transfers. The calibration unit is configured to generate a reset signal for the second counter (the N cycle counter, CNT_B) whenever the value of first counter (the M cycle counter, CNT_A) equals a predefined reset value in the range of [0:M-1]. The generated reset signal is passed by a double flip-flop synchronizer to time/clock domain B, wherein it resets (zeros) the second counter. The calibration unit is configured to test/simulate data transfers sequences carried out by the asynchronous FIFO memory device for all possible phase differences i.e., using all possible reset values for second counter in the range of [0:M-1], and identify meta-stabilities whenever the values of the first and second counters are not is congruency when the reset signal generated in the first time/clock domain is asserted in the second clock/time domain i.e., the value of the second counter CNT_B is different from N-1, excluding the first time the reset signal is asserted. When - 13 - 264939/2 meta-stability is identified the calibration unit selects a suitable phase shift with fixed latency (e.g., a 180º phase shift) based on the identified phase difference for which the meta-stability was identified, to carry out the data transfers.

For an overview of several example features, process stages, and principles of the invention, the examples of signal synchronization across different time/clock domains illustrated schematically and diagrammatically in the figures are mainly intended for data transfers operations. These signal synchronization schemes are shown as one example implementation that demonstrates a number of features, processes, and principles used to minimize/prevent data transfers latencies, but they are also useful for other applications and can be made in different variations. Therefore, this description will proceed with reference to the shown examples, but with the understanding that the invention recited in the claims below can also be implemented in myriad other ways, once the principles are understood from the descriptions, explanations, and drawings herein. All such variations, as well as any other modifications apparent to one of ordinary skill in the art and useful in time/clock domains synchronization applications may be suitably employed, and are intended to fall within the scope of this disclosure.

Fig. 1A is a block diagram of a calibration circuitry 10 usable for determining phase relationship for data transfers between two time/clock domains, Domain A and Domain B, having substantially the same pulse frequency of their clock signals, CLK_A and CLK_B (i.e.,F =F ), and an unknown phase difference. The data transfers A B between the time/clock domains A and B are carried out using the FIFO memory device 11 (also known as a two-clock FIFO synchronizer).

The FIFO memory device 11 is configured to receive input data streams in the time/clock domain A via its Din data input port, and a write enable signal via its Wen port, whenever new data provided to the Din data input port needs to be written into the FIFO memory device 11. The FIFO memory device 11 is further configured to output data streams in the time/clock domain B via its Dout data output port, issue in the time/clock domain B 'empty' signals via its Empty port whenever the FIFO memory device 11 is empty, and receive in the time/clock domain B read enable signals via its Ren port indicating that the FIFO memory device 11 needs to output new data via its data output port Dout.

The FIFO memory device 11 can be implemented using any suitable two-clock FIFO synchronizer configured to increment a write-pointer (not shown), and write the - 14 - 264939/2 data on its Din data input port to the location indicated by the write-pointer, whenever the Wen and CLK_A signals are asserted in Domain A, and to increment a read- pointer (not shown), and output the data stored in the location indicated by the read- pointer on its Dout data output port, in response to assertion of the Ren and CLK_B signals in Domain B.

In this specific and non-limiting example the clock signal CLK_B of Domain B is generated from the clock signal CLK_A of Domain A by the PLL unit 12. It is however noted that the clock signal CLK_B of Domain B can be generated by a separate clock pulse generation unit (not shown) that is independent of the clock signal CLK_A of Domain A.

The calibration circuitry 10 comprises a first multiplexer Mx1 which output is electrically connected to the Din data input port of the FIFO memory device 11, a second multiplexer Mx2 which output is electrically connected to the Wen port of the FIFO memory device 11, a third multiplexer Mx3 which output is used as the clock signal CLK_B of Domain B, a one bit counter (e.g., flip-flop) 13 configured to toggle its state responsive to changes in the state of the clock signal CLK_A of Domain A, and the control logic/unit 15 configured to switch the system between calibration and data transfer modes, orchestrate calibration procedures carried out by the calibration circuitry 10, and operate the FIFO memory device 11 to conduct data transfers in optimal phase relationship conditions determined by the calibration procedures.

In some possible embodiments the calibration circuitry 10 comprises a synchronizer (e.g., a two-flip-flop synchronization) circuit 14 for passing on line 14w the calibration-write-enable Cal_Wen signal (i.e., the output of the counter 13) to Domain B. As will explained hereinbelow, the control unit can use the Cal_Wen signal to detect meta-stabilities of the FIFO memory device 11 during data transfers between the time/clock domains A and B.

The first multiplexer Mx1 is configured to select the data source supplied to the Din data input port of the FIFO memory device 11, based on calibration enable signals Cal-en generated by control unit 15, and the second multiplexer Mx2 is configured to select the signal supplied to the Wen port of the FIFO memory device 11, based on calibration enable signals Cal-en. Particularly, the first multiplexer Mx1 receives on a first data input thereof the data streams Data-WR to be transferred to the Domain B through the FIFO memory device 11, and on a second data input thereof arbitrary data - 15 - 264939/2 to be used during the calibration procedures e.g., an endless sequence of zeroes. The second multiplexer Mx2 receives on its first input the write enable signal WR-En supplied to the FIFO memory device 11 during regular data transfer operations, and on its second input the output of the counter 13, used as the write enable signal during the calibration procedures.

During the calibration procedures the Cal-en signal is asserted in order to supply to the Din data input port of the FIFO memory device 11 a sequence of arbitrary data (e.g., a sequence of zeros) via the first multiplexer Mx1, and to supply to the Wen port of the FIFO memory device 11 the signals outputted by the counter 13 via the second multiplexer Mx2. In some embodiments the control unit 15 comprises one or more processors and memories (e.g., as shown in Fig. 2A), and the calibration enable signals Cal-en are asserted using computer software instructions when the FIFO memory device 11 is being calibrated.

During regular data transfer operations of the FIFO memory device 11 the Cal-en signal is deasserted in order for the first multiplexer Mx1 to transfer the data stream Data-WR to the Din data input of the FIFO memory device 11, and for the second multiplexer Mx2 to transfer the WR-En signal to the Wen port of the FIFO memory device 11. In this configuration the control unit 15 is configured to select either the true, or inverted by inverter 12i, root clock output from the PLL 12 as the clock signal CLK_B of Domain B, to mitigate against meta-stability. This is achieved by the control unit 15 using the Phase-sel line to select the clock signals CLK_B outputted by the third multiplexer Mx3 for Domain B, based on the results of the previously conducted calibration procedures (e.g., during system start-up and/or in-between data transfer operations).

With reference to Fig. 1B, showing a block diagram of a possible calibration procedure 18 in which the true phase output of the PLL 12 is initially selected in step S1 as the clock signal CLK_B of Domain B for conducting in step S2 data transfer between the time/clock domains A and B. The calibration procedure 18 can be similarly conducted initially using the inverted PLL output generated by the inverted 12i.

During the data transfer of step S2 the FIFO memory device 11 is written on alternate clock cycles of the clock signal CLK_A of Domain A, the FIFO memory device 11 is read in Domain B whenever it is not empty, and the state of the Empty flag is monitored to identify instabilities. In this configuration the Empty flag 11e - 16 - 264939/2 should present an alternating square wave signal corresponding to the write enable pattern supplied to the Wen port of the FIFO memory device 11 (i.e., the signal outputted by the counter 13). If the Empty flag 11e is not a square wave, this is most likely due to meta-stability occurring in the FIFO memory device 11.

If instabilities of the Empty flag signal 11e is not identified (i.e., meta-stability is not detected) by the control unit 15 in step S3, then is step S4 the true phase output of the PLL 12 is used for the data transfers through the FIFO memory device 11 in step S6 e.g., by deasserting the Phase-sel signal. On the other hand, if instabilities of the Empty flag signal 11e are identified by the control unit 15 in step S3 (i.e., meta-stability is detected), then is step S5 the inversion of the output of the PLL 12 generated by the inverter 12i is used for the data transfers through the FIFO memory device 11 in step S6 e.g., by asserting the Phase-sel signal.

Fig. 1C demonstrates a calibration procedure carried out using the calibration circuitry 10, and use of the Phase-sel signal generated by the control unit 15 to set the clock phase of the PLL 12 to avoid meta-stability effects of the FIFO memory device 11. The calibration procedure starts after the Cal_en signal is asserted at t0, which causes multiplexer Mx1 to pass the arbitrary data stream ("0") to the Din data input port of the FIFO memory device 11, and multiplexer Mx2 to pass the Cal_Wen signal (i.e., the output of counter 13) to the Wen port of the FIFO memory device 11.

Thereafter, starting at t1, the Cal_Wen signal is periodically asserted and the arbitrary data presented to the Din data input port is written in the FIFO memory device 11 on alternate clock cycles. The data values written into the FIFO memory device 11 has no significance, and is ignored on the read-side (i.e., Domain B).

At t2 instable Empty signal states are observed, as the Empty signal is changed to indicate that the FIFO memory device 11 is not empty, and further instable Empty signal states are thereafter observed at t4 and t5, after the read enable, Ren, signal is asserted in Domain B at t3, and the data is read from the FIFO memory device 11. The observed instability of the Empty signal is typically because the Empty signal is asserted when the write and read pointers of the FIFO memory (which operate on the first and second time/clock domains, CLK_A and CLK_B, respectively) have the same value. Due to meta-stability, registering the Empty signal by a flip-flop in the second time/clock domain will experience a variable delay of ±1 clock cycles. The Ren signal - 17 - 264939/2 is unstable in the presence of meta-stability of the Empty signal, because it is a function of the Empty flag when the circuitry 10 is operating in calibration mode.

The instable states of the Empty signal identified by the control unit 15 as meta- stability events across the time/clock domains, causing the control unit 15 to assert the Phase_sel signal at t6 in order to inverse the phase of the clock signal CLK_B of Domain B. As demonstrated, when the inversed PLL clock signal is used as CLK_B to conduct data transfer the Empty signal present stable alternating states after each read operation, which fully correspond to the alternating states of the Cal_Wen signal.

With this design, however, it is not possible to monitor the FIFO memory device 11 to detect meta-stability during normal data transfer operations (i.e., carried out while the Cal-en signal is deasserted). Therefore, in some embodiments the Cal_Wen signal is passed to the time/clock Domain B through the synchronizer circuit 14 for monitoring its state by the control unit (or control logic) 15, to detect ambiguities during the normal data transfer operations conducted by the FIFO memory device 11. For example, the control unit 15 can be configured to identify meta-stabilities by the sub- step S6' during the regular data transfers of step S6, by comparing the Cal_Wen signal 14w obtained in the time/clock Domain B (the signal passed from the counter 13 via the synchronizer circuit 14 to Domain B) with the Empty flag signal 11e outputted by the FIFO memory device 11. In this way, the control unit 15 can determine in step S6' that data transfer is carried out without meta-stability events if the synchronized Cal_Wen signal 14w match the Empty flag signal 11e in Domain B, and that meta-stability events occur during the data transfer if the synchronized Cal_Wen signal 14w does not match the Empty flag signal 11e in Domain B.

Accordingly, in some embodiments, the control unit 15 is configured to monitor the Empty signal 11e and the synchronized Cal_Wen signal 14w during regular data transfers, and/or during the calibration procedures, and identify meta-stabilities in the absence of similarity in their patterns (i.e., their autocorrelation function is smaller or greater than an expected value). Particularly, the Empty signal 11e of the FIFO memory device 11 should alternate, possibly with some time difference, to match the pattern of the synchronized Cal_Wen signal 14w. The control unit 15 can be configured to determine meta-stabilities whenever irregular wave patterns of the Empty signal 11e are detected, and/or when the autocorrelation function of the Empty signal 11e and of the synchronized Cal_Wen signal 14w is different from some determined expected - 18 - 264939/2 value. Upon detecting such irregularities the control unit 15 can change the phase of clock CLK_B of Domain B, in order to conduct data transfers substantially, or entirely, without meta-stability events.

Fig. 2A shows a calibration circuitry 20 according to some possible embodiments for calibration of time/clock Domains A and B operated with clock signals CLK_A and CLK_B respectively, having frequencies F and F , which ratio A B F /F substantially equals to some constant M/N i.e., F /F M/N, where M>0 and N>0 A B A B = are integer numbers. The components of the calibration circuitry 20 are located in Domain A and Domain B, and triggered by the respective clock signal of their respective domain.

In Domain A the calibration circuitry 20 comprises a M-cycles counter CNT_A triggered by the Domain A clock signal CLK_A, a memory cell/register CNT_X configured to hold a digital value between 0 to M-1, and a comparator Comp_A triggered by the Domain A clock signal CLK_A and configured to compare the value outputted by the counter CNT_A to the value stored in the memory cell/register CNT_X. In some embodiments a control unit 24 is used to carry out the calibration procedures using the calibration circuitry 20, and to deactivate the calibration circuitry components when calibration is not performed, via the calibration-enable Cal_en and/or the data-transfer-enable Dtran_en signals. Since the calibration circuitry 20 is independent of the FIFO memory device 11 it can be operated during data transfer operations e.g., for determining whether phase relationship of the clock signals CLK_A and CLK_B are suitable for carrying out meta-stability-free data transfers.

The control unit 24 can be configured to store digital values in the memory cell/register CNT_X during calibration procedures. Optionally, but in some embodiments preferably, the memory cell/register CNT_X is implemented by an M- cycles counter, and the control unit 24 is configured and operable to increment the CNT_X counter during various stages of the calibration procedures.

In Domain B the calibration circuitry 20 comprises a N-cycles counter CNT_B triggered by the Domain B clock signal CLK_B, a synchronizer (e.g., a two-flip-flop synchronization) circuit 14 triggered by the CLK_B clock signal and configured to pass the output of the comparator Comp_A from Domain A to Domain B for resetting the CNT_B counter, a memory cell/register Reg_B for holding the digital value N-1, a comparator Comp_B triggered by the CLK_B clock signal and configured to compare - 19 - 264939/2 the value outputted by the CNT_B counter to the value stored in the memory cell/register Reg_B, and an ambiguity/instability detection circuitry 22 configured to identify possible occurrence of instabilities in data transfers between the time/clock domains A and B by the FIFO memory device 11.

The control unit 24 comprises in some embodiments one or more processors 24p and memories 24m for storing data 24d (e.g., calibration data) and executable instructions of one or more computer software modules (e.g., calibration module 24c) configured and operable to activate and operate the calibration circuitry 20 for carrying out calibration procedures. For Example, the control unit 24 can start a calibration procedure by deasserting a data transfer enable Dtran_en signal, asserting a calibration enable signal Cal_en, and asserting reset signals, Rst_A and Rst_X, for resetting the CNT_A and CNT_X counters. The calibration module 24c can be configured to monitor the Ambiguity_detect signals generated by the calibration circuitry 20 and generate calibration data 24d based thereon, to be used for timing data transfer operations by the FIFO memory device 11. The control unit 24 can be further configured to deassert the data transfer enable signal Cal_en after each calibration procedure to deactivate the calibration circuitry, if so needed.

In some embodiments the control unit 24 comprises a timing module 24t configured and operable to assert the data transfer enable Dtran_en signals based on the calibration data 24d, when optimal conditions for data transfers between the clock domains are present. For example, and without being limiting, the timing module 24t can be configured to continuously operate the first and second counters, CNT_A and CNT_B, for determining phase relations between the time/clock domains based on their count values, and to assert the data transfer enable Dtran_en signal for starting data transfers between the time/clock domains by the asynchronous FIFO memory device when the determined phase relation matches one of the determined optimal phase relations for data transfers between the time/clock domains 24d stored in the memory 24m of the control unit 24.

Fig. 2B is a flowchart of a calibration process 28 carried out according to some possible embodiments using the calibration circuitry 20 of Fig. 2A. The calibration process 28 starts in step P1 by asserting the calibration enable signal Cal_en, and the Rst_X signal to reset the CNT_X register/counter. Next, in step P2, the Rst_A signal is asserted to reset the CNT_A counter, and thereafter in step P3, the counters CNT_A - 20 - 264939/2 and CNT_B are periodically triggered by their respective pulse clock signals. When the value of counter CNT_A reaches the value of the CNT_X counter/register the comparator Comp_A asserts an equality signal E_A that is passed through the synchronizer 14 to the reset port of the counter CNT_B.

If the value of the counter CNT_B is not equal to the value N-1 stored in Reg_B an Ambiguity_detect signal is asserted by the ambiguity/instability detection circuitry 22 while the equality signal E_A is asserted. Due to the constant ratio of the clock frequencies F /F = M/N, after the equality signal E_A is asserted for the first time the A B counter CNT_B should complete a full cycle by the time CNT_A completes a count from X+1, X+2,…, M-1, 0, 1,.. to X and the equality signal E_A is passed through the synchronizer circuit 14, where X is the value of CNT_X. Thus, if an ambiguity is identified in step P4, in step P5 it is checked if it is the first ambiguity detected in a calibration scan for a certain value X of the CNT_X counter/register, and if so, the count operations of CNT_A and CNT_B proceeds, as the control is passed to step P3.

If it is determined in step P5 that the identified ambiguity is not the first ambiguity detected in a calibration scan for a certain value X of the CNT_X counter/register, then in step P6, a 180º phase shift of the value X of the CNT_X counter/register is added to the calibration data 24d i.e., MOD (X+M/2 ), where MOD () is the modulo operator M M with divisor M, and   is the floor operator.

If ambiguities are not detected in step P4, in step P7 it is checked if the calibration scan for the value X of the counter/register CNT_X reached its end, and if not, the control is passed back to steps P3 and P4 for further count operations of the CNT_A and CNT_B counters and ambiguity events detection. If it is determined in step P7 that calibration scan for the value X reached its end i.e., there were no ambiguities during the entire calibration scan, then in step P8 the value X of the counter CNT_X is added to the calibration data 24d. The length of a calibration scan can be set to an average length of a typical data transfer operation carried out by the FIFO memory device 11, or to an expected maximal data transfer operation length. In some embodiments the length of each calibration scan is set to few thousand clock cycles.

After updating the calibration data in step P6 or P8, in step P9 the value X of counter/register CNT_X is incremented e.g., by asserting the Inc_X signal, and in step P10 it is checked if the value of counter/register CNT_X equals to M. If the value of counter/register CNT_X does not equal M, then the control is passed back to step P2 - 21 - 264939/2 for starting a new calibration scan for the new value X of counter/register CNT_X. If it is determined in step P10 that the value of counter/register CNT_X equals M/zero i.e., no need for more calibration scans, then in step P11 the calibration process is terminated, and thereafter in step P12 the collected calibration data 24d is used for timing data transfer operations using the FIFO memory device 11.

Particularly, by this stage, either no values of CNT_X have been able to detect meta-stability (ambiguity in the value of CNT_B when the reset pulse Rst_B passed by the synchronizer circuit 14 was received at ambiguity/instability detection circuitry 22 in Fig. 2A), or a subset of values detected meta-stability. In the latter case, an offset value of (CNT_X + M/2)modulo-M is computed for the subset of values of counter/register CNT_X for which meta-stability was detected, to designate ideal phase relations at which data transfer can be initiated guaranteeing substantially fixed (or no) latency. In the former case i.e., meta-stability was not observed for any of the values of the CNT_X register/counter, any phase relation is permissible to start data transfer (because meta-stability was not observed for any phase offset between CLK_A and CLK_B clock signals.

Fig. 2C exemplifies waveform signals in a calibration process across Domain A to Domain B in which the ratio of the clock frequencies is M/N=8/7. These clock domains can be frequency- and phase-locked, but the phase relationship between the two time/clock domains is unknown. Accordingly, in this example CNT_A in a M=8 cycles counter, and CNT_B is a N=7 cycles counter i.e., 8 clock cycles of clock CLK_A of Domain A have the same time period as 7 clock cycles of clock CLK_B of Domain B.

Accordingly, this calibration procedure can use 3-bit counters in the two clock/time domains, CNT_A and CNT_B. The counter CNT_A can be enabled by a calibration start signal, Cal_start. The counter CNT_A generates a (A/M)MHz square- wave signal in Domain A, and CNT_B generates a (B/N)MHz square-wave signal in Domain B. By definition, the two square-wave signals divided-down by the counters will have the same frequency. The Rst_A signal can be asserted in Domain A by the control unit 24 once when a new calibration scan is started for a certain value X of the register/counter CNT_X, and thereafter it can be asserted by the CNT_A counter when the CNT_A counter completes a count cycle. The equality signal E_A is passed across the clock domain crossing by the synchronizer circuit 14, to Domain B, wherein it - 22 - 264939/2 asserts the Rst_B signal that resets the CNT_B counter on the rising edge of CNT_B. If the value of CNT_B does not equal (N-1) when the Rst_B reset signal is asserted (ignoring the first time that it is reset), an Ambiguity_detect flag is asserted (see Fig. 2D). In some embodiments this calibration procedure is run over several thousand of clock cycles for each X value of counter/register CNT_X.

In order to test all possible phase relations, the value of the counter/register CNT_X at which E_A is asserted is incremented for each new calibration scan, and the calibration procedure is repeated over several thousand clock cycles. This has the effect of advancing the clock cycle at which E_A is toggled, by 1 clock cycle over each iteration. This step is repeated until all possible phase relationships of the two clocks, CNT_A and CNT_B, have been exercised. If a particular phase value, X, exhibits variable latency, the calibration procedure identifies phase MOD (X+floor(M/2)) as the M value of CNT_A at which data transfer can be started. This exploits the fact that once the FIFO memory device 11 has data within its memory, the latency is constant for as long as the read and write enables are asserted.

The implication of this calibration procedure is that the operation of the calibration circuitry described hereinabove can be maintained for the duration of the link i.e., of a data transfer between the time/clock domains, because latency ambiguity in the data transfer link can be avoided if the link is started at a point in the phase relationship between the two clock signals, CLK_A and CLK_B, at which the likelihood of meta-stability is minimized. Once the link is started, the FIFO memory 11 ensures that data is drawn at a constant rate across the time/clock domains, until the FIFO memory 11 is empty. At this point the calibration procedure should be restarted if the link is to be resumed.

The calibration techniques disclosed herein are expected to guarantee constant latencies for clock signals CLK_A and CLK_B having a nominal 50% duty cycle. In some applications it is not always feasible to guarantee a specific and constant latency across a clock domain crossing (CDC) due to meta-stability issues, but some systems have properties that may be exploited to eliminate the dynamically variable latency effects of meta-stability. Some properties that lend themselves to a calibration procedure that can be used for defining a fixed latency include, inter alia: - 23 - 264939/2  Continuous data transfer is guaranteed after the start of data transfer across the clock/time domains. There is no need to support irregularly-spaced data transfer bursts in either direction.

 It is permitted to adjust the start of data transfers within a small range of clock cycles.

 The clocks that have been specified for the clock domains have frequencies that are related by a rational fraction, or that are equal.

 These clocks are frequency-locked and phase-locked, although the exact phase relationship is not specified.

 The clocks within the system will be active for the duration over which constant latency is to be maintained. This ensures that the phase relationship between two clocks is maintained without the need for recalibration for each data transmit (Tx) or receive (Rx) session.

 The first two properties imply that it is possible to steer the start of data transfer to avoid regions in which there is the likelihood of meta-stability. It is therefore understood that the calibration techniques disclosed herein can be used to guarantee data transfer operations across different clock/time domains with constant latency.

In some embodiment an additional circuitry/logic can be used to ensure that inter-clock phase adjustment does not result in a different total latency value for the data transfer operations. Based on the calibration data 24d obtained by the calibration process, an offset value of the CNT_A counter in Domain A can be determined, and the write enable Wen signal of the FIFO memory 11 will be asserted once the count value of the CNT_A counter equals to the determined offset value. As this could potentially skew the output to the FIFO memory 11 when compared to other modules in certain applications, padding samples can be introduced to the Din data input port pf the FIFO memory 11 to ensure that the first valid (i.e., non-padding) sample thereafter introduced into the FIFO memory 11 is always written when the value of the CNT_A counter is zero (0). For example, with reference to Fig. 1A, the additional circuitry/logic can utilize circuitry such as the Mx1 multiplexer, and can be configured to manipulate the control input (Pad_en signal in Fig. 3) of the Mx1 multiplexer to feed the required padding samples (zeros) until the value of the CNT_A is zeroed. This additional circuitry/logic can be implemented at least partially by the control unit 24. - 24 - 264939/2 Fig. 3, exemplifies a data transfer operation for which an offset value Start_offset of four is determined based on the calibration data 24d. Thus, after the start transfer Tx_Start and write enable Wen signals are asserted four padding samples (zeros) are fed to the Din data input port of the FIFO memory 11. Thereafter, the padding enable Pad_en signal is deasserted and the actual data to be transferred d0, d1, d2,… , is then fed to the Din data input port of the FIFO memory 11. Correspondingly, the data outputted via the Dout output port of the FIFO memory 11 starts with the four padding samples, and thereafter the transferred d0, d1, d2,… , is outputted. This procedure can guarantee timing to the exact phase relationship offset between the CLK_A and CLK_B clock signals.

The embodiments disclosed herein are particularly useful for applications satisfying the following conditions: - The clock domains across which latency is to be made constant are frequency- locked to a common reference.

- The frequencies of the clock domains are related by an integer ratio (i.e., the ratio of the frequencies must be a common fraction).

- The phase relationship remain constant over the duration of measurement and post-measurement operation.

The calibration procedures are carried out in some embodiments after system power-up. The phase relationship of the clock domains shall remain constant while the PLL clock generators are active and locked. These calibration schemes rely on continuous data transfer from clock/time Domain A to clock/time Domain B through a FIFO memory device without any breaks.

It should also be understood that throughout this disclosure, where a process or method is shown or described, the steps of the method may be performed in any order or simultaneously, unless it is clear from the context that one step depends on another being performed first.

As will be appreciated by one of skill in the art, the present invention may be embodied as a method, system, computer program product, or a combination of the foregoing. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may generally be referred to herein as a "system". Furthermore, the present invention may - 25 - 264939/2 take the form of a computer program product on a computer-usable storage medium having computer-usable program code embodied in the medium. Features of the invention can be implemented primarily in hardware using, for example, hardware components such as application specific integrated circuits (ASICs) or field- programmable gated arrays (FPGAs). Implementation of the hardware state machine so as to perform the functions described herein will be apparent to persons skilled in the relevant art(s). In yet another embodiment, features of the invention can be implemented using a combination of both hardware and software.

As described hereinabove and shown in the associated figures, the present invention provides calibration and/or scheduling circuitries/devices, and related methods, for carrying out data transfers between time/clock domains operated by different clock pulse signals. While particular embodiments of the invention have been described, it will be understood, however, that the invention is not limited thereto, since modifications may be made by those skilled in the art, particularly in light of the foregoing teachings. As will be appreciated by the skilled person, the invention can be carried out in a great variety of ways, employing more than one technique from those described above, all without exceeding the scope of the claims.

Claims (37)

- 26 - 264939/2 CLAIMS

1. A method of detecting instabilities of a FIFO memory device in data transfers between first and second clock domains, the method comprising: 5 conducting first and second cyclical count processes in said first and second clock domains, respectively, a cycle of said first cyclical count process being proportional to a clock frequency of said first clock domain and a cycle of said second cyclical count process being proportional to a clock frequency of said second clock domain; 10 issuing in said second clock-domain a reset signal when a value of said first cyclical count process equals a predetermined value, said predetermined value associated with a certain phase relation between clock signals of said first and second clock domains; and issuing an instability detection signal if a value of said second cyclical count 15 process is different from a maximal count value of said second cyclical count process while said reset signal is issued.

2. The method of claim 1 comprising determining an instability associated with said certain phase relation when at least one instability detection signal is issued after a 20 first issuance of the reset signal in the second time domain.

3. The method of claim 2 comprising continuously conducting the first and second cyclical count processes to carry a predefined number of cyclical counts corresponding to an average length, or to an expected maximal length, of a data transfer operation by 25 the FIFO memory device for identifying instabilities associated with the certain phase relation.

4. The method of any one of the preceding claims wherein the issuing of the reset signal in the second clock-domain comprises synchronously passing the reset signal 30 from the first clock-domain to the second clock-domain. - 27 - 264939/2

5. The method of any one of the preceding claims comprising selecting a new value of the predetermined value used for issuing the reset signal, and continuously conducting the first and second cyclical count processes for identifying instabilities associated with a certain phase relation between the clock domains associated with said 5 selected new value.

6. The method of claim 5 comprising identifying instabilities associated with all possible phase relations between the clock domains corresponding to all possible values of the predetermined value ranging between minimal and maximal count values of the 10 first cyclical count process.

7. The method of any one of the preceding claims wherein the clock frequencies of the first and second clock domains are substantially equal, and wherein the count value of the first cyclical count process is used as the reset signal. 15

8. The method of claim 7 wherein the second cyclical count process is implemented by an Empty flag of the FIFO memory device.

9. The method of any one of the preceding claims comprising determining phase 20 relations optimal for transferring data by the FIFO memory device between the clock domains with constant latency based on the identified instabilities.

10. The method of claim 9 wherein the determining of the optimal phase relations comprises determining at least one phase relation that is relatively remote from at least 25 one of the phase relations associated with an identified instability.

11. The method of claim 10 wherein the determined at least one phase relation is in a range defined about a 180º phase shift of at least one of the phase relations associated with an instability. 30

12. The method of any one of claims 10 and 11 wherein the at least one of the phase relations associated with an instability is a phase relation for which a greatest number of meta-stabilities been identified. - 28 - 264939/2

13. The method according to any one of the preceding claims wherein a ratio of the clock frequencies of the first and second clock domains substantially equals to a ratio of the count cycles of the first and second cyclical count processes. 5

14. The method according to any one of the preceding claims wherein clock frequencies of the first and second clock-domains are frequency-locked to a common reference. 10 15. A method of operating a FIFO memory device the method comprising: calibrating said FIFO memory device using the method of any one of the preceding claims to identify the phase relations associated with the instabilities and determining therefrom optimal phase relations for conducting the data transfers between the clock domains by said FIFO memory device;

15. Continuously conducting the first and second cyclical count processes in their respective clock domains; determining a phase relation between clock signal of said clock domains based on count values of said first and second cyclical count processes; and starting data transfer between said first and second clock domains by said FIFO 20 memory device when the determined phase relation matches one of said optimal phase relations.

16. The method of any one of the preceding claims comprising carrying out calibration of the FIFO memory device during startup of at least one the clock domains. 25

17. The method of any one of claims 15 and 16 wherein the data transfers between first and second clock-domains are performed with constant latency.

18. A calibration circuitry for determining phase relationships prone to instabilities 30 in data transfers between first and second clock domains by a FIFO memory device, the calibration circuitry comprising: a first cyclical counter operated in said first clock domain, a cycle of said first cyclical counter being proportional to a clock frequency of said first clock domain; - 29 - 264939/2 a second cyclical counter operated in said second clock domain, a cycle of said second cyclical counter being proportional to a clock frequency of said second clock domain; a comparator configured to assert a reset signal for resetting said second counter 5 whenever count value of said first counter equals a predetermined value, said predetermined value associated with a certain phase relationship between clock signals of said first and second clock domains; and an instability detector configured to assert an instable indication signal if count value of said second counter is different from a maximal count value of said second 10 counter while said reset signal is asserted.

19. The circuitry of claim 18 configured to operate the first and second counters to carry a predefined number of cyclical counts corresponding to an average, or maximal, length of data transfer operation for identifying instabilities associated with a certain 15 phase relation between the clock domains.

20. The circuitry of any one of claims 18 and 19 comprising either a reference memory cell or counter for holding the predetermined value associated with the certain phase relationship. 20

21. The circuitry of claim 20 configured to store a new value in the reference memory cell, or to increment the reference counter, so as to set a new predetermined value for identifying instabilities associated with a certain phase relation between the clock domains associated with said new predetermined value. 25

22. The circuitry of any one of claims 17 to 21 comprising a synchronizer for passing the reset signal from the first clock-domain to the second clock-domain.

23. The circuitry of any one of claims 18 to 22 wherein the instability detector 30 comprises a comparator configured to assert a signal when the count value of the second counter equals a maximal count value of said second counter. - 30 - 264939/2

24. The circuitry of any one of claims 18 to 23 wherein a ratio of the clock frequencies of the first and second clock domains substantially equals to a ratio of the cycles of the first and second cyclical counters. 5

25. The circuitry of any one of claims 23 and 24 wherein the instability detector comprises a control unit configured and operable to monitor the reset signal and signals from the comparator of the instability detector, and determine instabilities associated with the certain phase relationship based thereon. 10

26. The circuitry of claim 25 wherein the control unit is configured and operable to operate the first and second counters to carry out a predefined number of cyclical counts corresponding to an average, or maximal, length of data transfer operation for identifying instabilities associated with the certain phase relation. 15

27. The circuitry of any one of claims 25 and 26 wherein the control unit is configured and operable to store a new predetermined value in the reference memory cell, or to increment the reference counter, and to operate the first and second counters to carry out a predefined number of cyclical counts for identifying instabilities associated with a certain phase relation between the clock domains corresponding to the 20 new value in the reference memory cell or counter.

28. The circuitry of any one of claims 25 to 27 wherein the control unit is configured and operable to identify instabilities associated with all possible phase relations between the clock domains. 25

29. The circuitry of any one of claims 18 to 28 wherein the cycles of the first and second cyclical counters equal one, and wherein the count value of said first cyclical counter is used as the reset signal.

30. 30. The circuitry of claim 29 wherein an empty-flag of the FIFO memory device is used to implement the second cyclical counter. - 31 - 264939/2

31. The circuitry of any one of claims 25 to 30 wherein the control unit is configured and operable to determine phase relations optimal for transferring data by the FIFO memory device between the clock domains with constant latency based on the identified instabilities. 5

32. The circuitry of claim 31 wherein the control unit is configured and operable to determine the optimal phase relations by determining at least one phase relation that is relatively remote from at least one of the phase relations associated with an identified instability. 10

33. The circuitry of claim 32 wherein the control unit is configured and operable to determine at least one phase relation in a range defined about a 180º phase shift of at least one of the phase relations associated with an instability. 15

34. The circuitry of any one of claims 32 and 33 wherein the at least one of the phase relations associated with an instability is a phase relation for which a greatest number of meta-stabilities been identified.

35. The circuitry of according to any one of claims 18 to 34 wherein the clock 20 frequencies of the first and second clock-domains are frequency-locked to a common reference.

36. Circuitry for operating a FIFO memory device to perform data transfers between first and second clock-domains, the circuitry comprising the calibration circuitry of any 25 one of claims 18 to 35 for calibrating said FIFO memory device to identify the instabilities phase relations and determining therefrom the optimal phase relations for data transfers, a timing module configured to continuously operate the first and second counters in their respective clock-domains for determining phase relation between the clock-domains based on count values of said first and second counters and asserting an 30 enable signal for starting data transfer by said FIFO memory device when the determined phase relation matches one of said optimal phase relations. - 32 - 264939/2

37. The circuitry of any one of claims 18 to 36 comprising a calibration module configured and operable to calibrate the FIFO memory device during startup procedure of at least one the clock-domains.