IE61763B1 - A microporcessor development system - Google Patents

Description

The present invention relates to a microprocessor development system.

There are many problems associated with the use of currently available microprocessor development systems. One such problem is lack of versatility as they are generally suitable for use with only one type of microprocessor and may not be easily modified for use with other types. Further, presently available microprocessor development systems do not adequately solve the problems of emulating microprocessors of the single-chip type which may share the functions of certain of the pins between the address/data functions and the input/output port functions. Additionally, such microprocessor development systems are generally limited in carrying out such operations as breakpoint assertion.

Finally, power supplies used for such systems often generate excessive heat and may constitute a safety hazard, especially where the equipment is serviced or configured by users.

The present invention is directed microprocessor development system problems . towards to providing a overcome these - 2 According to the invention there is provided a microprocessor development system comprisingsa control circuit for directing operation of the system; an interface circuit for output and reception of target microprocessor development data to and from a host computer; a monitor memory circuit for storage of target microprocessor monitor routines, said monitor memory circuit including a bootstrap read only memory circuit, connected to a random access memory circuit, and a memory control circuit which allows the random access memory to store monitor code which has been downloaded from the host computer, or to execute that monitor code; a breakpoint assertion circuit for assertion of breakpoints in target microprocessor memory addresses; a trace control and memory circuit operatively connected to an execution timer circuit; an emulation control and memory circuit connected to an external probe for connection with the target microprocessor; a target microprocessor programming circuit; and a power supply.

In one embodiment, the emulation control and memory circuit includes a serial random access memory circuit for connection with pins of a target microprocessor, said random access memory circuit being for conversion of serial information from said pins to parallel format for reception by the control circuit, and a port reconstruction circuit for reconstructing information normally transmitted on said pins.

In a further embodiment, the power supply is of the high efficiency linear-regulator type. Alternatively, the power supply is of the secondary switching regulator type.

The invention will be more clearly understood from the following description of some preferred embodiments thereof, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a microprocessor development system of the invention; - 4 Fig. 2 is a block diagram illustrating portion of the system; Fig. 3 is a block diagram illustrating another portion of the system; Fig. 4 is a circuit diagram illustrating portion of the system which connects with a certain type of target microprocessor; Fig. 5 and 6 are block diagrams illustrating alternative power supplies for use with the microprocessor development system.

Referring to the drawings and initially to Fig 1 there is illustrated a microprocessor development system of the invention, indicated generally by the reference numeral 1. The system 1 is illustrated in use connected to a host processor 2 and to a target microprocessor 3 by a probe 4. Control means for the system are provided by a control circuit 8 which controls an RS232C interface 9 for the host computer 2. The control circuit 8 also includes trace memory, execution timers and trigger processing logic. Microprocessor-specific in-circuit emulation means are provided by a family circuit 11 connected to the control circuit 8 by a trace bus 12 and by a general bus 13. The family circuit 11 includes emulation circuits and memory, and also breakpoint, trigger detection and mapping circuits. An emulation cable 15 is connected to the family circuit 11. The general bus 13 controls the synchronisation of all of the circuits of the system 1 and interconnects the control circuit 8, the family circuit 11 and a PROM programming circuit 16. The trace bus 12 connects the family circuit 11 to the trace memory of the control circuit 8. A power supply 17 delivers power to the system.

Briefly, in use, the host computer 2 is loaded with software which interacts with the system 1. A user source file is then inputted to the host computer 2 and an assembler or compiler converts the source file into object code which is stored in the host computer 2. The user may then use the system for emulation in which the code is run on the system 1 which simulates execution of the user's target microprocessor. In this case, the host computer 2 transmits the object code to random access memory of the system 1.

Alternatively, the system 1 may be used for in-circuit emulation which involves connecting the system 1 to the target microprocessor system by the probe 4. In this case, the system 1 generates all of the necessary control signals to run, analyse and monitor the target microprocessor system. When used for in-circuit emulation, the host computer 2 transmits the object code to random access memory of the target microprocessor system by the probe 4. Execution of the object code may be halted at breakpoints at which the current contents of registers, memory locations and input/output ports may be analyzed. The user may compare desired with actual microprocessor status using trace windows displayed on the screen of the host computer 2. The host computer 2 may be connected to a printer for printing of traces or microprocessor status and the user may opt for a trace of complete status of processor registers and flags after the execution of each instruction. Alternatively, traces of particular registers or memory locations may be printed only when the contents change.

Referring to Fig. 2, the control circuit 8 is illustrated in more detail. The purpose of the control circuit 8 is to carry out the operations which are common for emulation of any type of target microprocessor system. Thus, the control circuit 8 must be capable of interfacing with any type of family circuit 11 and also with the programming circuit 16. The control circuit 8 includes a microprocessor 20, the clock frequency of which is selected to provide the appropriate baud rate for the interface 9. There are many different memory areas, access to which is controlled by bank select control switches 21. Ths programs and data which are used for controlling the functions of the system are contained in a monitor memory 22. To ensure that the control circuit 8 is capable of initiating execution of a monitor program, and to ensure that it is capable of establishing communication with the host computer 2, it is necessary that the monitor memory 22 should include bootstrap monitor data which resides in EPROM. On the other hand, to ensure that the control circuit 8 is capable of executing a variety of different monitor programs corresponding to different types of target microprocessor, it is necessary that the monitor memory 22 should include monitor program data which resides in RAM, and which may be loaded with a specific monitor program by the host computer 2. In certain implementations, the control microprocessor 20 may be of a type, such as the 8031 type, which require that the program or code memory area of the microprocessor be separate from the data area. To overcome the problems of establishing communication with a bootstrap monitor which resides in EPROM, 1'5 of loading part of the monitor data into RAM, and of executing the monitor program in a separate program or code area, the monitor memory 22 includes circuits which allow monitor execution to switch from EPROM to RAM, and allow the RAM area to appear to the control microprocessor as either a data area (so as to allow the monitor program to be loaded) or as a code or program area (so as to allow the control microprocessor to execute a monitor program from that code or program area).

The control circuit 8 also includes a trace circuit 23 having trace memory, clock combination circuitry, start-stop circuitry, status bit circuitry, a trace address counter, interrupt circuitry and a circuit for reading back the trace. - 8 Tracing may be carried out in either a continuous mode or in a block mode. In the continuous mode, a start trigger initiates counting of the number of frames that are being traced. In the block mode, centre triggering is used and there is a circular buffer which is traced around until a start trigger occurs. To implement the block mode, a special counter, namely, a trace address counter is used.

The control circuit 8 also includes an execution timer 24 having three counters, the first of which handles the first 16 bits of the program timer, the second which handles the next 14 bits and the third which handles the last 14 bits. Power, emulate and command light emitting diodes (LED's) 25 and an expansion connector 26 are mounted on the control circuit 8.

An interface 27 is provided for the general bus 13, which includes separate buffers for data, for addresses, for a read line and for a write line. An event combination circuit 28 is provided for qualifying event signals transmitted from the target microprocessor system 3 via the general bus 13. An event ALU circuit 29 combines event signals which have been received and armed. Such event signals may be used for selection of data or to start a trigger.

The control circuit 8 includes a breakpoint circuit 30. For those types of target microprocessor which have an address range of 64K, the breakpoint circuit may be a RAM device of the 64K X 1 type to which the address bus of the target microprocessor 3 is applied. If the address should happen to correspond to a breakpoint address which has been set then the output data signal may be used to halt execution of the target program. For certain types of target microprocessor, it may be necessary to allow for a considerably wider address range than 64K, for example, 512K or 1 mbyte.

A typical family circuit 11 is illustrated in Fig. 3. As stated above, the family circuit 11 includes circuitry which is specific to the target microprocessor. More particularly the family circuit includes emulation circuitry, and memory, breakpoint, trigger detection and mapping circuitry in addition to various control logic elements associated with the emulation process.

Referring now to Fig. 4, portion of a family circuit 11 for use with a target microprocessor 3 such as that of the 8051 type is described. The target microprocessor 3 includes four ports PO to P3 of eight lines each. These ports are quasi bidirectional in that signals travel in both directions and there are no dedicated input or output ports. Such an arrangement may cause problems when the system 1 changes from the emulation mode to the command mode in which case it is possible that data must be transmitted to the control circuit 8. To ensure that operation of the target microprocessor is not interfered with by operation of the system 1, a reconstruction circuit 35 and a serial RAM 37 are connected to a line 38 connected to the port pin P3.7. The serial RAM 37 converts serial emulation information to parallel form for processing by the family circuit 11 and the control circuit 8. The reconstruction circuit 35 transmits information which would normally be transmitted on the line 38 for normal operation of the microprocessor 3 and ensures that the behaviour of these lines in the target system is identical to the behaviour of the target microprocessor itself, notwithstanding the use of the serial RAM 37 to transfer information to the control circuit.

Input signals on the pin P3.7 are applied to the target microprocessor 3 through a tri-state buffer 40. Output signals from the pin P3.7 are applied through the a D-type flip-flop circuit 36, an AND gate 41 and a tri-state buffer 42 to the external probe 4. During a read cycle in emulation mode, the input tri-state buffer 40 is enabled and the microprocessor 3 may accurately read the status of the pin P3.7 on the external probe 4. During a write cycle, output data from the target microprocessor 3 is latched into the flip-flop 36. If the microprocessor is sending out a logiclow signal, a flip-flop 43 activates the tri-state buffer 42, which in turn drives the pin P3.7 low. For a logic-high signal, the tri-state buffer 42 is disabled by the flip-flop 43, and the pin P3.7 is pulled to a logic-high state by the pull-up resistor 44. These characteristics accurately simulate the effect of the microprocessor port pin itself, while ensuring that during the monitor or control modes, the target microprocessor 3 may be isolated or effectively disconnected from the external probe 4 by disabling both tristate buffers 40 and 42. In monitor or control mode, the serial RAM 37 is halted by an enable circuit 37(b). The serial RAM 37 receives its input from the pin P3.7, and is clocked by a serial RAM address counter 45. The serial RAM data is transmitted to the general bus 13 by a bank select latch 46.

It will be appreciated that this feature of the invention allows use of the system 1 with microprocessors of the single-chip microcontroller type where the transfer of information in command mode must not be allowed to interfere with the behaviour of the target system.

Regarding the power supply 17, this is of the high efficiency linear regulator type illustrated in Fig. 5. Schottky diodes 50 are the main rectifying elements. A main series-pass transistor 51 has its base current derived from an auxiliary voltage supply 52 of a higher voltage than that of the main supply. The output supply current is measured by monitoring the voltage drop across a series output resistor 53 and a sample of the main DC supply is added to that voltage drop through a resistor 54 to allow the use of a low resistance value for the output resistor 53. Accordingly, the linear regulator power supply has a relatively high efficiency and there is lower heat dissipation than with conventional power supplies» Referring now to Fig. 8, there is illustrated an alternative construction of power supply, namely, a secondary switching power supply 60 having a conventional mains frequency isolation transformer 61 which provides a low voltage secondary output. Thus, the design provides the high efficiency which is characteristic of switching regulator designs but it does not expose the users of the system to dangerous electric shock which would exist if the switching regulator operated at a high voltage.

It will be appreciated that the microprocessor development system of the invention is extremely versatile because control and monitor data and software are stored in random access memory of the control circuit. Heretofore, various control programs were stored in ROM and thus a microprocessor development system could not be used with the various different types of microprocessor without physically removing and replacing the ROM. Further, the system allows for the updating of various control features simply by changing the software loaded in the host computer 2, which software is down-loaded to the monitor RAM. It will also be appreciated that the system 1 provides for the normal operation of a target microprocessor having no dedicated address bus. > 1. A microprocessor development system comprisings~ a control circuit for directing operation of the system; an interface circuit for output and reception of target microprocessor development data to and from a host computer; a monitor memory circuit for storage of target microprocessor monitor routines which define said monitor memory circuit including a bootstrap read only memory circuit, a random access memory circuit, and a memory control circuit which allows the random access memory to store monitor code which has been downloaded from the host computer, or to execute that monitor code; a breakpoint assertion circuit for assertion of breakpoints in target microprocessor memory addresses; a trace control and memory circuit operatively connected to an execution timer circuit; an emulation control and memory circuit connected to an external probe for connection with the target microprocessor; a target microprocessor programming circuit; and a power supply. 2. A microprocessor development system as claimed in claim

Claims (2)

1. , in which the emulation control and memory circuit includes a serial random access memory circuit for connection with pins of a target microprocessor, said 10 random access memory circuit being for conversion of serial information from said pins to parallel format for reception by the control circuit, and a port reconstruction circuit for reconstructing information normally transmitted on said pins. 15 3. A microprocessor development system as claimed in claims 1 or 2, wherein the power supply is of the high efficiency linear-regulator type. 4. A microprocessor development as claimed in claims 1 or

2. , wherein the power supply is of the secondary switching regulator type.