IE43367L - Time-division switching system - Google Patents

Abstract

1529106 Automatic exchange systems NORTHERN TELECOM Ltd 2 April 1976 [23 April 1975] 13469/76 Heading H4K A pcm conference circuit is arranged to deal simultaneously with a plurality of three or more party conferences, the circuit introducing a delay of two frames. An interface and control 10 extracts from the pcm highways of the system pcm speech samples in time slots concerned with conference calls and presents the speech samples over an 8 channel serial highway to the conference circuit in isochronous (interleaved bit) form, i.e. each channel comprises 32 bits, with the first bit of each of 32 pcm words being transmitted in channel 0, and the eighth bit in channel 7 etc. The conference circuit includes two 32 word, 8 bit, RAM memories I and II, one of the memories being fed with the incoming serial bit stream during one frame, whilst information fed into the other memory during the previous frame is being processed, the units MUX, 11, 11<SP>1</SP>, enabling the 32 speech samples to be stored in the RAM's in 8 bit parallel form. The processing frame of the conference circuit is divided into eight periods, period 0 not being used. During period 1 each 8 bit word in the RAM e.g. RAM1 written during the previous frame is used to address a read only memory 14 to convert the word into a 14 bit linear PCM word, and each linear word is added to a location of an accumulator 16 corresponding to the conference to which the word relates. During period 2, the 8 bit words are again supplied to address ROM 14, but with their sign bit changed such that a 14 bit word in 2's complement form is produced at the output of ROM, 14. This word is then added to the accumulator contents value for the corresponding conference (hence effectively subtracting the word of the subscriber) and the first 8 bits of the total are written into the location of RAM I corresponding to the read 8 bit word and the remaining 6 bits are stored in a corresponding location of an additional memory RAM III. The accumulator contents remain unchanged. During period 3, the 14 bit words stored jointly in RAM I and RAM III are converted back into companded 8 bit form using compressor 18 and are fed back into the corresponding locations of RAM I. During periods 4-7 RAM III and accumulator 16 are cleared, and in the following frame the contents of RAM I are read out via interface 10 to the subscriber time slots, thereby providing each subscriber of a conference with a PCM word representing the total speech of all the other subscribers of the conference. Where the number of conferees is between 6 and 12 the ROM 14 may be enabled to produce attenuated linearly coded words. The circuit may also be switched to a public address mode by causing the ROM 14 to produce words comprising logical 1's for all except a designated speaker. [GB1529106A]