HU195889B - Intelligent information storing system in particular to computers - Google Patents

Abstract

The present invention relates to an intelligent information storage system, particularly for use in computers. According to the invention, according to Fig. 1, there is a computer central unit (1) connected to a computer bus (2) per se known as well as a memory circuit (5) connected to a computer bus (2) via a memory control circuit (4), besides the computer. bus (2) is connected to a computer central unit (1), or a disconnection unit (3) is inserted between the part of the memory control circuit (4) and a peripheral controller for a portion of the computer bus (2) connected to the memory control circuit (4). circuit (6) and interconnected bus control circuit (7) and memory control central unit (S) are connected, and the memory control central unit (8) is connected to the isolation unit (3). -1-

Description

The present invention relates to an intelligent information storage system, in particular for use with computers.

Modern computers generally use various memories to store instructions and data. In known systems, communication between the central unit of the computer and the memory of the computer is effected by low-level commands, i.e. the central unit of the computer directly controls the individual memory operations via the bus system of the computer, of course through the appropriate memory controller.

In this way, the internal control of these memories locates, stores, transmits and checks data and blocks of data, and fetches and retrieves them from and to various peripherals, significantly consumes the central unit, operating memory, and bus system of the computer.

Computers require fast and reliable management of large amounts of data stored, as well as the use of central processing unit memory for the shortest time possible. Given that memory operations are often associated with mechanical movements (such as searching for paths) and without waiting for these mechanical movements to complete, direct control of memory operations is highly demanding on the central unit of the computer.

The object of the present invention is to expedite the operation of a computer by releasing a central unit of computers from a substantial portion of memory management tasks.

It is an object of the present invention to provide apparatus for relieving a central processing unit of a computer from direct memory control.

According to the present invention, the above object is solved by a device comprising a computer central unit connected to a computer bus and also a memory circuit connected to the computer bus via a memory control circuit, the part of the computer bus connected to the central unit and the memory control circuit. and a peripheral control circuit is connected to the portion of the computer bus connected to the memory control circuit, and a bus control circuit and a memory control central unit are connected to each other, and the memory control central unit is connected to the isolation unit.

The structure and operation of the apparatus according to the invention will be described in more detail on the basis of an exemplary embodiment, a time diagram and a flow chart illustrated in the accompanying drawings.

In the accompanying drawings, Figure 1 is a block diagram of an embodiment of the apparatus of the invention, a

Figure 2 is a time diagram of the operation of the apparatus of Figure 1, while Figure

Figure 3 is a flow diagram of the operation of the apparatus of Figure 1.

As shown in Figure 1, the apparatus comprises a computer central unit 1, a computer bus 2, a disconnector unit 3, a memory control circuit 4, a memory circuit 5, a peripheral control circuit 6, a bus control circuit 7 and a memory control central unit 8.

The computer central unit 1 is connected to the computer bus 2. The memory circuit 5 is connected via a memory control circuit, and the peripheral control circuit 6, and the interconnected bus control circuit 7 and the memory control central unit 8 are also connected to a computer bus 2 having a computer central unit and a memory control central unit. The separation unit 3 is inserted between the two. The memory control central unit 8 is in communication with the isolator 3.

In this embodiment of the apparatus according to the invention, the computer central unit 1 and the memory control central unit 8 are provided. aMotorola; with 68000 microprocessor, computer bus 2 with a known VME bus, disconnector unit 3 with bidirectional bus drivers SN 74 LS 245, memory circuit with MK 4564 dram memory circuits, and memory control circuit 4 with a memory circuit adapted to the above memory circuit , and the peripheral control circuit 6 can be implemented with any Motorola peripheral control circuit adapted to the VME bus, and the bus controller 7 can be implemented with a SCB 68 172 circuit.

The operation of the apparatus according to the invention will be described in more detail below with reference to Figures 2 and 3.

The computer central unit 1 addresses the memory control central unit 8 prior to performing the memory operation and sends the appropriate instruction on the data lines.

The memory control central unit 8 decodes the command and, in the case of some selected commands, which are expected to take longer, activates the isolator 3, which separates the computer bus 2 connected to the computer central unit 1 and the memory control circuit 4 memory-related part.

Thereafter, the memory control central unit 8 executes, via the bus control circuit 7, the commands sent by the computer port unit 1, e.g. writing to and reading from a memory circuit 5 to a peripheral via a peripheral control circuit 6.

During the execution of the instruction, the computer central unit 1 may work freely on the computer bus 2 because the disconnecting unit 3 completely separates the two parts of the computer bus 2.

After the instruction of the computer central unit 1 has been executed by the memory control central unit 8, it removes the separation of the two parts of the computer bus 2 by deactivating the isolation unit 3, and then interrupts in a manner known per se.

195 889 requests via computer bus 2 from computer central unit 1 to report execution of the instruction.

Line A of the time diagram of Figure 2 shows the appearance of the address issued by the central processing unit 1 and Line B shows the appearance of the address validation signal. Line C represents the output of the instruction containing data, while line D represents the data validation signal. After data validation, the instruction is decoded by the memory control unit 8 ¹ θ, and if the decoded instruction is one of the selected, the BUS SEP bus disconnection signal is displayed according to line E of FIG. under.

Line F of Figure 2 shows the end of command instruction, followed by line G, the IRQ interrupt request signal indicating that the computer 1 has executed the command issued. 20

Figure 3 essentially describes the above process.

An advantage of the intelligent information system according to the invention is that it significantly improves the operational efficiency of the computer by its ability to independently store, manage, process, copy, convert, verify, transfer data and blocks of data managed by the computer with simple control, and to connect peripherals without using the computer's central processing unit.

Claims (1)

Apparatus for intelligent storage of information, in particular for use with computers, comprising a computer central unit connected to a computer bus and a memory circuit connected to a computer bus via a memory control circuit, characterized in that the computer bus (2) an isolation unit (3) is provided between the connector portion and the portion of the memory control circuit (4), and optionally a peripheral control circuit (6) and a bus control circuit interconnected to the portion of the computer bus (2) connected to the memory control circuit (4) (7) and the memory control central unit (8) are connected, and the memory control central unit (8) is connected to the isolation unit (3).