GB9908209D0 - Parallel data processing apparatus - Google Patents

Parallel data processing apparatus

Info

Publication number
GB9908209D0
GB9908209D0 GBGB9908209.1A GB9908209A GB9908209D0 GB 9908209 D0 GB9908209 D0 GB 9908209D0 GB 9908209 A GB9908209 A GB 9908209A GB 9908209 D0 GB9908209 D0 GB 9908209D0
Authority
GB
United Kingdom
Prior art keywords
processing apparatus
data processing
parallel data
parallel
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9908209.1A
Other versions
GB2348976A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pixelfusion Ltd
Original Assignee
Pixelfusion Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB9908209A priority Critical patent/GB2348976A/en
Application filed by Pixelfusion Ltd filed Critical Pixelfusion Ltd
Publication of GB9908209D0 publication Critical patent/GB9908209D0/en
Priority to JP2000611183A priority patent/JP5285828B2/en
Priority to PCT/GB2000/001332 priority patent/WO2000062182A2/en
Priority to EP00917203A priority patent/EP1181648A1/en
Priority to AU38295/00A priority patent/AU3829500A/en
Publication of GB2348976A publication Critical patent/GB2348976A/en
Priority to US09/972,797 priority patent/US7363472B2/en
Priority to US11/615,849 priority patent/US20080040575A1/en
Priority to US11/615,833 priority patent/US20080184017A1/en
Priority to US11/620,014 priority patent/US7526630B2/en
Priority to US11/621,946 priority patent/US7966475B2/en
Priority to US11/621,952 priority patent/US7506136B2/en
Priority to US11/669,868 priority patent/US7925861B2/en
Priority to US11/678,556 priority patent/US20070242074A1/en
Priority to US11/748,367 priority patent/US20080008393A1/en
Priority to US11/750,982 priority patent/US20080016318A1/en
Priority to US11/750,951 priority patent/US7627736B2/en
Priority to US11/750,968 priority patent/US20070294510A1/en
Priority to US11/754,901 priority patent/US8169440B2/en
Priority to US11/759,211 priority patent/US20080007562A1/en
Priority to US11/759,205 priority patent/US8174530B2/en
Priority to US11/765,421 priority patent/US20080162874A1/en
Priority to US11/772,067 priority patent/US8762691B2/en
Priority to US11/772,079 priority patent/US7802079B2/en
Priority to US11/772,037 priority patent/US8171263B2/en
Priority to US11/774,500 priority patent/US20080162875A1/en
Priority to US12/363,690 priority patent/US20090198898A1/en
Priority to US12/404,222 priority patent/US7958332B2/en
Priority to JP2010222021A priority patent/JP2011023036A/en
Priority to JP2010222022A priority patent/JP2011023037A/en
Priority to US15/073,573 priority patent/US20160283241A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
GB9908209A 1999-04-09 1999-04-09 Single instruction multiple data array Withdrawn GB2348976A (en)

Priority Applications (30)

Application Number Priority Date Filing Date Title
GB9908209A GB2348976A (en) 1999-04-09 1999-04-09 Single instruction multiple data array
JP2000611183A JP5285828B2 (en) 1999-04-09 2000-04-07 Parallel data processor
PCT/GB2000/001332 WO2000062182A2 (en) 1999-04-09 2000-04-07 Parallel data processing apparatus
EP00917203A EP1181648A1 (en) 1999-04-09 2000-04-07 Parallel data processing apparatus
AU38295/00A AU3829500A (en) 1999-04-09 2000-04-07 Parallel data processing apparatus
US09/972,797 US7363472B2 (en) 1999-04-09 2001-10-09 Memory access consolidation for SIMD processing elements having access indicators
US11/615,833 US20080184017A1 (en) 1999-04-09 2006-12-22 Parallel data processing apparatus
US11/615,849 US20080040575A1 (en) 1999-04-09 2006-12-22 Parallel data processing apparatus
US11/620,014 US7526630B2 (en) 1999-04-09 2007-01-04 Parallel data processing apparatus
US11/621,946 US7966475B2 (en) 1999-04-09 2007-01-10 Parallel data processing apparatus
US11/621,952 US7506136B2 (en) 1999-04-09 2007-01-10 Parallel data processing apparatus
US11/669,868 US7925861B2 (en) 1999-04-09 2007-01-31 Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution
US11/678,556 US20070242074A1 (en) 1999-04-09 2007-02-23 Parallel data processing apparatus
US11/748,367 US20080008393A1 (en) 1999-04-09 2007-05-14 Parallel data processing apparatus
US11/750,968 US20070294510A1 (en) 1999-04-09 2007-05-18 Parallel data processing apparatus
US11/750,982 US20080016318A1 (en) 1999-04-09 2007-05-18 Parallel data processing apparatus
US11/750,951 US7627736B2 (en) 1999-04-09 2007-05-18 Thread manager to control an array of processing elements
US11/754,901 US8169440B2 (en) 1999-04-09 2007-05-29 Parallel data processing apparatus
US11/759,211 US20080007562A1 (en) 1999-04-09 2007-06-06 Parallel data processing apparatus
US11/759,205 US8174530B2 (en) 1999-04-09 2007-06-06 Parallel date processing apparatus
US11/765,421 US20080162874A1 (en) 1999-04-09 2007-06-19 Parallel data processing apparatus
US11/772,067 US8762691B2 (en) 1999-04-09 2007-06-29 Memory access consolidation for SIMD processing elements using transaction identifiers
US11/772,079 US7802079B2 (en) 1999-04-09 2007-06-29 Parallel data processing apparatus
US11/772,037 US8171263B2 (en) 1999-04-09 2007-06-29 Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions
US11/774,500 US20080162875A1 (en) 1999-04-09 2007-07-06 Parallel Data Processing Apparatus
US12/363,690 US20090198898A1 (en) 1999-04-09 2009-01-30 Parallel data processing apparatus
US12/404,222 US7958332B2 (en) 1999-04-09 2009-03-13 Parallel data processing apparatus
JP2010222022A JP2011023037A (en) 1999-04-09 2010-09-30 Parallel data processing apparatus
JP2010222021A JP2011023036A (en) 1999-04-09 2010-09-30 Parallel data processing apparatus
US15/073,573 US20160283241A1 (en) 1999-04-09 2016-03-17 Parallel data processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9908209A GB2348976A (en) 1999-04-09 1999-04-09 Single instruction multiple data array

Publications (2)

Publication Number Publication Date
GB9908209D0 true GB9908209D0 (en) 1999-06-02
GB2348976A GB2348976A (en) 2000-10-18

Family

ID=10851286

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9908209A Withdrawn GB2348976A (en) 1999-04-09 1999-04-09 Single instruction multiple data array

Country Status (1)

Country Link
GB (1) GB2348976A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2391083B (en) * 2002-07-19 2006-03-01 Picochip Designs Ltd Processor array
US8086806B2 (en) 2008-03-24 2011-12-27 Nvidia Corporation Systems and methods for coalescing memory accesses of parallel threads
US8392669B1 (en) 2008-03-24 2013-03-05 Nvidia Corporation Systems and methods for coalescing memory accesses of parallel threads

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4590465A (en) * 1982-02-18 1986-05-20 Henry Fuchs Graphics display system using logic-enhanced pixel memory cells
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures
GB8925721D0 (en) * 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5828894A (en) * 1990-11-13 1998-10-27 International Business Machines Corporation Array processor having grouping of SIMD pickets
JP3300776B2 (en) * 1994-03-15 2002-07-08 株式会社日立製作所 Switching control method for parallel processors

Also Published As

Publication number Publication date
GB2348976A (en) 2000-10-18

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)