GB9200207D0 - Computer memory array control - Google Patents
Computer memory array controlInfo
- Publication number
- GB9200207D0 GB9200207D0 GB929200207A GB9200207A GB9200207D0 GB 9200207 D0 GB9200207 D0 GB 9200207D0 GB 929200207 A GB929200207 A GB 929200207A GB 9200207 A GB9200207 A GB 9200207A GB 9200207 D0 GB9200207 D0 GB 9200207D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory units
- host computer
- data
- memory
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B2020/10916—Seeking data on the record carrier for preparing an access to a specific address
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Signal Processing (AREA)
- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Abstract
A computer memory controller for interfacing to a host computer comprises a buffer memory (26) for interfacing to a plurality of memory units (42) and for holding data read thereto and therefrom. A central controller (22) operative to control the transfer of data to and from the host computer and the memory units (42). The buffer memory (26) is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units (42). The central controller (22) is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller (22) is also operative in response to data requests from the host computer to control the memory units (42) to seek data stored in different memory units (42) simultaneously.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB929200207A GB9200207D0 (en) | 1992-01-06 | 1992-01-06 | Computer memory array control |
EP92924811A EP0620934A1 (en) | 1992-01-06 | 1992-12-10 | Computer memory array control |
CA002127380A CA2127380A1 (en) | 1992-01-06 | 1992-12-10 | Computer memory array control |
PCT/GB1992/002291 WO1993014455A1 (en) | 1992-01-06 | 1992-12-10 | Computer memory array control |
US07/988,831 US5526507A (en) | 1992-01-06 | 1992-12-10 | Computer memory array control for accessing different memory banks simullaneously |
JP5511984A JPH08501643A (en) | 1992-01-06 | 1992-12-10 | Computer memory array control |
AU30915/92A AU662376B2 (en) | 1992-01-06 | 1992-12-10 | Computer memory array control |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB929200207A GB9200207D0 (en) | 1992-01-06 | 1992-01-06 | Computer memory array control |
Publications (1)
Publication Number | Publication Date |
---|---|
GB9200207D0 true GB9200207D0 (en) | 1992-02-26 |
Family
ID=10708187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB929200207A Pending GB9200207D0 (en) | 1992-01-06 | 1992-01-06 | Computer memory array control |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0620934A1 (en) |
JP (1) | JPH08501643A (en) |
AU (1) | AU662376B2 (en) |
CA (1) | CA2127380A1 (en) |
GB (1) | GB9200207D0 (en) |
WO (1) | WO1993014455A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5375084A (en) * | 1993-11-08 | 1994-12-20 | International Business Machines Corporation | Selectable interface between memory controller and memory simms |
EP0727750B1 (en) * | 1995-02-17 | 2004-05-12 | Kabushiki Kaisha Toshiba | Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses |
US5937174A (en) * | 1996-06-28 | 1999-08-10 | Lsi Logic Corporation | Scalable hierarchial memory structure for high data bandwidth raid applications |
US5881254A (en) * | 1996-06-28 | 1999-03-09 | Lsi Logic Corporation | Inter-bus bridge circuit with integrated memory port |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4958351A (en) * | 1986-02-03 | 1990-09-18 | Unisys Corp. | High capacity multiple-disk storage method and apparatus having unusually high fault tolerance level and high bandpass |
US4993030A (en) * | 1988-04-22 | 1991-02-12 | Amdahl Corporation | File system for a plurality of storage classes |
AU630635B2 (en) * | 1988-11-14 | 1992-11-05 | Emc Corporation | Arrayed disk drive system and method |
-
1992
- 1992-01-06 GB GB929200207A patent/GB9200207D0/en active Pending
- 1992-12-10 CA CA002127380A patent/CA2127380A1/en not_active Abandoned
- 1992-12-10 EP EP92924811A patent/EP0620934A1/en not_active Ceased
- 1992-12-10 JP JP5511984A patent/JPH08501643A/en active Pending
- 1992-12-10 WO PCT/GB1992/002291 patent/WO1993014455A1/en not_active Application Discontinuation
- 1992-12-10 AU AU30915/92A patent/AU662376B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
CA2127380A1 (en) | 1993-07-22 |
EP0620934A1 (en) | 1994-10-26 |
AU662376B2 (en) | 1995-08-31 |
JPH08501643A (en) | 1996-02-20 |
WO1993014455A1 (en) | 1993-07-22 |
AU3091592A (en) | 1993-08-03 |
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