GB892112A - Improvements relating to serial digital multiplying and dividing devices - Google Patents

Abstract

892,112. Binary calculating apparatus. ELECTRIC & MUSICAL INDUSTRIES Ltd. May 27, 1958 [Feb. 26, 1957; March 1, 1957], Nos. 6370/57 and 6820/57. Class 106 (1). Binary multiplication or division is carried out in the serial-made by two arithmetic units each receiving the output from one half of a 2n digit circulating store for the product or dividend, so that two arithmetic operations can be carried out simultaneously. Fig. 2 of the second Provisional Specification shows a multiplier for binary numbers of n digits each (negative numbers being expressed as 2's complements) using a method involving successive examination of the pairs of neighbouring multiplier digits and selectively either adding the multiplicand A into the partial product and shifting it one digit, subtracting it from the partial product and shifting it one digit, or simply shifting it one digit according as b r (the rth digit of the multiplier B) <, > or = b r-1 respectively (b 1 = least significant digit; b o to be regarded as = O). A and B are fed into circulating stores 2 and 16 respectively, the last (most significant) digit of A being examined at 3 and then continuously emitted by a complement extender 4 to enable the extension of A to up to 2n digits for adding into or subtracting from the partial product which circulates continuously through half stores 14 and 15 of n digits capacity each in the direction shown. A frequency divider 10 divides clock pulses from 9 by (n+1) and acts through a trigger 11 and gates 5-8 to switch the multiplicand and its extension alternately to units 12 and 13 (store 2 having n+1 places to ensure this) so that two arithmetic operations may simultaneously be carried out on the partial product; since the switching takes place every minor cycle of n+1 pulses while each half store 14, 15 is n digits long the multiplicand is effectively shifted one digit relative to the partial product in the direction of increasing significance. The commands to add or subtract are passed to units 12 and 13 when necessary by triggers 26-29 in accordance with the output from digit detector 17 which examines the digits of B successively after each (n+1) clock pulses; any change in the output passes through gate 18 if b r > b r-1 and through gate 19 if b r < b r-1 to set one of the triggers 26-29 according to the output of trigger 21 which is switched at the end of every minor cycle, the triggers 26-29 remaining unchanged for 2 minor cycles since terminals 30 and 32 receive pulses at the end of odd minor cycles and 31 and 33 at the end of even minor cycles. Hence each unit 12 or 13 receives A in one minor cycle followed by its extension in the following minor cycle, the appropriate command according to two successive digits of B from one of triggers 26-29 during the two minor cycles and the partial product correctly phased according to the digits of B examined; at the end of the second minor cycle any carry is suppressed by a pulse applied at 34 or 35. Fig. 2 of the first Provisional Specification shows a divider using many units similar to those shown in the multiplier above described, receiving a dividend A of 2n digits by means not shown and storing it in circulating dividend (or partial remainder) store 14 and 15, and divisor B of n digits which is stored in 2 and examined for production of an extended complement at 4 as before. The output of 4 represents the sign of B, and this is compared by 46 or 47 at the end of each minor cycle with the sign of the partial remainder obtained from 44 or 45 respectively; if they are the same B is subtracted from A in 13 or 12 and a " 1 " is inserted in the corresponding digit position of the quotient, and if they are different B is added to A in 13 or 12 and a "0" inserted, a shift in the direction of decreasing significance of the divisor relative to the partial remainder being obtained between each sign comparison by making store 2 of (n - 1) digits and the unit 10 a divider by (n-1) of the clock pulses. Insertion of the correct digit into the quotient is effected by supplying a series of "1 " 's and a series of " 0 " 's to 53 and 54 respectively, one of these series being passed by gate 51 or 52 (depending on the sign comparison result) to a gate 55 which receives a clock pulse at 56 to " erase " any digit stored in the appropriate position (gate 57) and insert the quotient digit. After n minor cycles the quotient register is full, but two further cycles take place, the first being an (n+1)th addition (or subtraction) with insertion of the appropriate quotient digit to overwrite that first-written and the second being used to overwrite the second-written digit with a " 1." The Specification contains the mathematical justification for this division method.