GB875374A - Apparatus for generating a clock pulse train from an information representing electrical wave and for reading out information stored on a magnetic storage medium - Google Patents

Abstract

875,374. Digital data-storage apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd. Jan. 24, 1958 [Jan. 28, 1957], No. 2420/58. Class 106 (1). Apparatus for generating a clock pulse train from an information representing electrical wave having true polarity cross-overs at some or all of a series of regularly recurrent instants (a true polarity cross-over being one after which the polarity remains unchanged for a time at least equal to the recurrence period of said instants) comprises means for generating a clock pulse in response to the occurrence of each true polarity cross-over, means responsive to the generation of a clock pulse to produce a further clock pulse after an interval equal to the recurrence period of said instants and means responsive to the occurrence of a true polarity cross-over to prevent the production of a further clock pulse in response to the last preceding clock pulse. As described data, Fig. 5 (A), is read from a drum Fig. 1 (not shown), amplified and shaped to give outputs Figs. 5 (C), 5 (D) from which cross-over pulses Figs. 5 (E), 5 (F) are formed which are mixed and delayed by 1“ bit periods, Fig. 5 (G), and then processed to produce correctly timed pulses (Fig. 5 (J), not shown) occurring exactly at times 1, 2, 3, 4, &c., the processing being such that (a) cross-over pulses produced from spurious cross-overs, such as those occurring between times 13 and 16, are rejected, (b) the remaining cross-over pulses produced from genuine cross-overs are delayed a further “ bit period to bring them to the times 1, 2, 3, 4, &c., and (c) any time 1, 2, 3, 4, &c. then without a clock pulse is given one by delaying the immediately preceding pulse by one or more bit periods. Spurious cross-over pulses are separated from genuine cross-over pulses by means of a two-stage register comprising flip-flops FF5, FF6, Fig. 4, through which data read from the drum is stepped, and whose state is examined by gates G15, G16. If the flip-flop register stores 0, 1 or 1, 0 then gate G15 or G16 will set a flip-flop FF7 thereby opening a gate G1 and allowing the next delayed cross-over pulse, Fig. 5 (G), to enter a 1 bit delay line, which, with a gate G2 forms a recirculatory clockpulse store from which clock-pulses are taken at a “ bit tapping. If the register stores 0, 0 or 1, 1, gates G15 and G16 both remain closed, flip-flop FF7 is not set, having been reset by the last clock-pulse, and any crossover pulse (which will of course be spurious) is blocked at gate G1. Thus, only genuine cross-over pulses enter the delay line to provide clock-pulses with which to interpret data from the drum taken from flip-flop FF6 via a gate G3. In the particular embodiment described data is not read-out until a block start signal, comprising a train of 16 alternate ones and zeros followed by two ones and a zero, is read. When this is recognized (Figs. 2 and 3, not shown), gate G3 is opened. Specification 836,360 is referred to.