GB737498A - Testing arrangements for intelligence storage equipment - Google Patents

Abstract

737,498. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. March 25, 1953, No. 8232/53. Class 106 (1). Intelligence storage equipment comprises a memory device subdivided into a number of separate storage sections and a test section, recording and reading means associated with the memory device and arranged to co-operate with the sections, a control circuit associated with the recording and reading means and arranged to perform a sequence of operations in co-operation with the respective storage sections, means responsive to the bringing of the test section into operative relation with the recording and reading means to initiate a test sequence of operations by the control circuit, means for checking the test sequence and means for indicating if the test sequence is not correctly performed. In a first embodiment the equipment comprises a magnetic drum memory 1, Fig. 1, having read/record heads 5, 6, 7 cooperating with tracks 2, 3, 4. Each track is divided into a number of individual sections which need not be of equal length, the beginning of each section being defined by signals on a marker track 9, which signals are fed to a counter MPC. Each possible element position is defined by signals on a clock track 10, which signals step on a counter CPC to register the number of elements in each section before being zeroized by a signal from track 9 marking the beginning of the next section. In the present example the eleventh (last) section of each information track 2, 3, 4, &c., is used for testing purposes. The energization of the eleventh section of the counter MPC opens a gate G12 to allow the reading of this section of the track to pass to a testing device 13. Information is recorded in each section in binary code and, after being picked up by the reading head, is either returned to the record surface unchanged or, if a signal is present on the incoming line associated with the section under examination, the binary value is increased by one by recording the reverse of each binary digit received up to and including the first zero and thereafter recording the digits unchanged. The test section, however, provides only one binary digit position, and since a signal T, representing an incoming line signal, is provided permanently at a gate G11, the binary digit in the test section alternates between " 1 " and " 0 " continuously. These alternations may be compared with the alternations of a trigger circuit operated by the zeroizing pulse of the counter MPC. Any disagreement would give an output to operate an alarm 14. A single common control circuit 8 may be associated with a number of tracks in turn by employing an additional " track counter " (Fig. 2, not shown). Other embodiments are described in which the memory unit consists of (1) a mercury delay line, (2) a CRT-type memory, (3) a matrix of saturable magnetic cores, and (4) a matrix of ferroelectric elements.