GB2600569A

GB2600569A - III-V / silicon optoelectronic device and method of manufacture thereof

Info

Publication number: GB2600569A
Application number: GB2118589.7A
Authority: GB
Inventors: Yu Guomin; Zilkie Aaron-John
Original assignee: Rockley Photonics Ltd
Current assignee: Rockley Photonics Ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2022-05-04
Anticipated expiration: 2039-11-15
Also published as: GB2589092A; GB2589092B; WO2021094473A1; GB201916700D0; GB2600569B

Abstract

A method of manufacturing a device coupon, suitable for use in a transfer printing process, having the steps of: growing a multi-layered stack on a substrate 706, comprising one or more III-V semiconductor based optically active layers; fabricating one or more III-V semiconductor based photonic components from the multi-layered stack; and coating one or more lateral sides of the III-V semiconductor based photonic component(s) with an anti-reflective coating 111. The method may comprise providing first and second electrodes 105a,105b which electrically connect to respective layers of the multi-layered stack. Also disclosed is the device coupon produced from this method.

Description

Ill-V/ SILICON OPTOELECTRONIC DEVICE AND METHOD OF MANUFACTURE

THEREOF

Field of the Invention

The present invention relates to a III-V / Silicon optoelectronic device and method of making the same.

Background

Hybrid integration of III-V semiconductor based electro-optical devices, (e.g. modulators) with silicon-on-insulator (S01) platforms by chip bonding confers the advantage of combining the best parts of both material systems.

However, conventional chip bonding processes typically use flip-chip bonding, in which the III-V semiconductor based device is upside down and bonded into a cavity on the 301 platform. Devices fabricated using these methods typically suffer from high optical coupling losses between a waveguide in the III-V semiconductor based device and a waveguide in the SOI. Further the manufacturing process has a low yield, and relatively low reliability because of difficulties in accurately controlling the alignment of the respective waveguides.

Micro-transfer printing (MTP) is therefore being looked into, as an alternative way to integrate III-V semiconductor based devices with SOI wafers. In these methods, the III-V semiconductor based device can be printed into a cavity on the SOI in the same orientation it was manufactured, and the alignment between the III-V semiconductor based waveguide and the 501 waveguide is pre-determined in the vertical direction (Z-direction). The requirements for alignment are therefore reduced from three dimensions to two, which can be more easily facilitated.

However, an issue with MTP arises from the gap that exists between the III-V semiconductor based waveguide and the 301 waveguide facets. Although the gap width can typically be well controlled (e.g. within the range 0.5 pm to 1.5 pm) it can cause the following issues: (i) a high optical coupling loss between the III-V semiconductor based waveguide and the 301 waveguide; and (ii) it leaves a gap in which particles, debris, or dirt may infiltrate, which can block the optical path, this reduces the device's long term reliability.

Therefore there is a need for a method of manufacturing an optoelectronic device, and the resultant optoelectronic device, which overcomes the shortcomings identified above.

Summary

Accordingly, embodiments of a first aspect of the invention provide a method of manufacturing an optoelectronic device, the manufactured device including a III-V semiconductor based photonic component coupled to a silicon waveguide, the method comprising: providing a device coupon, the device coupon including the III-V semiconductor based photonic component; providing a silicon platform, the silicon platform comprising a cavity within which is a bonding surface for the device coupon; transfer printing the device coupon onto the cavity, such that a surface of the device coupon directly abuts the bonding surface and at least one channel is present between the device coupon and a sidewall of the cavity; and filling the at least one channel with a filling material via a spin-coating process, to form a bridge coupling the III-V semiconductor based photonic component to the silicon waveguide.

The method uses simple fabrication processes, and the method is suitable for volume production. Moreover, the resulting devices demonstrate reduced levels of optical loss.

The method may have any one or, to the extent that they are compatible, any combination of the following optional features.

The III-V semiconductor based photonic component may be any one: an electro-absorption modulator; a laser; a photodetector; a semiconductor optical amplifier. The device coupon may include two or more III-V semiconductor based photonic components, and may include any combination of the photonic components listed above. For example the device coupon may include a laser and an electro-absorption modulator; a laser, an electro-absorption modulator, and a semiconductor optical amplifier; or a laser, an electro-absorption modulator, a semiconductor optical amplifier, and a photodetector.

The III-V semiconductor based photonic component may include a III-V semiconductor based waveguide. One or more photonic components may be integrated into the III-V semiconductor based waveguide.

The bridge may not be waveguide, in that it may not function so as to confine an optical mode within the bridge structure.

The method may include a step of curing the filling material after it has been spun coated. For example, the filling material may be cured by UV or thermal curing.

The device coupon may include a first and second electrode. As such, the III-V semiconductor based photonic component can be tested and characterised before it is bonded to the silicon platform. Correspondingly, the yield of the method may be higher as malfunctioning or poorly fabricated device coupons are not used (and so silicon platforms are preserved).

A silicon waveguide may be in a device layer of a silicon-on-insulator wafer provided in the silicon platform, and the silicon waveguide may directly abut the cavity.

The silicon waveguide may include a waveguide tapering in height in a direction towards the cavity, from a first height to a second height, the first height being greater than the second height. Accordingly, the height of the silicon waveguide may decrease as it approaches the cavity. The resulting taper may function as a mode converter, between an optical mode within the III-V semiconductor based photonic component and an output waveguide of the resulting optoelectronic device.

The silicon waveguide may include a T-bar end portion, positioned adjacent to the cavity.

The III-V semiconductor based photonic component may include a U-shaped waveguide, and the silicon platform may include two silicon waveguides, each coupled to a respective leg of the III-V semiconductor based U-shaped waveguide. As such, the input and output waveguides of the optoelectronic device may be provided on a same side of the device.

The method may include a step, before filling the channel, of lining one or more sidewalls of the cavity with an anti-reflective liner.

The method may include a step, before transfer printing the device coupon, of providing an anti-reflective coating around one or more lateral side of the device coupon. The anti-reflective coating can serve to protect the lateral sides of the device coupon during the transfer printing process.

The method may include a step, after filling the channel, of covering the channel with a cladding layer. This isolates the filling material from moisture, which makes the resulting device more reliable. The cladding layer is, in some embodiments, silicon dioxide.

The method may include a step, after transfer printing the device coupon into the cavity, of providing electrode contact pads on the silicon platform, and electrically connecting them to the III-V semiconductor based photonic component. The resulting device has a reduction in parasitic capacitance, and so may operate faster.

The method may include a step, before transfer printing the device coupon, of providing an adhesive layer which forms the bonding surface of the cavity.

The method may include a step, after transfer printing the device coupon, of annealing the device coupon and silicon-on-insulator wafer.

The III-V semiconductor based photonic component may include a III-V semiconductor based waveguide including a 1-bar end portion which, when printed into the cavity, may be positioned adjacent to the channel.

The filling material may be a polymer. For example, the filling material may be Benzocyclobutene. In other embodiments the filling material is a sol-gel.

In a second aspect, embodiments of the present invention provide an optoelectronic device, including: a silicon waveguide, provided in a device layer of a silicon-on-insulator wafer; a III-V semiconductor based photonic component, located within a cavity of the silicon-on-insulator wafer; and a bridge, which optically couples the silicon waveguide to the III-V semiconductor based photonic component; wherein the bridge is at least partially formed of a polymer.

Such an optoelectronic device has been found to have decreased optical loss between the silicon waveguide and the III-V semiconductor based photonic component.

The optoelectronic device may have any one or, to the extent that they are compatible, any combination of the following optional features.

The bridge may also include one or more anti-reflective coatings. The bridge may include a pair of anti-reflective coatings, located on opposing sides of the polymer. One of the pair of anti-reflective coatings is formed of a layer of silicon nitride located between a pair of silicon dioxide layers.

The bridge may be covered by a passivation layer. This isolates the bridge from moisture, which makes the resulting device more reliable. The passivation layer is, in some embodiments, silicon dioxide.

The polymer may be Benzocyclobutene. The polymer may be sol-gel.

In a third aspect, embodiments of the present invention provide a method of manufacturing a device coupon, suitable for use in a transfer printing process, having the steps of growing a multi-layered stack on a substrate, comprising one or more III-V semiconductor based optically active layers; fabricating one or more III-V semiconductor based photonic components from the multi-layered stack; and coating one or more lateral sides of the III-V semiconductor based photonic component(s) with an anti-reflective coating.

Advantageously, the anti-reflective coating serves: (i) reduce the optical losses when the device coupon is printed to a platform; (ii) protect the III-V semiconductor based photonic component during the printing process; (iii) enhance device long term reliability.

The method may further comprise a step of: coating one or more lateral sides of the III-V semiconductor based photonic component with an anti-reflective coating.

The method may further comprise a step of providing a first electrode and a second electrode which electrically connect to respective layers of the multi-layered stack. Advantageously, this allows the III-V semiconductor based components to be tested and characterised before they are printed on a platform.

The method may include depositing one or more tethers onto the III-V semiconductor based photonic component, and removing a sacrificial layer of the component between the III-V semiconductor based photonic component and a substrate.

In a fourth aspect, embodiments of the present invention provide a device coupon, for use in a transfer printing process, comprising: a one or more III-V semiconductor based photonic component; and an anti-reflective coating, located on one or more lateral sides of the III-V semiconductor based photonic component.

The device may further comprise a first electrode and a second electrode, electrically connected to the III-V semiconductor based photonic component. Advantageously, this allows the III-V semiconductor based components to be tested and characterised before they are printed on a platform. The III-V semiconductor based photonic component may include a III-V semiconductor based waveguide.

In a fifth aspect, embodiments of the present invention provide an optoelectronic device manufactured using the method of the first aspect and including any one, or any combination insofar as they are compatible, of the optional features set out with reference thereto.

In a sixth aspect, embodiments of the present invention provide a device coupon manufactured using the method of the third aspect of the invention and including any one, or any combination insofar as they are compatible, of the optional features set out with reference thereto.

Further aspects of the present invention provide: a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first and third aspects; a computer readable medium storing a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first and third aspects; and a computer system programmed to perform the method of the first and third aspects.

Brief Description of the Drawings

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1A and 1B show, respectively, a top-down and section view of an optoelectronic device according to an embodiment of the present invention; Figure 2A and 2B show, respectively, a top-down and section view of a variant optoelectronic device according to an embodiment of the present invention; Figure 3A -3E show, respectively, a top-down view and sections view of a III-V waveguide and SOI waveguide interface according to embodiments of the present invention; Figure 4A and 4B show schematic views of variant interfaces; Figures 5 show further detail of a bridge and coupling structure; Figure 6 is a plot of coupling loss (dB) against wavelength (nm) for a simulated bridge and coupling structure; Figures 7(i) to 7(vi) show various manufacturing stages of a device coupon according to an embodiment of the present invention; Figures 80) to 8(v) show various manufacturing stages of a variant device coupon according to an embodiment of the present invention; Figures 9(i) to 9(v) show various manufacturing stages of a silicon platform according to an embodiment of the present invention; Figures 100) to 10(viii) show various manufacturing stages of an optoelectronic device according to an embodiment of the present invention; Figures 11(i) to 11(v) show various variant manufacturing stage of an optoelectronic device according to an embodiment of the present invention; Figure 12 shows a section view of two optoelectronic devices on a single silicon platform according an embodiment of the present invention; and Figure 13 shows a section view of three optoelectronic devices on a single silicon platform according to an embodiment of the present invention.

Detailed Description and Further Optional Features

Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

Figure 1A and 1B show, respectively, a top-down and section view of an optoelectronic device according to an embodiment of the present invention. As can be seen in Figure 1A, the optoelectronic device 100 broadly comprises a silicon platform 101, containing silicon waveguides 103a and 103b. The silicon waveguides function as input and output waveguides to the device. Each silicon waveguide is coupled at respective interfaces 104 to a III-V semiconductor based waveguide 102 which is within III-V device coupon 106. The coupon having been bonded to the silicon platform. The III-V semiconductor based waveguide 102 is, in this example, U-shaped and so allows for connection to the silicon waveguides 103a and 103b on a same side of the device coupon 106.

The device coupon 106 also includes a first 105a and second 105b electrical contact pads or electrodes. The electrical contact pads connect to different layers of a III-V semiconductor based device 110 in the III-V semiconductor based waveguide and, in use, are connected to a driver which operates the device. This operation may be performed at RF frequencies.

Figure 1B is a section view of the device 100 along the line A-B-C shown inn Figure 1A. The section view shows the III-V semiconductor based device 110 in more detail, and also shows the cladding layer 114 omitted from Figure 1A for reasons of clarity. The cladding layer is, in this example, formed of silicon dioxide (Si02). The cross-sectional structure of the silicon platform 101 is shown in more detail: a silicon substrate 117 is partially covered by a buried oxide layer 116, atop which are the silicon waveguides 103a and 103b.

The plurality of layers forming the III-V semiconductor based device 110 can also be seen, the detail of which are discussed in detail with relation to Figure 70). The nature of interface 104 is also shown in more detail, and comprises: anti-reflective coating 111 and 306 and bridge fill 112. The anti-reflective coatings are provided on the device coupon 106, as well as the silicon platform 101. The space between the anti-reflective coatings is filled by bridge fill 112 which is formed of a polymer. More detail relating to the interface 104 is shown in and discussed with relation to Figures 3B, 4A, 4B, and 5 respectively.

The anti-reflective coating 111 on the silicon platform 101 enhances the coupling from the III-V semiconductor based waveguide 102 into a 1800 nm section 113 of the silicon waveguide 103a. This 1800 nm section tapers to a 3000 nm section 115 for transmission to or from the device 100. In an example then where silicon waveguide 103a is the input waveguide, an optical signal is received into the 3000 nm section 115, and is converted to a mode confined within the 1800 nm section 113 before transmission into the III-V semiconductor based waveguide 104.

As can be seen in Figure 1B, a gap exists between the silicon platform and the device coupon which has been filled by bridge fill 112, in this example Benzocyclobutene (BCB).

The thickness of the gap varies as a function of position along the perimeter of the device coupon 106. At positions distal to the interfaces 104, the gap can be as wide as 20 pm as shown in Figure 1B. Whereas, at positions proximal to and including the interfaces 104, the gap may be as narrow as (or narrower than) 1 pm. In this example, a height, x, from the bottommost portion of the bridge fill 112 to a bottommost portion of the buried oxide layer is around 810 nm (the buried oxide layer having a height of around 400 nm). Where the buried oxide layer has a height of around 1 pm, the height x may be around 210 nm.

Figure 2A and 23 show, respectively, a top-down and section view of a variant optoelectronic device 200 according to an embodiment of the present invention. Where this embodiment shares features with the device 100 discussed above, like features are indicated by like reference numerals. The device 200 in Figures 2A and 2B chiefly differs from the earlier device in that contact pads 201a and 201b extend across the device coupon 206 to the silicon platform 202. This has the advantage that a smaller parasitic capacitance is experienced in use, and so the device speed is enhanced.

Figure 3A -3E show, respectively, a top-down view and sections view of a III-V waveguide and SOI waveguide interface according to embodiments of the present invention. VVhilst the example shown in Figure 3A, a top-down view, is device 100, the interface shown has the same structure when implemented in device 200. Figure 3B is a section view along the line A-A', Figure 30 is a section view along the line B-B', Figure 3D is a section view along the line C-C'; and Figure 3E is a section view along the line D-D'.

In Figure 38, light is guided along the 'x' direction either from the 1.8 pm silicon waveguide 113 into the III-V semiconductor waveguide 102 or vice versa. As can be seen, the gap between the III-V semiconductor waveguide 102 and the 1.8 pm silicon waveguide has the following structure, in layers along the 'x' direction: 20 nm silicon dioxide layer 302; 180 nm anti-reflective silicon nitride, Si3N14, layer 111; 100 nm silicon dioxide layer 304; BCB fill 305; and 180 nm anti-reflective silicon nitride, Si3N14, layer 306. The 20 nm silicon dioxide layer 302 has a refractive index of around 1.45. The silicon nitride layer 111 has a refractive index of around 1.995, and the 100 nm silicon dioxide layer 304 has a refractive index of around 1.45. The 180 nm Si3N4 layer 306 has a refractive index of around 2.28 and, in this embodiment, with a composition slightly different to layer Si3N4 layer 111. However, the refractive index of the SisN4 layers, 111 and 306, can be the same, either 1.995 or 2.28 with slight adjustment to their thickness. The entire gap has a width of around 1 pm. The entire anti-reflective coating, formed of layers 302, 111, 304, and 306 has a thickness of around 480 nm. The BOB fill has a refractive index of around 1.56. All of these refractive indexes are quoted for light at a wavelength of around 1310 nm.

The combination of these layers, in this fashion, have been found to enhance the coupling efficiency from the III-V semiconductor waveguide 102 to the 1.8 pm silicon waveguide 113.

Also shown in this view is silicon substrate portion 307, which extends part way up the cavity within which the device coupon sits. The height of this portion is around 810 nm. An optically active layer 301 of the III-V semiconductor based waveguide 102 can also be seen, in this example a multiple quantum well.

Figure 30 is a cross-section along the line B-B' in Figure 3A. The structure of the III-V semiconductor based waveguide 102 can be seen in greater detail. Broadly, the waveguide includes a waveguide slab or base 102b, and a ridge or rib 102 extending therefrom. Between the slab and rib, or forming a part of the rib, is the optically active layer 301. The slab, in this example, has a height of around 1.74 pm, whereas the rib has a height of around 3.956 pm. The rib has a width of around 2.5 pm.

Figure 3D is a cross-section along the line C-C' in Figure 3A. The structure of the 1.8 pm silicon waveguide 113 can be seen in greater detail. Broadly, the waveguide includes a slab or base, and a ridge or rib. The slab is around 200 nm tall, whereas the rib is around 1.8 pm tall and around 2.6 pm wide. Figure 3E is a cross-section along the line D-D' in Figure 3A. The structure of the 3pm silicon waveguide 115 can be seen in greater detail. Broadly, the waveguide includes a slab or base and a ridge or rib. The slab is around 1.8 pm tall, whereas the rib is around 3 pm tall and around 2.6 pm wide. Herein, the height of a feature is typically measured from an uppermost surface of the buried oxide layer 116 to an uppermost surface of that feature. The height of the rib and slab in the 1.8 pm waveguide 113 tapers to the height in the 3 pm waveguide, such that the tapered region functions as a mode converter between the 1.8 pm waveguide and 3 pm waveguide.

Figure 4A and 4B show schematic views top-down views of variant interfaces. In the example shown in Figure 4A, which is the interface implemented in Figures 1A and 2A, the interface between the III-V semiconductor based waveguide 102 and the silicon waveguides 103a/b is at an angle a relative to the guiding direction (A-B, or vice versa). The angle a typically takes a value of between 1° and 100 inclusive. Also shown in Figure 4A is the 'T' geometry of the interfaces. The 'bar' of the T in the III-V semiconductor waveguide, i.e. the portion which extends at the angle a, has a width of around 2 pm. The 'bar' of the T in the silicon waveguide, again the portion which extends at the angle a, has a width of around 1 pm. A gap between the respective T interfaces is around 1 pm.

Figure 4B is a top-down schematic of a variant interface, which may be used in place of the interface shown in Figure 4A. Whilst it is still 'T' shaped in geometry, in the example shown in Figure 4B there bars of the T are not angled relative to the guiding direction (A-B). Figure 5 show further detail of the interface and coupling structure. Figure 5 is a 3D perspective view of the interface between the III-V semiconductor based waveguide 102 and the silicon waveguides 103a/b.

Figure 6 is a plot of coupling loss (dB) against wavelength (nm) for a simulated bridge and coupling structure. Notably, the plot shows that the optical coupling loss over the 0-band (around 1260 nm to around 1360 nm) is between 1.22 and 1.32 dB.

Figures 7(i) to 7(vi) show various manufacturing stages of a device coupon according to an embodiment of the present invention. In the step shown in Figure 7(0, a III-V semiconductor based stack is provided. In the example shown, the stack comprises the following layers (from an uppermost layer to a lowermost layer): 701 -P-doped InGaAs layer; 702-P-doped InP layer; 301-Multiple quantum well layer; 703-N-doped InP layer; 704-Undoped InP layer; 705-Sacrificial layer; and 706-InP substrate layer.

In another example, the stack has the following layers: Layer Multiplier Material Composition Wavelength (nm) Thickness (nm) Doping (cm-3) 19 InGaAs Lattice match to InP 120+30 1x1019 CBr+Zn 18 InGaAsP 1100 50 1 5x 1013 Zn 17 InP - - 1340 1x1019Zn 16 InGaAsP 1100 20 1x1019Zn AllnAs 60 1x1017 to 1x10" Zn 14 AllnAs 843 60 1x1017Zn 13 AlInGaAs 968 70 12 12x AlInGaAs 1127 7 11 12x AlInGaAs 1245 9 AlInGaAs 1127 7 9 InGaAsP 1100 117 8 InP - - 80 2x 1017Si 7 InP 70 5x 10175i 6 InP - - 920 8x 1017Si InGaAsP Lattice Match to InP 1100 20 Undoped 4 InP 800 Undoped 3 InGaAs 50 Undoped 2 Release AllnAs 500 Undoped 1 Buffer InP 50 Undoped 0 InP Substrate

Table 1

Where layer 4 forms the bottom surface layer of the device coupon once separated from the InP substrate, and layers 3 and 2 are sacrificial layers used in the release of the coupon from the substrate.

These layers can be provided, for example, through molecular beam epitaxy or chemical vapour deposition. Once provided, through standard fabrication processes (e.g. etching, deposition, and masking) a III-V electro-absorption modulator (EAM) structure can be fabricated. The result of this is shown in Figure 7(U). The structure includes the III-V semiconductor based device 110 discussed previously. An upper layer of which is electrically connected to the first electrical contact pad 105a, and a lower layer of which (NInP layer) is electrically connected to the second electrical contact pad 105b.

Also of note, is that the anti-reflective coating (ARC) formed of the SiO2 layer 303, Si31\14 layer 111, and second Si02 layer 304 are formed as a part of the device coupon manufacture. The ARC also functions then as a facet protection coating for the sacrificial release layer etching process discussed below. The structure includes, as a fill e.g. between the III-V semiconductor based device 110 and peripheral components, a BCB fill 801. The use of BCB takes advantage of its relatively low dielectric constant, which can reduce parasitic capacitance and so provide a higher operating speed.

Next, in a step the results of which are shown in Figure 7(iii), a dry etching process is performed to remove the portions of the sacrificial layer 705 which have an exposed upper surface. That is, the portions of the sacrifice layer which extend laterally beyond the ARC are removed as shown in Figure 7(iii). This step 'releases' the multi-layered stack, in that it is ready for subsequent processing. An upper surface of the InP substrate is thereby exposed, as are lateral sides of the sacrifice layer 705. Subsequently, in a step shown in Figure 7(iv), a photoresist tether (PR) 707 is applied to the outside of the device coupon, covering the ARC and upper surfaces. Notably, the lateral sides of the sacrificial layer 705 remain exposed.

After this, in a step show in Figure 7(v), a wet etch process is started to begin removing the sacrificial layer 705. The etch proceeds in the direction shown, i.e. laterally towards the centre of the coupon from the periphery thereof When the wet etch process is completed, a structure shown in Figure 7(vi) results. The coupon 106 is suspended by the photoresist 707 above the InP substrate 704, with the lowermost surface of the undoped InP layer 704 facing the uppermost surface of the substrate. The device coupon is then ready for transfer printing.

Figures 80) to 8(v) show various manufacturing stages of a variant device coupon according to an embodiment of the present invention. The method shown in Figures 8(i) to 8(v) starts after the step shown in Figure 70); that is the provision of a multi-layered epitaxial stack formed of III-V semiconductor layers. In a step the results of which are shown in Figure 8(i), standard fabrication processes (e.g. etching, deposition, and masking) a variant III-V electroabsorption modulator (EAM) structure can be provided. The structure in Figure 8(i) differs from that in Figure 700 in that electrode traces 805a and 805b are provided which will electrically connect to contact pads which extend at least partially onto the silicon platform (as discussed previously in relation to Figures 2A and 2B).

After the step shown in Figure 80), a dry etch process is performed to remove the portions of the sacrificial layer 705 which have an exposed upper surface. The result of this is shown in Figure 8(ui). An upper surface of the InP substrate 706 is thereby exposed, as are lateral sides of the sacrificial layer 705. Subsequently, in a step shown in Figure 8(iii), a photoresist tether 707 is applied to the outside of the device coupon, covering the ARC and upper surfaces. Notably, the lateral sides of the sacrificial layer 705 remain exposed.

After this step, in a step shown in Figure 8(iv), a wet etch process is started to begin removing the sacrificial layer 705. The etch proceeds in the direction shown, i.e. laterally towards the centre of the coupon from the periphery thereof. When the wet etch process is completed, a structure shown in Figure 8(v) results. The coupon 206 is suspended by the photoresist 707 above the InP substrate 704, with the lowermost surface of the undoped InP layer 704 facing the uppermost surface of the substrate. The device coupon is then ready for transfer printing.

Figures 9(i) to 9(v) show various manufacturing stages of a silicon platform according to an embodiment of the present invention. In a first step, shown in Figure 9(i), a silicon-oninsulator wafer is provided. A silicon device layer 901, which is around 3000 nm or 3 pm tall, is above a 400 nm buried oxide (e.g. Si02) layer 116. The buried oxide layer is above the silicon substrate 117.

Next, in a step the results of which are shown in Figure 9(h), a first cavity 902 is etched into the silicon device layer. A part of this step includes the deposition of cladding layer 114 (formed here of silicon dioxide). The first cavity is etched so that a 1800 nm portion of the silicon device layer remains above the buried oxide layer. This etch also provides the 3 pm to 1800 pm waveguide taper discussed previously, which functions as a mode converter for light passing through the taper.

After the taper has been provided, a second etch is performed to form second cavity 903. This second cavity extends through the buried oxide layer and partially into the silicon substrate. The exact depth of the etch is chosen such that an optical mode supported by the 1800 nm silicon waveguide 113 is generally aligned with an optical mode supported by the III-V semiconductor based waveguide 102 (when present in the cavity 903). The surface roughness (e.g. R., Rz, or RmAx) of the bed of the second cavity is preferably at a sub nanometre level, as measured using an atomic force microscope. The measured area is typically around 10 pm by 10 pm.

Next, in a step shown in Figure 90v) the 180 nm Si3N4 anti-reflective coating is provided on one or more sidewalls of the cavity 903. The silicon platform is then ready for micro-transfer printing. Figure 9(v) shows an optional further step, where an adhesive layer 904 (such as BCB) is spun-coated onto the silicon platform. The adhesive layer is between 30 nm and 100 nm thick Figures 100) to 10(viii) show various manufacturing stages of an optoelectronic device according to an embodiment of the present invention. In a first step, shown in Figure 100) a stamp (in some examples an elastomer stamp) is used to pick up the device coupon 106 by attaching to the photoresist tether 707. In a first movement, indicated by the left-hand arrow in Figure 100), the stamp and device coupon 106 are lifted up and away from the InP substrate 706 which breaks the tethers. Subsequently, the stamp and device coupon are moved laterally towards the silicon platform.

Next, in a step shown in Figure 10(ui), the device coupon 106 is deposited into the second cavity 903 formed in the silicon platform earlier. This deposition step includes aligning the III-V semiconductor based waveguide 102 within the device coupon 106 with the 1800 nm silicon waveguide. Once deposited, a lowermost surface of the undoped InP layer 704 directly abuts an upper surface of the silicon substrate layer 117 (asides from examples where an adhesive 904 is used, in which case the adhesive will sit between the undoped InP layer and the silicon substrate).

Subsequently, in a step shown in Figure 10(iii) the stamp is released and the device coupon 106 is left within the cavity 903. Once the stamp has been released, the photoresist 707 is then removed using a dry etching process. The combination of device coupon 106 and silicon platform is then annealed at a temperature of between 280°C and 300°C inclusive for at least 1 and no more than 15 hours. The result of this processing is shown in Figure 100v).

Also of note, in Figure 10(iv) is channel 906 which surround a periphery of the device coupon 106 between the device coupon and the sidewalls of the cavity 903. The channel 906 thereby defines a boundary around the device coupon 106.

After the annealing step, the combination of device coupon 106 and silicon platform is then spun coated with a polymer 907 (in this example Benzocyclobutene) and thermally cured at around 280°C for around 60 minutes in a nitrogen atmosphere (N2). The result of this spin coating step is shown in Figure 10(v). Notably the spun coated BOB 907 fills the channel 906 and provides the bridge fill 305 discussed previously.

After the thermal curing process has completed, the polymer 907 is etched back in a dry etch step (using, for example, 02 CF4, or SF6 gas) such that the upper surface of contact pads 105a and 105b are exposed, as well as cladding layer 114. The result of this is shown in Figure 10(vi). Subsequently, further cladding layer 114 is added as shown in Figure 10(vii) to isolate the bridge fill 305 from moisture. This cladding layer, in some examples formed from Si02, has a thickness of around 500 nm. Finally, in a step shown in Figure 10(viii), vias are opened in the cladding layer above the contact pads 105a and 105b for wire bonding.

Figures 11(i) to 11(v) show various variant manufacturing stage of an optoelectronic device according to an embodiment of the present invention. The steps shown in Figures 100) to 10(v) are repeated using the device coupon 206 discussed with relation to Figures 80) to 8(v). The result, as shown in Figure 110) is a device coupon 206 which has been bonded to the silicon substrate of the silicon platform. The spun coated polymer 907 again fills the channels 906, and the device has been thermally cured at around 280°C for around 60 minutes in a nitrogen atmosphere (N2).

Next, as shown in Figure 1100 an etching and/or planarization process is performed so that the upper surface of wire traces 805b and 805a are exposed. After this further cladding material is deposited to provide a 500 nm thick Si02 cladding layer 114, as shown in Figure 11(iii). After this deposition, vias are opened in the cladding layer 114 above the traces 805a and 805b. The result of this is shown in Figure 11(iv). This allows for a metallization process to provide contact pads 201a and 201b, which extend at least partially over the silicon platform. The device is then ready for wire bonding and operation.

Figure 12 shows a section view of two optoelectronic devices on a single silicon platform according an embodiment of the present invention. In this example, three cavities are formed: a first cavity at least partially defining a 1800 nm silicon waveguide; a second cavity within which a III-V semiconductor based electro-absorption modulator 1201 has been printed; and a third cavity adjacent to a 3000 nm silicon waveguide 115 within which a III-V semiconductor based laser 1202 has been deposited. The III-V semiconductor based electro-absorption modulator 1201 is optically coupled to a first and second 1800 nm silicon waveguide 113. In use, laser 1202 produces an optical signal which is coupled into the 3000 nm silicon waveguide 115, a taper in or between the 3000 nm and 1800 nm silicon waveguides coverts the optical mode to one which is couplable into the EAM 1201. The EAM 1201 imparts a modulation profile to the signal, which is then coupled into 1800 nm silicon waveguide 113 for further transmission.

Figure 13 shows a section view of three optoelectronic devices on a single silicon platform according to an embodiment of the present invention. The arrangement in Figure 13 differs from that in Figure 12 in that it further includes a semiconductor optical amplifier, SOA, 1203, which is located in a fourth cavity. The SOA is configured to receive signals from the EAM, via 1800 nm silicon waveguide 113, and amplify them before coupling them into output waveguide 1301.

While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

List of Features 101, 202 Silicon platform 1201 EAM 102 III-V semiconductor based waveguide 1202 Laser 103a/b Silicon waveguide 1203 SOA 104 Waveguide interface 1301 Output waveguide 105a/b Contact pads 106, 206 III-V device coupon III-V semiconductor based photonic component 111 Anti-reflective coating 112 Bridge fill 113 1800 nm silicon waveguide portion 114 Cladding layer 3000 nm silicon waveguide portion 116 Buried oxide layer 117 Silicon substrate 201a/b Contact pads 301 Multiple quantum well (QM) layer 302 First silicon dioxide liner 304 Second silicon dioxide liner 305 BCB bridge fill 306 Second silicon nitride liner 307 Silicon substrate portion 102a III-V waveguide ridge 102b III-V waveguide slab 701 -706 III-V semiconductor layers 707 Photoresist tether 801 BCB fill 805a/b Electrode trace 901 Silicon on insulator / device layer 902 First cavity 903 Bonding cavity 904 Adhesive 905 Stamp (elastomer) 907 Spun coated BCB The following numbered paragraphs (paras.) contain further statements of various aspects of the present invention 1. A method of manufacturing an optoelectronic device, the manufactured device including a III-V semiconductor based photonic component coupled to a silicon waveguide, the method comprising: providing a device coupon, the device coupon including the III-V semiconductor based photonic component; providing a silicon platform, the silicon platform comprising a cavity within which is a bonding surface for the device coupon; transfer printing the device coupon onto the cavity, such that a surface of the device coupon directly abuts the bonding surface and at least one channel is present between the device coupon and a sidewall of the cavity; and filling the at least one channel with a filling material via a spin-coating process, to form a bridge coupling the III-V semiconductor based photonic component to the silicon waveguide.

2. The method of para 1, further comprising a step of curing the filling material after it has been spun-coated.

3. The method of para 1 or 2, wherein the device coupon includes a first and second electrode.

4. The method of any preceding para, wherein a silicon waveguide is in a device layer of a silicon-on-insulator wafer provided in the silicon platform, the silicon waveguide directly abutting the cavity.

5. The method of para 4, wherein the silicon waveguide includes a waveguide tapering in height in a direction towards the cavity, from a first height to a second height, the first height being greater than the second height.

6. The method of either para 4 or claim 5, wherein the silicon waveguide includes a T-bar end portion, positioned adjacent to the cavity.

7. The method of any preceding para, wherein the III-V semiconductor based photonic component includes a U-shaped waveguide, and the silicon platform includes two silicon waveguides, each coupled to a respective leg of the III-V semiconductor based U-shaped waveguide.

8. The method of any preceding para, further including a step, before filling the channel, of lining one or more sidewalls of the cavity with an anti-reflective liner.

9. The method of any preceding para, further including a step, before transfer printing the device coupon, of providing an anti-reflective coating around one or more lateral side of the device coupon.

10. The method of any preceding para, further including a step, after filling the channel, of covering the channel with a cladding layer.

11. The method of any preceding para, further including a step, after transfer printing the device coupon onto the cavity, of providing electrode contact pads on the silicon platform, and electrically connected them to the III-V semiconductor based photonic component.

12. The method of any preceding para, further including a step, before transfer printing the device coupon, of providing an adhesive layer which forms the bonding surface of the cavity.

13. The method of any preceding para, further including a step, after transfer printing the device coupon, of annealing the device coupon and silicon-on-insulator wafer 14. The method of any preceding para, wherein the III-V semiconductor based photonic component includes a III-V semiconductor based waveguide including a T-bar end portion which, when printed into the cavity, is positioned adjacent to the channel.

15. The method of any preceding para, wherein the filling material is a polymer.

16. The method of any preceding para, wherein the filling material is Benzocyclobutene.

17. The method of any of paras 1 -14, wherein the filling material is sol-gel.

18. An optoelectronic device, including: a silicon waveguide, provided in a device layer of a silicon-on-insulator wafer; a III-V semiconductor based photonic component, located within a cavity of the silicon-on-insulator wafer; and a bridge, which optically couples the silicon waveguide to the III-V semiconductor based photonic component; wherein the bridge is at least partially formed of a polymer.

19. The optoelectronic device of para 18, wherein the bridge also included one or more anti-reflective coatings.

20. The optoelectronic device of para 19, wherein the bridge includes a pair of anti-reflective coatings, located on opposing sides of the polymer.

21. The optoelectronic device of para 20, wherein one of the pair of anti-reflective coatings is formed of a layer of silicon nitride located between a pair of silicon dioxide layers.

22. A method of manufacturing a device coupon, suitable for use in a transfer printing process, having the steps of: growing a multi-layered stack on a substrate, comprising one or more III-V semiconductor based optically active layers; fabricating one or more III-V semiconductor based photonic components from the multi-layered stack; and coating one or more lateral sides of the III-V semiconductor based photonic component(s) with an anti-reflective coating.

23. The method of para 22, further comprising a step of providing a first electrode and a second electrode which electrically connect to respective layers of a multi-layered stack.

24. A device coupon, for use in a transfer printing process, comprising: a one or more III-V semiconductor based photonic component; and an anti-reflective coating, located on one or more lateral sides of the III-V semiconductor based photonic component.

25. The device coupon of para 24, further comprising a first electrode and a second electrode, electrically connected to the III-V semiconductor based photonic component.

Claims

CLAIMS1. A method of manufacturing a device coupon, suitable for use in a transfer printing process, having the steps of: growing a multi-layered stack on a substrate, comprising one or more III-V semiconductor based optically active layers; fabricating one or more III-V semiconductor based photonic components from the multi-layered stack; and coating one or more lateral sides of the III-V semiconductor based photonic component(s) with an anti-reflective coating.
2. The method of claim 1, further comprising a step of providing a first electrode and a second electrode which electrically connect to respective layers of a multi-layered stack.
3. A device coupon, for use in a transfer printing process, comprising: a one or more III-V semiconductor based photonic component; and an anti-reflective coating, located on one or more lateral sides of the III-V semiconductor based photonic component.
4. The device coupon of claim 3, further comprising a first electrode and a second electrode, electrically connected to the III-V semiconductor based photonic component.