GB2580631A

GB2580631A - Phase-locked loop circuitry

Info

Publication number: GB2580631A
Application number: GB1900683.2A
Authority: GB
Inventors: Li Kim
Original assignee: Cml Microcircuits Uk Ltd
Current assignee: Cml Microcircuits Uk Ltd
Priority date: 2019-01-17
Filing date: 2019-01-17
Publication date: 2020-07-29
Anticipated expiration: 2039-01-17
Also published as: GB201900683D0; GB2580631B; WO2020148517A1

Abstract

Phase-locked loop circuitry 200 comprises a first phase detector 202 that generates a control signal CPD by comparing the phases of an input signal FREF and a first, undivided feedback signal FVCO from the VCO 204. The circuit also comprises a second phase/frequency detector 206 that generates a control signal CPFD by comparing the frequencies of the input signal FREF and a second, divided feedback signal FDIV. The VCO 204 generates an oscillator signal FVCO in response to a combined control signal CCOM derived from control signals CPD and CPFD. In a first mode of operation, frequency converter 210 generates the divided feedback signal FDIV from the oscillator signal FVCO and locks the VCO via phase/frequency detector 206. In a second mode of operation (fig.3), frequency converter 210 generates an output signal FOUT , via switch 212, from the locked oscillator signal FVCO. In the second mode, the VCO remains locked via phase detector 202. The output frequency FOUT is thus defined by the oscillator frequency as locked by a first divider value in the first phase, and by a second divider value applied in the second phase. The circuit provides faster settling, lower phase noise and lower power consumption.

Description

PHASE-LOCKED LOOP CIRCUITRY

The present invention relates to phase-locked loop circuitry, to an apparatus comprising phase-locked loop circuitry, and to a method of operating phase-locked loop circuitry.

A phase-locked loop (PLL) can be used to generate a periodic output signal having a phase that is related or "locked" to the phase of a periodic input signal. In its simplest form, a PLL may comprise a comparator that receives an input signal, a loop filter that can be used to set the response dynamics of the PLL, and a voltage-controlled oscillator that generates an output signal. The comparator compares the phases of the input signal and a feedback signal derived from the output signal, and generates a control signal based on the phase comparison. The loop filter filters the control signal and the filtered control signal is passed to the voltage-controlled oscillator to control the instantaneous oscillation frequency of the output signal. The PLL is arranged such that a difference in phase between the input signal and feedback signal causes a control signal to be generated that acts to bring the output signal back into phase with the input signal.

In many PLL applications, it is desirable for the output signal frequency to be a multiple of the input signal frequency. A typical arrangement for achieving this is shown in Figure 1. In this arrangement, the PLL circuitry 100 comprises a phase-frequency comparator (PFD) 102 that receives a periodic input signal having a reference frequency FREF, a low-pass loop filter (LPF) 104, and a voltage-controlled oscillator (VCO) 106 that generates a periodic output signal having a frequency Four In this arrangement, the output signal is fed back to the -2 -PFD 102 through a frequency converter in the form of a divider 108 that divides the output signal frequency Four by a programmable integer P, and thus generates a feedback signal having a frequency F^iv that is a fraction 1/P of the output signal frequency Four, such that Four = F^iv x P. In this arrangement, the PFD 102 compares the phases and frequencies of the input signal and feedback signal and generates a control signal CPF^ based on the comparison. The LPF 104 receives the control signal CPF^ and generates a filtered version of that control signal. The filtered control signal is then passed to the VCO 106 to control the output signal frequency Four. The PLL circuitry 100 is arranged such that a detected difference in the phases and/or frequencies of the input signal and feedback signal at the PFD 102 causes a control signal CPF^ to be generated that acts to bring the feedback signal back into phase with the input signal at the same frequency as the input signal. In this arrangement, since the feedback signal frequency F^iv is caused to be the same as the input signal frequency FREF, and since Four = F^iv x P, it follows that Four is caused to be equal to FREF x P. Thus, the output signal frequency FOUT can be made to be a programmable integer multiple P of the input signal frequency FREE.

Programmable synthesis of one or more output frequencies from an input reference frequency can be particularly, although not exclusively, useful in many data communication (e.g. radio) applications, in which it is often desirable to select one of plural possible signal frequencies for transmission and/or reception of data. -3 -

It is desired to provide improved phase-locked loop circuitry, improved apparatus comprising phase-locked loop circuitry, and improved methods of operating phase-locked loop circuitry.

According to an aspect of the present invention, there is provided phase-s locked loop circuitry, the circuitry comprising: a first comparator configured to receive an input signal and a first feedback signal, wherein the first comparator is configured to generate a first control signal based on a comparison of the phases of the input signal and the first feedback signal; a second comparator configured to receive the input signal and a second feedback signal, wherein the second comparator is configured to generate a second control signal based on a comparison of the frequencies of the input signal and the second feedback signal; a controllable oscillator configured to receive a combined control signal derived from the first control signal and the second control signal, wherein the controllable oscillator is configured to generate an oscillator signal in response to the combined control signal, and wherein the controllable oscillator is configured to provide the oscillator signal to the first comparator as the first feedback signal; a frequency converter configured to receive the oscillator signal, wherein 20 the frequency converter is configurable to generate the second feedback signal from the oscillator signal in a first mode of operation, and wherein the frequency converter is configurable to generate an output signal from the oscillator signal in a second mode of operation; and -4 -a controller configured to reconfigure the circuitry between operating in the first mode of operation in which the second feedback signal is generated and provided to the second comparator to set the frequency of the oscillator signal and operating in a second mode of operation in which the output signal is generated and provided to an output.

In embodiments, providing the oscillator signal to the first comparator as the first feedback signal can lead to relatively faster settling times and relatively lower phase noise than conventional PLL arrangements. This is because the first feedback signal need not be passed through a frequency converter in the feedback path between the controllable oscillator and the first comparator. This also allows the input signal frequency to be relatively higher than conventional PLL arrangements. Furthermore, generating and providing the second feedback signal to the second comparator can still allow the oscillator signal frequency to be set to a multiple of the input signal frequency. The controller can also allow a first (relatively higher power) mode of operation to be implemented in which the second feedback signal is generated and provided to the second comparator to assist with setting the oscillator signal frequency, and then allow a second (relatively lower power) mode of operation to be implemented in which the first feedback signal maintains the phase lock between the input signal and oscillator signal, and in which the oscillator signal and frequency converter are used to generate the output signal, i.e. without needing to generate and provide the second feedback signal to the second comparator to maintain the oscillator signal frequency. In this regard, it has been identified that, even though the second feedback signal is not being generated and provided to the second comparator -5 -in the second mode of operation, the phase of the oscillator signal can still remain locked to the phase of the input signal by virtue of the first comparator, and thus the oscillator signal frequency can remain at the frequency set in the first mode of operation. Furthermore, passing the oscillator signal through the frequency converter in both the first mode of operation and the second mode of operation can reduce the complexity of the circuitry and provide a greater degree of flexibility over the output signal frequencies that can be generated.

It will accordingly be appreciated that embodiments of the present invention can provide faster settling times, lower levels of phase noise, lower levels of power consumption, and greater flexibility for frequency synthesis when compared with conventional PLL arrangements. It has also been found that embodiments of the present invention can be used to provide a wide variety of synthesised frequencies with a reduced occurrence of unwanted FM sidebands or "spurs". These benefits are particularly, although not exclusively, desirable in data communication (e.g. radio) applications, which often rely on accurate, rapid and efficient transmission and/or reception of data over a number of frequency bands.

In embodiments, the input signal may have a frequency in the range 1 MHz to 120 MHz, such as in the range 10 MHz to 40 MHz. The input signal may be provided by a reference oscillator, such as a crystal oscillator. The output signal may have a frequency in the range 1 MHz to 1 GHz, such as in the range 5 MHz to 120 MHz.

In embodiments, the first comparator may comprise a phase comparator (phase detector or "PD"). The first comparator may comprise a sampling -6 -comparator. In this regard, it is possible for conventional PLLs to be made to have lower noise by decreasing the PLL bandwidth. However, this can lead to slower settling times. In contrast to this, in embodiments in which the first comparator comprises a sampling comparator, the feedback loop comprising the first comparator can have both lower noise and a larger bandwidth which settles much faster than conventional PLLs. The first comparator may comprise a differential sampling comparator.

The first comparator may further comprise a first charge pump ("CP"). The first charge pump may comprise a first switched current source. The first comparator may be configured to control the first charge pump to provide a first control current as the first control signal when the input signal and first feedback signal are out of phase with each other. The first comparator may be configured to control the first charge pump to provide substantially zero current as the first control signal when the input signal and first feedback signal are substantially in phase with each other.

In embodiments, the second comparator may comprise a frequency (and e.g. phase) comparator (phase frequency detector or "PFD"). The second comparator may be configured to generate the second control signal based on a comparison of the frequencies and phases of the input signal and the second feedback signal. In embodiments, since the second comparator is only needed to assist with setting the oscillator signal frequency in the first mode of operation, and is not needed in the second mode of operation, and thus does not need to be particularly low noise, the feedback loop comprising the second comparator can also have a larger bandwidth for faster settling times. -7 -

The second comparator may further comprise a second charge pump ("CP"). The second charge pump may comprise a second switched current source. The second comparator may be configured to control the second charge pump to provide a second control current as the second control signal when the input signal and second feedback signal have different frequencies (and/or phases) to each other. The second comparator may be configured to control the second charge pump to provide substantially zero current as the second control signal when the input signal and second feedback signal have substantially the same frequencies (and e.g. phases) as each other.

In embodiments, the first control signal and second control signal may be combined at an electrical connection or junction. For example, the first control current and second control current may be summed at the electrical connection or junction.

In embodiments, the circuitry may further comprise a loop filter configured to receive the combined control signal and output a filtered version of the combined control signal to the controllable oscillator. The loop filter may comprise a low pass filter. Thus, the loop filter may attenuate frequencies in the combined control signal which are above a selected cut-off frequency. The loop filter may comprise appropriate capacitors and/or resistors to set the filtering characteristics of the loop filter. The loop filter may convert the combined control signal from a current control signal to a voltage control signal.

In embodiments, the controllable oscillator may comprise a voltage-controlled oscillator. The controllable oscillator may be configured to generate an -8 -oscillator signal having an instantaneous oscillation frequency that is based on an applied voltage due to the (e.g. filtered) combined control signal.

In embodiments, the frequency converter may comprise a frequency divider and/or frequency multiplier. In the first mode of operation, the frequency converter may be operated as a frequency divider. In the second mode of operation, the frequency converter may be operated as a frequency divider or as a frequency multiplier. The frequency converter may be programmable, e.g. in use. The frequency converter may be reprogrammable, e.g. in use. The frequency converter may comprise a digital frequency converter. The frequency converter may comprise one or more flip-flops arranged in series. The frequency converter may comprise (e.g. programmable/reprogrammable) control logic for controlling (e.g. reconfiguring) the operation of the frequency converter, e.g. on the basis of one or more control values provided to the frequency converter. Alternatively, the frequency converter may comprise an analogue frequency converter. In embodiments, the frequency converter may be configured to generate the second feedback signal from the oscillator signal in the first mode of operation but not in the second mode of operation. Similarly, the frequency converter may be configured to generate the output signal from the oscillator signal in the second mode of operation but not in the first mode of operation.

In embodiments, the relationship (e.g. ratio) between the frequencies of the oscillator signal and the second feedback signal may be determined by a first control value that controls the frequency converter in the first mode of operation. The first control value may be an (e.g. positive and/or non-zero) integer value. The first control value may be provided to the frequency converter prior to -9 -powering or when resetting the circuitry. The first control value may be a programmable or reprogrammable control value. Alternatively, the first control value may be a non-programmable or non-reprogrammable control value. The first control value may be in the range 1 to 1200, such as in the range 4 to 127.

As will be appreciated from the above, in the first mode of operation, if the frequency converter divides the oscillator signal frequency Fvco by a first value PDIVLOCK, such that the second feedback signal frequency FDIv equals Fvco / PDIVLOCK, and if the second feedback signal frequency FDIV is caused to equal FREF, such that Fvco / PoivLocK is also caused to equal FREF, then Fvco is locked at FREF x PDIVLOCK. In this way, the oscillator signal frequency can be set to be an (e.g. integer) multiple of the input signal frequency. In most cases, the first control value PDIVLOCK DIVLOCK is not equal to one, and thus the oscillator signal frequency Fvco may not be caused to be equal to the input signal frequency FREF. However, in other cases, the first control value PDIVLOCK may be equal to one, and thus the oscillator signal frequency Fvco may be caused to be equal to the input signal frequency FREF.

In embodiments, the relationship (e.g. ratio) between the frequencies of the oscillator signal and the output signal may be determined by a second control value that controls the frequency converter in the second mode of operation. The second control value may be an (e.g. positive and/or non-zero) integer value. The second control value may be provided to the frequency converter prior to powering or when resetting the circuitry. The second control value may be a programmable or reprogram mable control value. Alternatively, the second control value may be a non-programmable or non-reprogrammable control value. The -to -second control value may be in the range 1 to 1200, such as in the range 4 to 127.

As will be appreciated from the above, in the second mode of operation, if the oscillator signal frequency Fvco was locked at FREF x PoivLocK in the first mode of operation, and if the frequency converter now divides the oscillator signal frequency Fvco by a second value Pow, then the output signal frequency Four will equal FREF x PDIVLOCK / PDIV. The relationship (e.g. ratio) between the input signal frequency FREE and the output signal frequency FOUT may therefore be determined by the first control value and the second control value that are /o provided to the frequency converter. In this way, depending on the selected control values, the output signal frequency Four can be set to be an (e.g. integer or non-integer) multiple or fraction of the input signal frequency FREF. Furthermore, careful selection of the first control value and the second control value can avoid boundary spurs that may occur at some output frequencies. In most cases, the second control value PoivLocK is not equal to the first control value Poly, and thus the output signal frequency Four may not be equal to the input signal frequency FREE. However, in other cases, the first control value P DIVLOCK may be equal to the second control value Pow, and thus the output signal frequency FOUT may be equal to the input signal frequency FREF.

In embodiments, the circuitry may further comprise a switching arrangement (switching circuitry) configurable to connect the frequency converter electrically to the second comparator in the first mode of operation, thereby providing the second feedback signal to the second comparator in the first mode of operation. The switching arrangement may be configurable to disconnect the -11 -frequency converter electrically from the second comparator in the second mode of operation, thereby not providing the output signal to the second comparator in the second mode of operation.

In embodiments, the circuitry may comprise a switching arrangement (switching circuitry) configurable to connect the frequency converter electrically to the output in the second mode of operation, thereby providing the output signal to the output in the second mode of operation. The switching arrangement may be configurable to disconnect the frequency converter electrically from the output in the first mode of operation, thereby not providing the second feedback signal to the output in the first mode of operation.

As discussed above, the controller is configured to reconfigure the circuitry (e.g. to reconfigure the frequency converter and/or switching arrangement) between operating in the first mode of operation and operating in the second mode of operation. In embodiments, the controller may be configured to reconfigure the circuitry between operating in the first mode of operation and operating in the second mode of operation manually and/or automatically. For example, the controller may be configured to place the circuitry in the first mode of operation when the circuitry is initially powered and/or reset. The circuitry may be reset when the first control value and/or second control value are changed, e.g. in use. The controller may be configured to reconfigure the circuitry from operating in the first mode of operation to operating in the second mode of operation when a particular condition is met. The particular condition may comprise the frequency (and, e.g., phase) of the input signal being substantially the same as the frequency (and, e.g., phase) of the second feedback signal, e.g. -12 -for at least a particular period of time. The particular period of time may be determined by a particular number of periodic cycles of the input signal. The particular number may be, or may be derived from, a count control value provided to the controller. The count control value may be provided to the controller prior to powering or when resetting the circuitry. The count control value may be a programmable or reprogrammable control value. Alternatively, the count control value may be a non-programmable or non-reprogrammable control value. The particular number or count control value may be in the range 10 to 1000. The particular number or count control value may be selected based on the settling time for the circuitry.

In embodiments, the controller may be configured to determine when the particular condition is met. For example, the controller may be configured to receive the input signal and may be configured to count the number of periodic cycles of the input signal to determine whether or not the particular period of time has elapsed. For example, when it is determined that the frequency (and, e.g., phase) of the input signal is substantially the same as the frequency (and, e.g., phase) of the second feedback signal (and in response to that determination), the controller may be configured to receive the input signal and may be configured to count the number of periodic cycles of the input signal to determine whether or not the particular period of time has elapsed.

In embodiments, the controller may be configured to receive an active signal from the second comparator which indicates whether or not the frequency (and, e.g., phase) of the input signal is substantially the same as the frequency (and, e.g., phase) of the second feedback signal, e.g. whether or not the second comparator (e.g. the second charge pump) is providing the second control current. Thus, the second comparator may be configured to provide an active signal that indicates whether or not the frequency (and, e.g., phase) of the input signal is substantially the same as the frequency (and, e.g., phase) of the second feedback signal, e.g. whether or not the second comparator (e.g. the second charge pump) is providing the second control current.

In embodiments, in the first mode of operation, the controller may be configured to provide power to the second comparator. In the second mode of operation, the controller may be configured to power down the second comparator. This can further reduce the power consumed by the circuitry when in the second mode of operation.

In embodiments, the controller may comprise control circuitry, which may be programmable or non-programmable (e.g. hardwired).

The phase-locked loop circuitry may be provided in any desired and suitable form. For example, the circuitry may be provided on a printed circuit board (PCB) as part of a PCB device and/or as part of a packaged device (e.g. microchip). The device may be a surface mount device or a through-hole device. Electrical connections between the various components referred to herein and/or any further components may be provided internally or externally to the device as desired.

According to another aspect of the present invention, there is provided an apparatus comprising the phase-locked loop circuitry or device as described herein in any aspect or embodiment. In embodiments, the phase-locked loop circuitry or device may form part of any apparatus requiring one or more (e.g. plural) output signal frequencies to be synthesised from the input signal. For example, the phase-locked loop circuitry or device may form part of an apparatus configured to synthesise one or more (e.g. plural) output signal frequencies from the input signal. For example, the apparatus may comprise or may be a data communication (e.g. radio) apparatus, such as a transmitter, receiver or transceiver. The apparatus may comprise or may be a portable and/or hand-held apparatus. The apparatus may be a battery-powered apparatus.

According to another aspect of the present invention, there is provided a method of operating phase-locked loop circuitry as described herein in any aspect or embodiment. In embodiments, the method may comprise providing the phase-locked loop circuitry, device and/or apparatus as described herein in any aspect or embodiment. The method may comprise providing the input signal to the first and second comparators. The method may comprise providing the first value and/or second value to the frequency converter. The method may comprise providing the count value to the controller. The method may comprise providing the input signal to the controller. The method may comprise operating the circuitry in the first mode of operation in which the frequency converter generates the second feedback signal from the oscillator signal and provides the second feedback signal to the second comparator. The method may comprise the controller (e.g. in response to determining that the particular condition has been met) reconfiguring the circuitry between operating in the first mode of operation and operating in the second mode of operation. The method may comprise operating the circuitry in the second mode of operation in which the frequency -15 -converter generates the output signal from the oscillator signal and provides the output signal to the output.

By way of example only, embodiments of the invention will now be described in detail with reference being made to the accompanying drawings in which: Figure 1 shows typical phase-locked loop circuitry in which the frequency of an output signal can be set to be a multiple of the frequency of an input signal; Figure 2 shows phase-locked loop circuitry according to an embodiment of the present invention when operating in a first mode of operation; Figure 3 shows the phase-locked loop circuitry according to the embodiment of Figure 2 when operating in a second mode of operation; and Figure 4 shows various timing diagrams during operation of the phase-locked loop circuitry according to the embodiment of Figures 2 and 3.

Figure 1 shows typical phase-locked loop circuitry 100, the features of which are described in detail above and thus will not be repeated here. Such circuitry can suffer from slow settling times, high levels of phase noise, high levels of power consumption, and inflexibility in terms of the output frequencies FOUT that can be generated from the input frequency FREF.

Figures 2 and 3 show phase-locked loop circuitry 200 according to an embodiment of the present invention. In this embodiment, the circuitry 200 comprises a first comparator 202 that comprises a sampling phase comparator and switched current charge pump (PD/CP). The first comparator 202 receives an input signal having a reference frequency FREF and a first feedback signal having an oscillator frequency FouT from a voltage-controlled oscillator (VCO) 204. In this embodiment, the input signal is provided by a crystal oscillator (not shown). The input signal frequency may, for example, be 40 MHz. The first comparator 202 generates a first current control signal CP^ that is based on a comparison of the phases of the input signal and the first feedback signal.

The circuitry 200 further comprises a second comparator 206 that comprises a phase frequency comparator and switched current charge pump (PFD/CP). The second comparator 206 also receives the input signal having the reference frequency FREE and a second feedback signal having a divided frequency F^iv. The second comparator 206 generates a second current control signal CPF^ that is based on a comparison of the phases and frequencies of the input signal and the second feedback signal.

The circuitry 200 further comprises a low pass filter (LPF) 208 that receives a combined control signal CcoM, which is derived by summing the first control signal CP^ and the second control signal CPF^. The LPF 208 outputs a filtered version of the combined control signal CFcom in the form of a tuning voltage to the VCO 204. In this embodiment, the LPF 208 acts to smooth the combined control signal Ccom to create CFCOM, with the level of filtering being chosen to attenuate unwanted harmonics of the reference frequency FREE from the first and second comparator outputs. At the output of the VCO 204, the reference frequency FREF spurs may, for example, be attenuated by at least 70dB.

The VCO 204 receives the filtered (tuning voltage) version of the combined control signal CFCOM and, in accordance with CFCOM, generates an oscillator signal having the oscillator frequency Fvco. The oscillator signal is fed back to the first -17 -comparator 202 as the first feedback signal. This allows the phase of the oscillator signal to be locked to the phase of the input signal.

The oscillator signal is also provided to a frequency converter in the form of a programmable frequency divider 210. In this embodiment, the divider 210 comprises a series of flip-flops with suitable control logic. Depending on the mode of operation, the divider 210 either divides the oscillator signal by a first control value PDIVLOCK to provide the second feedback signal having a frequency Foiv (see Figure 2) or divides the oscillator signal by a second control value PDIV to provide an output signal having a frequency FouT (see Figure 3).

The circuitry 200 further comprises a switching arrangement 212 that either electrically connects the divider 210 to the second comparator 206 in a first mode of operation, thereby providing the second feedback signal to the second comparator 206 in the first mode of operation (see Figure 2), or electrically connects the divider 210 to an output in a second mode of operation, thereby providing the output signal to the output in the second mode of operation (see Figure 3).

The circuitry 200 further comprises a controller 214 that automatically reconfigures the divider 210 and switching arrangement 212 between the modes of operation via a divider control signal CD and a switch control signal Cs respectively. The automatic determination to reconfigure the divider 210 and switching arrangement 212 is made on the basis of an active control signal CACTIVE provided by the second comparator 206, the input signal frequency FREF, and a count control value PcouNT provided to the controller 214.

-18 -As is shown in Figure 2, in the first mode of operation, the divider 210 is configured to divide the oscillator signal frequency Fvco by a first integer control value P^IVLOCK, such that the second feedback signal frequency F^IV equals Fvco I PDIVLOCK. PDIVLOCK may, for example, be 30. The second feedback signal frequency F^IV is then caused to equal the input signal frequency FREF by the first comparator 202 and second comparator 206, such that Fvco / PDIVLOCK is caused to equal FREF. Accordingly, the oscillator signal frequency Fvco is locked at FREF X PDIVLOCK. This allows the oscillator signal frequency Fvco to be set to be an integer multiple of the input signal frequency FREF. Since the first comparator 202 is used to lock and then maintain the relative phases of the input signal and oscillator signal based on the oscillator signal itself, the oscillator signal can settle faster and can have lower phase noise when compared with conventional PLL arrangements.

When the controller 214 determines that the oscillator signal frequency Fvco has stabilized for a number PcouNT of cycles of the input signal, the controller 214, via the switch control signal CD, instructs the divider 210 to generate the output signal from the oscillator signal by dividing the oscillator signal frequency Fvco by a second value PDIV. PcouNT may, for example, be 127, 255 or 477. Pow may, for example, be 10.

At the same time, the controller 214, via the switch control signal Cs, instructs the switching arrangement 212 to output the output signal. Since the oscillator signal frequency Fvco was locked at FREF x PDIVLOCK in the first mode of operation, and the divider 210 now divides the oscillator signal frequency Fvco by the second value PDIv, the output signal frequency FouT is locked at FREF x -19 -PDIVLOCK / PDIV. For example, when FREF = 40 MHz, P DIVLOCK = 30 and Poiv = 10, then Four may be 120 MHz.

Depending on the relative values of P DIVLOCK and P DIV, the output signal frequency Four can accordingly be set to be equal to, a multiple of, or even a fraction of, the input signal frequency FREF. Thus, a wider variety of output signal frequencies Four can be generated when compared with conventional PLL arrangements. Furthermore, since the second comparator 206 is no longer used in the second mode of operation, and may be powered down by the controller 214 in the second mode of operation, power consumption can be reduced significantly in the second mode of operation. This is particularly useful when the circuitry 200 is provided on a PCB as a package device (microchip) for use in a portable hand-held battery-powered radio communication apparatus.

Operation of the circuitry 200 will now be further described with reference to the timing diagrams of Figure 4. Figure 4 firstly shows a timing diagram 400 for the input signal, which has a frequency FREE in both the first and second modes of operation, and thus has a constant period of 1/FREE. As discussed above, the circuitry 200 initially operates in the first mode of operation, in which the divider 210 generates the second feedback signal and the switching arrangement 212 provides the second feedback signal to the second comparator 206. In this regard, Figure 4 also shows a timing diagram 402 for the second feedback signal, which has a frequency Foiv. The cross-hatched region of the timing diagram 402 is intended to indicate the time over which the frequency Foiv and phase of the second feedback signal are adjusted by the second comparator 206 to match the frequency FREE and phase of the input signal. In this regard, Figure 4 also shows -20 -a timing diagram 404 for the active control signal CACTIVE, which is intermittently active as the frequency Foiv is adjusted to match FREF. This process is greatly improved with assistance from the first comparator 202 locking the phases of the input signal and oscillator signal. The frequency Foiv then remains at FREF by virtue of the first comparator 202 locking the phases of the input signal and oscillator signal, and this locking is maintained without needing assistance from the second comparator 206. In this regard, the timing diagram 404 shows that the active control signal CAC-FIVE goes low for a period PCOUNT x 1/FREF when the frequency Foiv is phase-locked at FREE by the first comparator 202. As discussed above, once the controller 214 counts PCOUNT cycles of the input signal, the controller 214 then switches the divider 210 and switching arrangement 212 to the second mode of operation, in which the divider 210 generates the output signal and the switching arrangement 212 provides the output signal to the output. In this regard, Figure 4 also shows a combined timing diagram 406 for the divider control signal Co and switch control signal Cs, which initially indicates that Co/Cs are low (state 1) during the first mode of operation to provide the second feedback signal to the second comparator 206, and then go high (state 2) during the second mode of operation to provide the output signal to the output. Figure 4 finally shows a timing diagram 408 for the output signal, which initially indicates that the output signal is low during the first mode of operation and is then output at a frequency Four equal to FREF x PolyLocK/Poiv.

If it is desired to alter Poiv (but not PDIVLOCK), for example to generate an output signal at a different frequency Four, then the new Poiv DIV can merely be provided to the divider 210 and there is otherwise no need to reconfigure the -21 -circuitry 200. However, if it is desired to alter P DIVLOCK (with or without altering P^iv), for example to generate an output signal at a different frequency Four, then the new P^ivLocK (and possibly a new Pow) can be provided to the divider 210, and the controller 214 resets the circuitry 200 so as to operate in the first mode of operation again, followed by the second mode of operation again in the same manner as described above.

Claims

-22 -CLAIMS1. Phase-locked loop circuitry, the circuitry comprising: a first comparator configured to receive an input signal and a first feedback signal, wherein the first comparator is configured to generate a first control signal 5 based on a comparison of the phases of the input signal and the first feedback signal; a second comparator configured to receive the input signal and a second feedback signal, wherein the second comparator is configured to generate a second control signal based on a comparison of the frequencies of the input 10 signal and the second feedback signal; a controllable oscillator configured to receive a combined control signal derived from the first control signal and the second control signal, wherein the controllable oscillator is configured to generate an oscillator signal in response to the combined control signal, and wherein the controllable oscillator is configured /5 to provide the oscillator signal to the first comparator as the first feedback signal; a frequency converter configured to receive the oscillator signal, wherein the frequency converter is configurable to generate the second feedback signal from the oscillator signal in a first mode of operation, and wherein the frequency converter is configurable to generate an output signal from the oscillator signal in 20 a second mode of operation; and a controller configured to reconfigure the circuitry between operating in the first mode of operation in which the second feedback signal is generated and provided to the second comparator to set the frequency of the oscillator signal -23 -and operating in a second mode of operation in which the output signal is generated and provided to an output.
2. The circuitry as claimed in claim 1, wherein the circuitry further comprises a loop filter configured to receive the combined control signal and output a filtered version of the combined control signal to the controllable oscillator.
3. The circuitry as claimed in claim 1 or 2, wherein the frequency converter comprises a frequency divider.
4. The circuitry as claimed in claim 1, 2 or 3, wherein the relationship between the frequencies of the oscillator signal and the second feedback signal is determined by a first control value that controls the frequency converter in the first mode of operation.
5. The circuitry as claimed in any one of the preceding claims, wherein the relationship between the frequencies of the oscillator signal and the output signal is determined by a second control value that controls the frequency converter in 15 the second mode of operation.
6. The circuitry as claimed in any one of the preceding claims, wherein the circuitry comprises a switching arrangement configurable to connect the frequency converter electrically to the second comparator in the first mode of operation, thereby providing the second feedback signal to the second comparator in the first mode of operation.
7. The circuitry as claimed in any one of the preceding claims, wherein the circuitry comprises a switching arrangement configurable to connect the frequency converter electrically to the output in the second mode of operation, thereby providing the output signal to the output in the second mode of operation.
-24 - 8. The circuitry as claimed in any one of the preceding claims, wherein the controller is configured to reconfigure the circuitry automatically between operating in the first mode of operation and operating in the second mode of operation.
9. The circuitry as claimed in any one of the preceding claims, wherein the controller is configured to reconfigure the circuitry from operating in the first mode of operation to operating in the second mode of operation when a particular condition is met.
10. The circuitry as claimed in claim 9, wherein the particular condition comprises the frequency of the input signal being substantially the same as the frequency of the second feedback signal.
11. The circuitry as claimed in claim 9 or 10, wherein the particular condition comprises the frequency of the input signal being substantially the same as the frequency of the second feedback signal for at least a particular period of time.
12. The circuitry as claimed in claim 11, wherein the particular period of time is determined by a particular number of periodic cycles of the input signal.
13. The circuitry as claimed in claim 12, wherein the particular number is, or is derived from, a count control value provided to the controller.
14. The circuitry as claimed in claim 11, 12 or 13, wherein the controller is configured to receive the input signal and is configured to count the number of periodic cycles of the input signal to determine whether or not the particular period of time has elapsed.
15. The circuitry as claimed in any one of the preceding claims, wherein the controller is configured to receive an active signal from the second comparator -25 -which indicates whether or not the frequency of the input signal is substantially the same as the frequency of the second feedback signal.
16. An apparatus comprising the phase-locked loop circuitry as claimed in any one of the preceding claims, wherein the apparatus is configured to synthesise one or more output signal frequencies from the input signal using the circuitry.
17. The apparatus as claimed in claim 16, wherein the apparatus comprises a data communication apparatus.
18. The apparatus as claimed in claim 16 or 17, wherein the apparatus comprises a portable and/or hand-held apparatus.
19. The apparatus as claimed in claim 16, 17 or 18, wherein the apparatus comprises a battery-powered apparatus.
20. A method of operating the phase-locked loop circuitry as claimed in any one of claims 1-15, the method comprising operating the circuitry in the first mode of operation in which the frequency converter generates the second feedback signal from the oscillator signal and provides the second feedback signal to the second comparator, reconfiguring the circuitry between operating in the first mode of operation and operating in the second mode of operation. and operating the circuitry in the second mode of operation in which the frequency converter generates the output signal from the oscillator signal and provides the output signal to the output.